1 /* 2 * Copyright 1996 Massachusetts Institute of Technology 3 * 4 * Permission to use, copy, modify, and distribute this software and 5 * its documentation for any purpose and without fee is hereby 6 * granted, provided that both the above copyright notice and this 7 * permission notice appear in all copies, that both the above 8 * copyright notice and this permission notice appear in all 9 * supporting documentation, and that the name of M.I.T. not be used 10 * in advertising or publicity pertaining to distribution of the 11 * software without specific, written prior permission. M.I.T. makes 12 * no representations about the suitability of this software for any 13 * purpose. It is provided "as is" without express or implied 14 * warranty. 15 * 16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS 17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, 18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT 20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $Id$ 30 */ 31 32 /* 33 * Interface to performance-monitoring counters for Intel Pentium and 34 * Pentium Pro CPUs. 35 */ 36 37 #ifndef _MACHINE_PERFMON_H_ 38 #define _MACHINE_PERFMON_H_ 1 39 40 #ifndef KERNEL 41 #include <sys/ioccom.h> 42 #endif 43 44 #define NPMC 2 45 46 #define PMIOSETUP _IOW('5', 1, struct pmc) 47 #define PMIOGET _IOWR('5', 7, struct pmc) 48 #define PMIOSTART _IOW('5', 2, int) 49 #define PMIOSTOP _IOW('5', 3, int) 50 #define PMIOREAD _IOWR('5', 4, struct pmc_data) 51 #define PMIORESET _IOW('5', 5, int) 52 #define PMIOTSTAMP _IOR('5', 6, struct pmc_tstamp) 53 54 struct pmc { 55 int pmc_num; 56 union { 57 struct { 58 unsigned char pmcus_event; 59 unsigned char pmcus_unit; 60 unsigned char pmcus_flags; 61 unsigned char pmcus_mask; 62 } pmcu_s; 63 unsigned int pmcu_val; 64 } pmc_pmcu; 65 }; 66 67 #define PMC_ALL (-1) 68 69 #define pmc_event pmc_pmcu.pmcu_s.pmcus_event 70 #define pmc_unit pmc_pmcu.pmcu_s.pmcus_unit 71 #define pmc_flags pmc_pmcu.pmcu_s.pmcus_flags 72 #define pmc_mask pmc_pmcu.pmcu_s.pmcus_mask 73 #define pmc_val pmc_pmcu.pmcu_val 74 75 #define PMCF_USR 0x01 /* count events in user mode */ 76 #define PMCF_OS 0x02 /* count events in kernel mode */ 77 #define PMCF_E 0x04 /* use edge-detection mode */ 78 #define PMCF_PC 0x08 /* PMx output pin control */ 79 #define PMCF_INT 0x10 /* APIC interrupt enable (do not use) */ 80 #define PMCF_EN 0x40 /* enable counters */ 81 #define PMCF_INV 0x80 /* invert counter mask comparison */ 82 83 #define PMCF_SYS_FLAGS (PMCF_INT | PMCF_EN) /* user cannot set */ 84 85 struct pmc_data { 86 int pmcd_num; 87 quad_t pmcd_value; 88 }; 89 90 struct pmc_tstamp { 91 int pmct_rate; 92 quad_t pmct_value; 93 }; 94 95 #ifndef KERNEL 96 97 #define _PATH_PERFMON "/dev/perfmon" 98 99 #else 100 101 /* 102 * Intra-kernel interface to performance monitoring counters 103 */ 104 void perfmon_init __P((void)); 105 int perfmon_avail __P((void)); 106 int perfmon_setup __P((int, unsigned int)); 107 int perfmon_get __P((int, unsigned int *)); 108 int perfmon_fini __P((int)); 109 int perfmon_start __P((int)); 110 int perfmon_stop __P((int)); 111 int perfmon_read __P((int, quad_t *)); 112 int perfmon_reset __P((int)); 113 114 /* 115 * We pass the device down this interface because in the future 116 * the different counters might be accessed through separate devices. 117 */ 118 int perfmon_close __P((dev_t, int, int, struct proc *)); 119 int perfmon_open __P((dev_t, int, int, struct proc *)); 120 int perfmon_ioctl __P((dev_t, int, caddr_t, int, struct proc *)); 121 #endif /* KERNEL */ 122 123 /* 124 * Pentium Pro performance counters, from Appendix B. 125 */ 126 /* Data Cache Unit */ 127 #define PMC6_DATA_MEM_REFS 0x43 128 #define PMC6_DCU_LINES_IN 0x45 129 #define PMC6_DCU_M_LINES_IN 0x46 130 #define PMC6_DCU_M_LINES_OUT 0x47 131 #define PMC6_DCU_MISS_OUTSTANDING 0x48 132 133 /* Instruction Fetch Unit */ 134 #define PMC6_IFU_IFETCH 0x80 135 #define PMC6_IFU_IFETCH_MISS 0x81 136 #define PMC6_ITLB_MISS 0x85 137 #define PMC6_IFU_MEM_STALL 0x86 138 #define PMC6_ILD_STALL 0x87 139 140 /* L2 Cache */ 141 #define PMC6_L2_IFETCH 0x28 /* MESI */ 142 #define PMC6_L2_LD 0x29 /* MESI */ 143 #define PMC6_L2_ST 0x2a /* MESI */ 144 #define PMC6_L2_LINES_IN 0x24 145 #define PMC6_L2_LINES_OUT 0x26 146 #define PMC6_L2_M_LINES_INM 0x25 147 #define PMC6_L2_M_LINES_OUTM 0x27 148 #define PMC6_L2_RQSTS 0x2e /* MESI */ 149 #define PMC6_L2_ADS 0x21 150 #define PMC6_L2_DBUS_BUSY 0x22 151 #define PMC6_L2_DBUS_BUSY_RD 0x23 152 153 /* External Bus Logic */ 154 #define PMC6_BUS_DRDY_CLOCKS 0x62 155 #define PMC6_BUS_LOCK_CLOCKS 0x63 156 #define PMC6_BUS_REQ_OUTSTANDING 0x60 157 #define PMC6_BUS_TRAN_BRD 0x65 158 #define PMC6_BUS_TRAN_RFO 0x66 159 #define PMC6_BUS_TRAN_WB 0x67 160 #define PMC6_BUS_TRAN_IFETCH 0x68 161 #define PMC6_BUS_TRAN_INVAL 0x69 162 #define PMC6_BUS_TRAN_PWR 0x6a 163 #define PMC6_BUS_TRAN_P 0x6b 164 #define PMC6_BUS_TRAN_IO 0x6c 165 #define PMC6_BUS_TRAN_DEF 0x6d 166 #define PMC6_BUS_TRAN_BURST 0x6e 167 #define PMC6_BUS_TRAN_ANY 0x70 168 #define PMC6_BUS_TRAN_MEM 0x6f 169 #define PMC6_BUS_DATA_RCV 0x64 170 #define PMC6_BUS_BNR_DRV 0x61 171 #define PMC6_BUS_HIT_DRV 0x7a 172 #define PMC6_BUS_HITM_DRV 0x7b 173 #define PMC6_BUS_SNOOP_STALL 0x7e 174 175 /* Floating Point Unit */ 176 #define PMC6_FLOPS 0xc1 /* counter 0 only */ 177 #define PMC6_FP_COMP_OPS_EXE 0x10 /* counter 0 only */ 178 #define PMC6_FP_ASSIST 0x11 /* counter 1 only */ 179 #define PMC6_MUL 0x12 /* counter 1 only */ 180 #define PMC6_DIV 0x13 /* counter 1 only */ 181 #define PMC6_CYCLES_DIV_BUSY 0x14 /* counter 0 only */ 182 183 /* Memory Ordering */ 184 #define PMC6_LD_BLOCKS 0x03 185 #define PMC6_SB_DRAINS 0x04 186 #define PMC6_MISALIGN_MEM_REF 0x05 187 188 /* Instruction Decoding and Retirement */ 189 #define PMC6_INST_RETIRED 0xc0 190 #define PMC6_UOPS_RETIRED 0xc2 191 #define PMC6_INST_DECODER 0xd0 /* (sic) */ 192 193 /* Interrupts */ 194 #define PMC6_HW_INT_RX 0xc8 195 #define PMC6_CYCLES_INT_MASKED 0xc6 196 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 197 198 /* Branches */ 199 #define PMC6_BR_INST_RETIRED 0xc4 200 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 201 #define PMC6_BR_TAKEN_RETIRED 0xc9 202 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 203 #define PMC6_BR_INST_DECODED 0xe0 204 #define PMC6_BTB_MISSES 0xe2 205 #define PMC6_BR_BOGUS 0xe4 206 #define PMC6_BACLEARS 0xe6 207 208 /* Stalls */ 209 #define PMC6_RESOURCE_STALLS 0xa2 210 #define PMC6_PARTIAL_RAT_STALLS 0xd2 211 212 /* Segment Register Loads */ 213 #define PMC6_SEGMENT_REG_LOADS 0x06 214 215 /* Clocks */ 216 #define PMC6_CPU_CLK_UNHALTED 0x79 217 218 /* 219 * Pentium Performance Counters 220 * This list comes from the Harvard people, not Intel. 221 */ 222 #define PMC5_DATA_READ 0 223 #define PMC5_DATA_WRITE 1 224 #define PMC5_DATA_TLB_MISS 2 225 #define PMC5_DATA_READ_MISS 3 226 #define PMC5_DATA_WRITE_MISS 4 227 #define PMC5_WRITE_M_E 5 228 #define PMC5_DATA_LINES_WBACK 6 229 #define PMC5_DATA_CACHE_SNOOP 7 230 #define PMC5_DATA_CACHE_SNOOP_HIT 8 231 #define PMC5_MEM_ACCESS_BOTH 9 232 #define PMC5_BANK_CONFLICTS 10 233 #define PMC5_MISALIGNED_DATA 11 234 #define PMC5_INST_READ 12 235 #define PMC5_INST_TLB_MISS 13 236 #define PMC5_INST_CACHE_MISS 14 237 #define PMC5_SEGMENT_REG_LOAD 15 238 #define PMC5_BRANCHES 18 239 #define PMC5_BTB_HITS 19 240 #define PMC5_BRANCH_TAKEN 20 241 #define PMC5_PIPELINE_FLUSH 21 242 #define PMC5_INST_EXECUTED 22 243 #define PMC5_INST_EXECUTED_V 23 244 #define PMC5_BUS_UTILIZATION 24 245 #define PMC5_WRITE_BACKUP_STALL 25 246 #define PMC5_DATA_READ_STALL 26 247 #define PMC5_WRITE_E_M_STALL 27 248 #define PMC5_LOCKED_BUS 28 249 #define PMC5_IO_CYCLE 29 250 #define PMC5_NONCACHE_MEMORY 30 251 #define PMC5_ADDR_GEN_INTERLOCK 31 252 #define PMC5_FLOPS 34 253 #define PMC5_BP0_MATCH 35 254 #define PMC5_BP1_MATCH 36 255 #define PMC5_BP2_MATCH 37 256 #define PMC5_BP3_MATCH 38 257 #define PMC5_HW_INTR 39 258 #define PMC5_DATA_RW 40 259 #define PMC5_DATA_RW_MISS 41 260 261 #endif /* _MACHINE_PERFMON_H_ */ 262