1 /*- 2 * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 35 #include <sys/param.h> 36 #include <sys/types.h> 37 #include <sys/bus.h> 38 #include <sys/eventhandler.h> 39 #include <sys/sockio.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sysctl.h> 50 #include <sys/syslog.h> 51 #include <sys/taskqueue.h> 52 #include <sys/limits.h> 53 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_pcb.h> 65 #include <netinet/tcp_lro.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/if_ether.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <vm/vm.h> 76 #include <vm/pmap.h> 77 78 #include <dev/led/led.h> 79 #include <dev/pci/pcireg.h> 80 #include <dev/pci/pcivar.h> 81 #include <dev/pci/pci_private.h> 82 83 #include <net/iflib.h> 84 85 #include "ifdi_if.h" 86 87 #if defined(__i386__) || defined(__amd64__) 88 #include <sys/memdesc.h> 89 #include <machine/bus.h> 90 #include <machine/md_var.h> 91 #include <machine/specialreg.h> 92 #include <x86/include/busdma_impl.h> 93 #include <x86/iommu/busdma_dmar.h> 94 #endif 95 96 #include <sys/bitstring.h> 97 /* 98 * enable accounting of every mbuf as it comes in to and goes out of 99 * iflib's software descriptor references 100 */ 101 #define MEMORY_LOGGING 0 102 /* 103 * Enable mbuf vectors for compressing long mbuf chains 104 */ 105 106 /* 107 * NB: 108 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 109 * we prefetch needs to be determined by the time spent in m_free vis a vis 110 * the cost of a prefetch. This will of course vary based on the workload: 111 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 112 * is quite expensive, thus suggesting very little prefetch. 113 * - small packet forwarding which is just returning a single mbuf to 114 * UMA will typically be very fast vis a vis the cost of a memory 115 * access. 116 */ 117 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 static MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 struct iflib_txq; 132 typedef struct iflib_txq *iflib_txq_t; 133 struct iflib_rxq; 134 typedef struct iflib_rxq *iflib_rxq_t; 135 struct iflib_fl; 136 typedef struct iflib_fl *iflib_fl_t; 137 138 struct iflib_ctx; 139 140 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 141 142 typedef struct iflib_filter_info { 143 driver_filter_t *ifi_filter; 144 void *ifi_filter_arg; 145 struct grouptask *ifi_task; 146 void *ifi_ctx; 147 } *iflib_filter_info_t; 148 149 struct iflib_ctx { 150 KOBJ_FIELDS; 151 /* 152 * Pointer to hardware driver's softc 153 */ 154 void *ifc_softc; 155 device_t ifc_dev; 156 if_t ifc_ifp; 157 158 cpuset_t ifc_cpus; 159 if_shared_ctx_t ifc_sctx; 160 struct if_softc_ctx ifc_softc_ctx; 161 162 struct mtx ifc_mtx; 163 164 uint16_t ifc_nhwtxqs; 165 uint16_t ifc_nhwrxqs; 166 167 iflib_txq_t ifc_txqs; 168 iflib_rxq_t ifc_rxqs; 169 uint32_t ifc_if_flags; 170 uint32_t ifc_flags; 171 uint32_t ifc_max_fl_buf_size; 172 int ifc_in_detach; 173 174 int ifc_link_state; 175 int ifc_link_irq; 176 int ifc_watchdog_events; 177 struct cdev *ifc_led_dev; 178 struct resource *ifc_msix_mem; 179 180 struct if_irq ifc_legacy_irq; 181 struct grouptask ifc_admin_task; 182 struct grouptask ifc_vflr_task; 183 struct iflib_filter_info ifc_filter_info; 184 struct ifmedia ifc_media; 185 186 struct sysctl_oid *ifc_sysctl_node; 187 uint16_t ifc_sysctl_ntxqs; 188 uint16_t ifc_sysctl_nrxqs; 189 uint16_t ifc_sysctl_qs_eq_override; 190 uint16_t ifc_sysctl_rx_budget; 191 192 qidx_t ifc_sysctl_ntxds[8]; 193 qidx_t ifc_sysctl_nrxds[8]; 194 struct if_txrx ifc_txrx; 195 #define isc_txd_encap ifc_txrx.ift_txd_encap 196 #define isc_txd_flush ifc_txrx.ift_txd_flush 197 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 198 #define isc_rxd_available ifc_txrx.ift_rxd_available 199 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 200 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 201 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 202 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 203 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 204 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 205 eventhandler_tag ifc_vlan_attach_event; 206 eventhandler_tag ifc_vlan_detach_event; 207 uint8_t ifc_mac[ETHER_ADDR_LEN]; 208 char ifc_mtx_name[16]; 209 }; 210 211 212 void * 213 iflib_get_softc(if_ctx_t ctx) 214 { 215 216 return (ctx->ifc_softc); 217 } 218 219 device_t 220 iflib_get_dev(if_ctx_t ctx) 221 { 222 223 return (ctx->ifc_dev); 224 } 225 226 if_t 227 iflib_get_ifp(if_ctx_t ctx) 228 { 229 230 return (ctx->ifc_ifp); 231 } 232 233 struct ifmedia * 234 iflib_get_media(if_ctx_t ctx) 235 { 236 237 return (&ctx->ifc_media); 238 } 239 240 void 241 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 242 { 243 244 bcopy(mac, ctx->ifc_mac, ETHER_ADDR_LEN); 245 } 246 247 if_softc_ctx_t 248 iflib_get_softc_ctx(if_ctx_t ctx) 249 { 250 251 return (&ctx->ifc_softc_ctx); 252 } 253 254 if_shared_ctx_t 255 iflib_get_sctx(if_ctx_t ctx) 256 { 257 258 return (ctx->ifc_sctx); 259 } 260 261 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 262 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 263 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 264 265 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 266 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 267 268 #define RX_SW_DESC_MAP_CREATED (1 << 0) 269 #define TX_SW_DESC_MAP_CREATED (1 << 1) 270 #define RX_SW_DESC_INUSE (1 << 3) 271 #define TX_SW_DESC_MAPPED (1 << 4) 272 273 #define M_TOOBIG M_PROTO1 274 275 typedef struct iflib_sw_rx_desc_array { 276 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 277 struct mbuf **ifsd_m; /* pkthdr mbufs */ 278 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 279 uint8_t *ifsd_flags; 280 } iflib_rxsd_array_t; 281 282 typedef struct iflib_sw_tx_desc_array { 283 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 284 struct mbuf **ifsd_m; /* pkthdr mbufs */ 285 uint8_t *ifsd_flags; 286 } if_txsd_vec_t; 287 288 289 /* magic number that should be high enough for any hardware */ 290 #define IFLIB_MAX_TX_SEGS 128 291 /* bnxt supports 64 with hardware LRO enabled */ 292 #define IFLIB_MAX_RX_SEGS 64 293 #define IFLIB_RX_COPY_THRESH 128 294 #define IFLIB_MAX_RX_REFRESH 32 295 /* The minimum descriptors per second before we start coalescing */ 296 #define IFLIB_MIN_DESC_SEC 16384 297 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 298 #define IFLIB_QUEUE_IDLE 0 299 #define IFLIB_QUEUE_HUNG 1 300 #define IFLIB_QUEUE_WORKING 2 301 /* maximum number of txqs that can share an rx interrupt */ 302 #define IFLIB_MAX_TX_SHARED_INTR 4 303 304 /* this should really scale with ring size - this is a fairly arbitrary value */ 305 #define TX_BATCH_SIZE 32 306 307 #define IFLIB_RESTART_BUDGET 8 308 309 #define IFC_LEGACY 0x001 310 #define IFC_QFLUSH 0x002 311 #define IFC_MULTISEG 0x004 312 #define IFC_DMAR 0x008 313 #define IFC_SC_ALLOCATED 0x010 314 #define IFC_INIT_DONE 0x020 315 #define IFC_PREFETCH 0x040 316 #define IFC_DO_RESET 0x080 317 #define IFC_CHECK_HUNG 0x100 318 319 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 320 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 321 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 322 struct iflib_txq { 323 qidx_t ift_in_use; 324 qidx_t ift_cidx; 325 qidx_t ift_cidx_processed; 326 qidx_t ift_pidx; 327 uint8_t ift_gen; 328 uint8_t ift_br_offset; 329 uint16_t ift_npending; 330 uint16_t ift_db_pending; 331 uint16_t ift_rs_pending; 332 /* implicit pad */ 333 uint8_t ift_txd_size[8]; 334 uint64_t ift_processed; 335 uint64_t ift_cleaned; 336 uint64_t ift_cleaned_prev; 337 #if MEMORY_LOGGING 338 uint64_t ift_enqueued; 339 uint64_t ift_dequeued; 340 #endif 341 uint64_t ift_no_tx_dma_setup; 342 uint64_t ift_no_desc_avail; 343 uint64_t ift_mbuf_defrag_failed; 344 uint64_t ift_mbuf_defrag; 345 uint64_t ift_map_failed; 346 uint64_t ift_txd_encap_efbig; 347 uint64_t ift_pullups; 348 349 struct mtx ift_mtx; 350 struct mtx ift_db_mtx; 351 352 /* constant values */ 353 if_ctx_t ift_ctx; 354 struct ifmp_ring *ift_br; 355 struct grouptask ift_task; 356 qidx_t ift_size; 357 uint16_t ift_id; 358 struct callout ift_timer; 359 360 if_txsd_vec_t ift_sds; 361 uint8_t ift_qstatus; 362 uint8_t ift_closed; 363 uint8_t ift_update_freq; 364 struct iflib_filter_info ift_filter_info; 365 bus_dma_tag_t ift_desc_tag; 366 bus_dma_tag_t ift_tso_desc_tag; 367 iflib_dma_info_t ift_ifdi; 368 #define MTX_NAME_LEN 16 369 char ift_mtx_name[MTX_NAME_LEN]; 370 char ift_db_mtx_name[MTX_NAME_LEN]; 371 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 372 #ifdef IFLIB_DIAGNOSTICS 373 uint64_t ift_cpu_exec_count[256]; 374 #endif 375 } __aligned(CACHE_LINE_SIZE); 376 377 struct iflib_fl { 378 qidx_t ifl_cidx; 379 qidx_t ifl_pidx; 380 qidx_t ifl_credits; 381 uint8_t ifl_gen; 382 uint8_t ifl_rxd_size; 383 #if MEMORY_LOGGING 384 uint64_t ifl_m_enqueued; 385 uint64_t ifl_m_dequeued; 386 uint64_t ifl_cl_enqueued; 387 uint64_t ifl_cl_dequeued; 388 #endif 389 /* implicit pad */ 390 391 bitstr_t *ifl_rx_bitmap; 392 qidx_t ifl_fragidx; 393 /* constant */ 394 qidx_t ifl_size; 395 uint16_t ifl_buf_size; 396 uint16_t ifl_cltype; 397 uma_zone_t ifl_zone; 398 iflib_rxsd_array_t ifl_sds; 399 iflib_rxq_t ifl_rxq; 400 uint8_t ifl_id; 401 bus_dma_tag_t ifl_desc_tag; 402 iflib_dma_info_t ifl_ifdi; 403 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 404 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 405 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 406 } __aligned(CACHE_LINE_SIZE); 407 408 static inline qidx_t 409 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 410 { 411 qidx_t used; 412 413 if (pidx > cidx) 414 used = pidx - cidx; 415 else if (pidx < cidx) 416 used = size - cidx + pidx; 417 else if (gen == 0 && pidx == cidx) 418 used = 0; 419 else if (gen == 1 && pidx == cidx) 420 used = size; 421 else 422 panic("bad state"); 423 424 return (used); 425 } 426 427 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 428 429 #define IDXDIFF(head, tail, wrap) \ 430 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 431 432 struct iflib_rxq { 433 /* If there is a separate completion queue - 434 * these are the cq cidx and pidx. Otherwise 435 * these are unused. 436 */ 437 qidx_t ifr_size; 438 qidx_t ifr_cq_cidx; 439 qidx_t ifr_cq_pidx; 440 uint8_t ifr_cq_gen; 441 uint8_t ifr_fl_offset; 442 443 if_ctx_t ifr_ctx; 444 iflib_fl_t ifr_fl; 445 uint64_t ifr_rx_irq; 446 uint16_t ifr_id; 447 uint8_t ifr_lro_enabled; 448 uint8_t ifr_nfl; 449 uint8_t ifr_ntxqirq; 450 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 451 struct lro_ctrl ifr_lc; 452 struct grouptask ifr_task; 453 struct iflib_filter_info ifr_filter_info; 454 iflib_dma_info_t ifr_ifdi; 455 456 /* dynamically allocate if any drivers need a value substantially larger than this */ 457 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 458 #ifdef IFLIB_DIAGNOSTICS 459 uint64_t ifr_cpu_exec_count[256]; 460 #endif 461 } __aligned(CACHE_LINE_SIZE); 462 463 typedef struct if_rxsd { 464 caddr_t *ifsd_cl; 465 struct mbuf **ifsd_m; 466 iflib_fl_t ifsd_fl; 467 qidx_t ifsd_cidx; 468 } *if_rxsd_t; 469 470 /* multiple of word size */ 471 #ifdef __LP64__ 472 #define PKT_INFO_SIZE 6 473 #define RXD_INFO_SIZE 5 474 #define PKT_TYPE uint64_t 475 #else 476 #define PKT_INFO_SIZE 11 477 #define RXD_INFO_SIZE 8 478 #define PKT_TYPE uint32_t 479 #endif 480 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 481 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 482 483 typedef struct if_pkt_info_pad { 484 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 485 } *if_pkt_info_pad_t; 486 typedef struct if_rxd_info_pad { 487 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 488 } *if_rxd_info_pad_t; 489 490 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 491 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 492 493 494 static inline void 495 pkt_info_zero(if_pkt_info_t pi) 496 { 497 if_pkt_info_pad_t pi_pad; 498 499 pi_pad = (if_pkt_info_pad_t)pi; 500 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 501 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 502 #ifndef __LP64__ 503 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 504 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 505 #endif 506 } 507 508 static inline void 509 rxd_info_zero(if_rxd_info_t ri) 510 { 511 if_rxd_info_pad_t ri_pad; 512 int i; 513 514 ri_pad = (if_rxd_info_pad_t)ri; 515 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 516 ri_pad->rxd_val[i] = 0; 517 ri_pad->rxd_val[i+1] = 0; 518 ri_pad->rxd_val[i+2] = 0; 519 ri_pad->rxd_val[i+3] = 0; 520 } 521 #ifdef __LP64__ 522 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 523 #endif 524 } 525 526 /* 527 * Only allow a single packet to take up most 1/nth of the tx ring 528 */ 529 #define MAX_SINGLE_PACKET_FRACTION 12 530 #define IF_BAD_DMA (bus_addr_t)-1 531 532 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 533 534 #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) 535 536 #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) 537 #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) 538 #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) 539 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 545 /* Our boot-time initialization hook */ 546 static int iflib_module_event_handler(module_t, int, void *); 547 548 static moduledata_t iflib_moduledata = { 549 "iflib", 550 iflib_module_event_handler, 551 NULL 552 }; 553 554 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 555 MODULE_VERSION(iflib, 1); 556 557 MODULE_DEPEND(iflib, pci, 1, 1, 1); 558 MODULE_DEPEND(iflib, ether, 1, 1, 1); 559 560 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 561 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 562 563 #ifndef IFLIB_DEBUG_COUNTERS 564 #ifdef INVARIANTS 565 #define IFLIB_DEBUG_COUNTERS 1 566 #else 567 #define IFLIB_DEBUG_COUNTERS 0 568 #endif /* !INVARIANTS */ 569 #endif 570 571 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, 572 "iflib driver parameters"); 573 574 /* 575 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 576 */ 577 static int iflib_min_tx_latency = 0; 578 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 579 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 580 static int iflib_no_tx_batch = 0; 581 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 582 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 583 584 585 #if IFLIB_DEBUG_COUNTERS 586 587 static int iflib_tx_seen; 588 static int iflib_tx_sent; 589 static int iflib_tx_encap; 590 static int iflib_rx_allocs; 591 static int iflib_fl_refills; 592 static int iflib_fl_refills_large; 593 static int iflib_tx_frees; 594 595 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 596 &iflib_tx_seen, 0, "# tx mbufs seen"); 597 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 598 &iflib_tx_sent, 0, "# tx mbufs sent"); 599 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 600 &iflib_tx_encap, 0, "# tx mbufs encapped"); 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 602 &iflib_tx_frees, 0, "# tx frees"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 604 &iflib_rx_allocs, 0, "# rx allocations"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 606 &iflib_fl_refills, 0, "# refills"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 608 &iflib_fl_refills_large, 0, "# large refills"); 609 610 611 static int iflib_txq_drain_flushing; 612 static int iflib_txq_drain_oactive; 613 static int iflib_txq_drain_notready; 614 static int iflib_txq_drain_encapfail; 615 616 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 617 &iflib_txq_drain_flushing, 0, "# drain flushes"); 618 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 619 &iflib_txq_drain_oactive, 0, "# drain oactives"); 620 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 621 &iflib_txq_drain_notready, 0, "# drain notready"); 622 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, 623 &iflib_txq_drain_encapfail, 0, "# drain encap fails"); 624 625 626 static int iflib_encap_load_mbuf_fail; 627 static int iflib_encap_txq_avail_fail; 628 static int iflib_encap_txd_encap_fail; 629 630 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 631 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 632 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 633 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 635 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 636 637 static int iflib_task_fn_rxs; 638 static int iflib_rx_intr_enables; 639 static int iflib_fast_intrs; 640 static int iflib_intr_link; 641 static int iflib_intr_msix; 642 static int iflib_rx_unavail; 643 static int iflib_rx_ctx_inactive; 644 static int iflib_rx_zero_len; 645 static int iflib_rx_if_input; 646 static int iflib_rx_mbuf_null; 647 static int iflib_rxd_flush; 648 649 static int iflib_verbose_debug; 650 651 SYSCTL_INT(_net_iflib, OID_AUTO, intr_link, CTLFLAG_RD, 652 &iflib_intr_link, 0, "# intr link calls"); 653 SYSCTL_INT(_net_iflib, OID_AUTO, intr_msix, CTLFLAG_RD, 654 &iflib_intr_msix, 0, "# intr msix calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# rx intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 660 &iflib_fast_intrs, 0, "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 662 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_zero_len, CTLFLAG_RD, 666 &iflib_rx_zero_len, 0, "# times rxeof saw zero len mbuf"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 668 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, 670 &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); 671 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 672 &iflib_rxd_flush, 0, "# times rxd_flush called"); 673 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 674 &iflib_verbose_debug, 0, "enable verbose debugging"); 675 676 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 677 static void 678 iflib_debug_reset(void) 679 { 680 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 681 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 682 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 683 iflib_txq_drain_notready = iflib_txq_drain_encapfail = 684 iflib_encap_load_mbuf_fail = iflib_encap_txq_avail_fail = 685 iflib_encap_txd_encap_fail = iflib_task_fn_rxs = iflib_rx_intr_enables = 686 iflib_fast_intrs = iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = 687 iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = 688 iflib_rx_mbuf_null = iflib_rxd_flush = 0; 689 } 690 691 #else 692 #define DBG_COUNTER_INC(name) 693 static void iflib_debug_reset(void) {} 694 #endif 695 696 697 698 #define IFLIB_DEBUG 0 699 700 static void iflib_tx_structures_free(if_ctx_t ctx); 701 static void iflib_rx_structures_free(if_ctx_t ctx); 702 static int iflib_queues_alloc(if_ctx_t ctx); 703 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 704 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 705 static int iflib_qset_structures_setup(if_ctx_t ctx); 706 static int iflib_msix_init(if_ctx_t ctx); 707 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); 708 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 709 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 710 static int iflib_register(if_ctx_t); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_stop(if_ctx_t ctx); 717 static void iflib_if_init_locked(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 #ifdef DEV_NETMAP 723 #include <sys/selinfo.h> 724 #include <net/netmap.h> 725 #include <dev/netmap/netmap_kern.h> 726 727 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 728 729 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 730 731 /* 732 * device-specific sysctl variables: 733 * 734 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 735 * During regular operations the CRC is stripped, but on some 736 * hardware reception of frames not multiple of 64 is slower, 737 * so using crcstrip=0 helps in benchmarks. 738 * 739 * iflib_rx_miss, iflib_rx_miss_bufs: 740 * count packets that might be missed due to lost interrupts. 741 */ 742 SYSCTL_DECL(_dev_netmap); 743 /* 744 * The xl driver by default strips CRCs and we do not override it. 745 */ 746 747 int iflib_crcstrip = 1; 748 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 749 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on rx frames"); 750 751 int iflib_rx_miss, iflib_rx_miss_bufs; 752 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 753 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed rx intr"); 754 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 755 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed rx intr bufs"); 756 757 /* 758 * Register/unregister. We are already under netmap lock. 759 * Only called on the first register or the last unregister. 760 */ 761 static int 762 iflib_netmap_register(struct netmap_adapter *na, int onoff) 763 { 764 struct ifnet *ifp = na->ifp; 765 if_ctx_t ctx = ifp->if_softc; 766 int status; 767 768 CTX_LOCK(ctx); 769 IFDI_INTR_DISABLE(ctx); 770 771 /* Tell the stack that the interface is no longer active */ 772 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 773 774 if (!CTX_IS_VF(ctx)) 775 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 776 777 /* enable or disable flags and callbacks in na and ifp */ 778 if (onoff) { 779 nm_set_native_flags(na); 780 } else { 781 nm_clear_native_flags(na); 782 } 783 iflib_stop(ctx); 784 iflib_init_locked(ctx); 785 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 786 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 787 if (status) 788 nm_clear_native_flags(na); 789 CTX_UNLOCK(ctx); 790 return (status); 791 } 792 793 static void 794 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 795 { 796 iflib_fl_t fl; 797 798 fl = &rxq->ifr_fl[flid]; 799 iru->iru_paddrs = fl->ifl_bus_addrs; 800 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 801 iru->iru_idxs = fl->ifl_rxd_idxs; 802 iru->iru_qsidx = rxq->ifr_id; 803 iru->iru_buf_size = fl->ifl_buf_size; 804 iru->iru_flidx = fl->ifl_id; 805 } 806 807 static int 808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 809 { 810 struct netmap_adapter *na = kring->na; 811 u_int const lim = kring->nkr_num_slots - 1; 812 u_int head = kring->rhead; 813 struct netmap_ring *ring = kring->ring; 814 bus_dmamap_t *map; 815 struct if_rxd_update iru; 816 if_ctx_t ctx = rxq->ifr_ctx; 817 iflib_fl_t fl = &rxq->ifr_fl[0]; 818 uint32_t refill_pidx, nic_i; 819 820 if (nm_i == head && __predict_true(!init)) 821 return 0; 822 iru_init(&iru, rxq, 0 /* flid */); 823 map = fl->ifl_sds.ifsd_map; 824 refill_pidx = netmap_idx_k2n(kring, nm_i); 825 /* 826 * IMPORTANT: we must leave one free slot in the ring, 827 * so move head back by one unit 828 */ 829 head = nm_prev(head, lim); 830 while (nm_i != head) { 831 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 832 struct netmap_slot *slot = &ring->slot[nm_i]; 833 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 834 uint32_t nic_i_dma = refill_pidx; 835 nic_i = netmap_idx_k2n(kring, nm_i); 836 837 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 838 839 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 840 return netmap_ring_reinit(kring); 841 842 fl->ifl_vm_addrs[tmp_pidx] = addr; 843 if (__predict_false(init) && map) { 844 netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 845 } else if (map && (slot->flags & NS_BUF_CHANGED)) { 846 /* buffer has changed, reload map */ 847 netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); 848 } 849 slot->flags &= ~NS_BUF_CHANGED; 850 851 nm_i = nm_next(nm_i, lim); 852 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 853 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 854 continue; 855 856 iru.iru_pidx = refill_pidx; 857 iru.iru_count = tmp_pidx+1; 858 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 859 860 refill_pidx = nic_i; 861 if (map == NULL) 862 continue; 863 864 for (int n = 0; n < iru.iru_count; n++) { 865 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], 866 BUS_DMASYNC_PREREAD); 867 /* XXX - change this to not use the netmap func*/ 868 nic_i_dma = nm_next(nic_i_dma, lim); 869 } 870 } 871 } 872 kring->nr_hwcur = head; 873 874 if (map) 875 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 877 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 878 return (0); 879 } 880 881 /* 882 * Reconcile kernel and user view of the transmit ring. 883 * 884 * All information is in the kring. 885 * Userspace wants to send packets up to the one before kring->rhead, 886 * kernel knows kring->nr_hwcur is the first unsent packet. 887 * 888 * Here we push packets out (as many as possible), and possibly 889 * reclaim buffers from previously completed transmission. 890 * 891 * The caller (netmap) guarantees that there is only one instance 892 * running at any time. Any interference with other driver 893 * methods should be handled by the individual drivers. 894 */ 895 static int 896 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 897 { 898 struct netmap_adapter *na = kring->na; 899 struct ifnet *ifp = na->ifp; 900 struct netmap_ring *ring = kring->ring; 901 u_int nm_i; /* index into the netmap ring */ 902 u_int nic_i; /* index into the NIC ring */ 903 u_int n; 904 u_int const lim = kring->nkr_num_slots - 1; 905 u_int const head = kring->rhead; 906 struct if_pkt_info pi; 907 908 /* 909 * interrupts on every tx packet are expensive so request 910 * them every half ring, or where NS_REPORT is set 911 */ 912 u_int report_frequency = kring->nkr_num_slots >> 1; 913 /* device-specific */ 914 if_ctx_t ctx = ifp->if_softc; 915 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 916 917 if (txq->ift_sds.ifsd_map) 918 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 919 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 920 921 922 /* 923 * First part: process new packets to send. 924 * nm_i is the current index in the netmap ring, 925 * nic_i is the corresponding index in the NIC ring. 926 * 927 * If we have packets to send (nm_i != head) 928 * iterate over the netmap ring, fetch length and update 929 * the corresponding slot in the NIC ring. Some drivers also 930 * need to update the buffer's physical address in the NIC slot 931 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 932 * 933 * The netmap_reload_map() calls is especially expensive, 934 * even when (as in this case) the tag is 0, so do only 935 * when the buffer has actually changed. 936 * 937 * If possible do not set the report/intr bit on all slots, 938 * but only a few times per ring or when NS_REPORT is set. 939 * 940 * Finally, on 10G and faster drivers, it might be useful 941 * to prefetch the next slot and txr entry. 942 */ 943 944 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 945 pkt_info_zero(&pi); 946 pi.ipi_segs = txq->ift_segs; 947 pi.ipi_qsidx = kring->ring_id; 948 if (nm_i != head) { /* we have new packets to send */ 949 nic_i = netmap_idx_k2n(kring, nm_i); 950 951 __builtin_prefetch(&ring->slot[nm_i]); 952 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 953 if (txq->ift_sds.ifsd_map) 954 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 955 956 for (n = 0; nm_i != head; n++) { 957 struct netmap_slot *slot = &ring->slot[nm_i]; 958 u_int len = slot->len; 959 uint64_t paddr; 960 void *addr = PNMB(na, slot, &paddr); 961 int flags = (slot->flags & NS_REPORT || 962 nic_i == 0 || nic_i == report_frequency) ? 963 IPI_TX_INTR : 0; 964 965 /* device-specific */ 966 pi.ipi_len = len; 967 pi.ipi_segs[0].ds_addr = paddr; 968 pi.ipi_segs[0].ds_len = len; 969 pi.ipi_nsegs = 1; 970 pi.ipi_ndescs = 0; 971 pi.ipi_pidx = nic_i; 972 pi.ipi_flags = flags; 973 974 /* Fill the slot in the NIC ring. */ 975 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 976 977 /* prefetch for next round */ 978 __builtin_prefetch(&ring->slot[nm_i + 1]); 979 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 980 if (txq->ift_sds.ifsd_map) { 981 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 982 983 NM_CHECK_ADDR_LEN(na, addr, len); 984 985 if (slot->flags & NS_BUF_CHANGED) { 986 /* buffer has changed, reload map */ 987 netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); 988 } 989 /* make sure changes to the buffer are synced */ 990 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], 991 BUS_DMASYNC_PREWRITE); 992 } 993 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 994 nm_i = nm_next(nm_i, lim); 995 nic_i = nm_next(nic_i, lim); 996 } 997 kring->nr_hwcur = head; 998 999 /* synchronize the NIC ring */ 1000 if (txq->ift_sds.ifsd_map) 1001 bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, 1002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1003 1004 /* (re)start the tx unit up to slot nic_i (excluded) */ 1005 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1006 } 1007 1008 /* 1009 * Second part: reclaim buffers for completed transmissions. 1010 */ 1011 if (iflib_tx_credits_update(ctx, txq)) { 1012 /* some tx completed, increment avail */ 1013 nic_i = txq->ift_cidx_processed; 1014 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1015 } 1016 return (0); 1017 } 1018 1019 /* 1020 * Reconcile kernel and user view of the receive ring. 1021 * Same as for the txsync, this routine must be efficient. 1022 * The caller guarantees a single invocations, but races against 1023 * the rest of the driver should be handled here. 1024 * 1025 * On call, kring->rhead is the first packet that userspace wants 1026 * to keep, and kring->rcur is the wakeup point. 1027 * The kernel has previously reported packets up to kring->rtail. 1028 * 1029 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1030 * of whether or not we received an interrupt. 1031 */ 1032 static int 1033 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1034 { 1035 struct netmap_adapter *na = kring->na; 1036 struct netmap_ring *ring = kring->ring; 1037 uint32_t nm_i; /* index into the netmap ring */ 1038 uint32_t nic_i; /* index into the NIC ring */ 1039 u_int i, n; 1040 u_int const lim = kring->nkr_num_slots - 1; 1041 u_int const head = netmap_idx_n2k(kring, kring->rhead); 1042 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1043 struct if_rxd_info ri; 1044 1045 struct ifnet *ifp = na->ifp; 1046 if_ctx_t ctx = ifp->if_softc; 1047 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1048 iflib_fl_t fl = rxq->ifr_fl; 1049 if (head > lim) 1050 return netmap_ring_reinit(kring); 1051 1052 /* XXX check sync modes */ 1053 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1054 if (fl->ifl_sds.ifsd_map == NULL) 1055 continue; 1056 bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, 1057 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1058 } 1059 /* 1060 * First part: import newly received packets. 1061 * 1062 * nm_i is the index of the next free slot in the netmap ring, 1063 * nic_i is the index of the next received packet in the NIC ring, 1064 * and they may differ in case if_init() has been called while 1065 * in netmap mode. For the receive ring we have 1066 * 1067 * nic_i = rxr->next_check; 1068 * nm_i = kring->nr_hwtail (previous) 1069 * and 1070 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1071 * 1072 * rxr->next_check is set to 0 on a ring reinit 1073 */ 1074 if (netmap_no_pendintr || force_update) { 1075 int crclen = iflib_crcstrip ? 0 : 4; 1076 int error, avail; 1077 uint16_t slot_flags = kring->nkr_slot_flags; 1078 1079 for (i = 0; i < rxq->ifr_nfl; i++) { 1080 fl = &rxq->ifr_fl[i]; 1081 nic_i = fl->ifl_cidx; 1082 nm_i = netmap_idx_n2k(kring, nic_i); 1083 avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); 1084 for (n = 0; avail > 0; n++, avail--) { 1085 rxd_info_zero(&ri); 1086 ri.iri_frags = rxq->ifr_frags; 1087 ri.iri_qsidx = kring->ring_id; 1088 ri.iri_ifp = ctx->ifc_ifp; 1089 ri.iri_cidx = nic_i; 1090 1091 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1092 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1093 ring->slot[nm_i].flags = slot_flags; 1094 if (fl->ifl_sds.ifsd_map) 1095 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, 1096 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1097 nm_i = nm_next(nm_i, lim); 1098 nic_i = nm_next(nic_i, lim); 1099 } 1100 if (n) { /* update the state variables */ 1101 if (netmap_no_pendintr && !force_update) { 1102 /* diagnostics */ 1103 iflib_rx_miss ++; 1104 iflib_rx_miss_bufs += n; 1105 } 1106 fl->ifl_cidx = nic_i; 1107 kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); 1108 } 1109 kring->nr_kflags &= ~NKR_PENDINTR; 1110 } 1111 } 1112 /* 1113 * Second part: skip past packets that userspace has released. 1114 * (kring->nr_hwcur to head excluded), 1115 * and make the buffers available for reception. 1116 * As usual nm_i is the index in the netmap ring, 1117 * nic_i is the index in the NIC ring, and 1118 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1119 */ 1120 /* XXX not sure how this will work with multiple free lists */ 1121 nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); 1122 1123 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1124 } 1125 1126 static void 1127 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1128 { 1129 struct ifnet *ifp = na->ifp; 1130 if_ctx_t ctx = ifp->if_softc; 1131 1132 CTX_LOCK(ctx); 1133 if (onoff) { 1134 IFDI_INTR_ENABLE(ctx); 1135 } else { 1136 IFDI_INTR_DISABLE(ctx); 1137 } 1138 CTX_UNLOCK(ctx); 1139 } 1140 1141 1142 static int 1143 iflib_netmap_attach(if_ctx_t ctx) 1144 { 1145 struct netmap_adapter na; 1146 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1147 1148 bzero(&na, sizeof(na)); 1149 1150 na.ifp = ctx->ifc_ifp; 1151 na.na_flags = NAF_BDG_MAYSLEEP; 1152 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1153 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1154 1155 na.num_tx_desc = scctx->isc_ntxd[0]; 1156 na.num_rx_desc = scctx->isc_nrxd[0]; 1157 na.nm_txsync = iflib_netmap_txsync; 1158 na.nm_rxsync = iflib_netmap_rxsync; 1159 na.nm_register = iflib_netmap_register; 1160 na.nm_intr = iflib_netmap_intr; 1161 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1162 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1163 return (netmap_attach(&na)); 1164 } 1165 1166 static void 1167 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1168 { 1169 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1170 struct netmap_slot *slot; 1171 1172 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1173 if (slot == NULL) 1174 return; 1175 if (txq->ift_sds.ifsd_map == NULL) 1176 return; 1177 1178 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1179 1180 /* 1181 * In netmap mode, set the map for the packet buffer. 1182 * NOTE: Some drivers (not this one) also need to set 1183 * the physical buffer address in the NIC ring. 1184 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1185 * netmap slot index, si 1186 */ 1187 int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); 1188 netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); 1189 } 1190 } 1191 1192 static void 1193 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1194 { 1195 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1196 struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; 1197 struct netmap_slot *slot; 1198 uint32_t nm_i; 1199 1200 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1201 if (slot == NULL) 1202 return; 1203 nm_i = netmap_idx_n2k(kring, 0); 1204 netmap_fl_refill(rxq, kring, nm_i, true); 1205 } 1206 1207 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1208 1209 #else 1210 #define iflib_netmap_txq_init(ctx, txq) 1211 #define iflib_netmap_rxq_init(ctx, rxq) 1212 #define iflib_netmap_detach(ifp) 1213 1214 #define iflib_netmap_attach(ctx) (0) 1215 #define netmap_rx_irq(ifp, qid, budget) (0) 1216 #define netmap_tx_irq(ifp, qid) do {} while (0) 1217 1218 #endif 1219 1220 #if defined(__i386__) || defined(__amd64__) 1221 static __inline void 1222 prefetch(void *x) 1223 { 1224 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1225 } 1226 static __inline void 1227 prefetch2cachelines(void *x) 1228 { 1229 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1230 #if (CACHE_LINE_SIZE < 128) 1231 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1232 #endif 1233 } 1234 #else 1235 #define prefetch(x) 1236 #define prefetch2cachelines(x) 1237 #endif 1238 1239 static void 1240 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1241 { 1242 if (err) 1243 return; 1244 *(bus_addr_t *) arg = segs[0].ds_addr; 1245 } 1246 1247 int 1248 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1249 { 1250 int err; 1251 if_shared_ctx_t sctx = ctx->ifc_sctx; 1252 device_t dev = ctx->ifc_dev; 1253 1254 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1255 1256 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1257 sctx->isc_q_align, 0, /* alignment, bounds */ 1258 BUS_SPACE_MAXADDR, /* lowaddr */ 1259 BUS_SPACE_MAXADDR, /* highaddr */ 1260 NULL, NULL, /* filter, filterarg */ 1261 size, /* maxsize */ 1262 1, /* nsegments */ 1263 size, /* maxsegsize */ 1264 BUS_DMA_ALLOCNOW, /* flags */ 1265 NULL, /* lockfunc */ 1266 NULL, /* lockarg */ 1267 &dma->idi_tag); 1268 if (err) { 1269 device_printf(dev, 1270 "%s: bus_dma_tag_create failed: %d\n", 1271 __func__, err); 1272 goto fail_0; 1273 } 1274 1275 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1276 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1277 if (err) { 1278 device_printf(dev, 1279 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1280 __func__, (uintmax_t)size, err); 1281 goto fail_1; 1282 } 1283 1284 dma->idi_paddr = IF_BAD_DMA; 1285 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1286 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1287 if (err || dma->idi_paddr == IF_BAD_DMA) { 1288 device_printf(dev, 1289 "%s: bus_dmamap_load failed: %d\n", 1290 __func__, err); 1291 goto fail_2; 1292 } 1293 1294 dma->idi_size = size; 1295 return (0); 1296 1297 fail_2: 1298 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1299 fail_1: 1300 bus_dma_tag_destroy(dma->idi_tag); 1301 fail_0: 1302 dma->idi_tag = NULL; 1303 1304 return (err); 1305 } 1306 1307 int 1308 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1309 { 1310 int i, err; 1311 iflib_dma_info_t *dmaiter; 1312 1313 dmaiter = dmalist; 1314 for (i = 0; i < count; i++, dmaiter++) { 1315 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1316 break; 1317 } 1318 if (err) 1319 iflib_dma_free_multi(dmalist, i); 1320 return (err); 1321 } 1322 1323 void 1324 iflib_dma_free(iflib_dma_info_t dma) 1325 { 1326 if (dma->idi_tag == NULL) 1327 return; 1328 if (dma->idi_paddr != IF_BAD_DMA) { 1329 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1330 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1331 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1332 dma->idi_paddr = IF_BAD_DMA; 1333 } 1334 if (dma->idi_vaddr != NULL) { 1335 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1336 dma->idi_vaddr = NULL; 1337 } 1338 bus_dma_tag_destroy(dma->idi_tag); 1339 dma->idi_tag = NULL; 1340 } 1341 1342 void 1343 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1344 { 1345 int i; 1346 iflib_dma_info_t *dmaiter = dmalist; 1347 1348 for (i = 0; i < count; i++, dmaiter++) 1349 iflib_dma_free(*dmaiter); 1350 } 1351 1352 #ifdef EARLY_AP_STARTUP 1353 static const int iflib_started = 1; 1354 #else 1355 /* 1356 * We used to abuse the smp_started flag to decide if the queues have been 1357 * fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). 1358 * That gave bad races, since the SYSINIT() runs strictly after smp_started 1359 * is set. Run a SYSINIT() strictly after that to just set a usable 1360 * completion flag. 1361 */ 1362 1363 static int iflib_started; 1364 1365 static void 1366 iflib_record_started(void *arg) 1367 { 1368 iflib_started = 1; 1369 } 1370 1371 SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, 1372 iflib_record_started, NULL); 1373 #endif 1374 1375 static int 1376 iflib_fast_intr(void *arg) 1377 { 1378 iflib_filter_info_t info = arg; 1379 struct grouptask *gtask = info->ifi_task; 1380 if (!iflib_started) 1381 return (FILTER_HANDLED); 1382 1383 DBG_COUNTER_INC(fast_intrs); 1384 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1385 return (FILTER_HANDLED); 1386 1387 GROUPTASK_ENQUEUE(gtask); 1388 return (FILTER_HANDLED); 1389 } 1390 1391 static int 1392 iflib_fast_intr_rxtx(void *arg) 1393 { 1394 iflib_filter_info_t info = arg; 1395 struct grouptask *gtask = info->ifi_task; 1396 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1397 if_ctx_t ctx; 1398 int i, cidx; 1399 1400 if (!iflib_started) 1401 return (FILTER_HANDLED); 1402 1403 DBG_COUNTER_INC(fast_intrs); 1404 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1405 return (FILTER_HANDLED); 1406 1407 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1408 qidx_t txqid = rxq->ifr_txqid[i]; 1409 1410 ctx = rxq->ifr_ctx; 1411 1412 if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { 1413 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1414 continue; 1415 } 1416 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 1417 } 1418 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1419 cidx = rxq->ifr_cq_cidx; 1420 else 1421 cidx = rxq->ifr_fl[0].ifl_cidx; 1422 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1423 GROUPTASK_ENQUEUE(gtask); 1424 else 1425 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1426 return (FILTER_HANDLED); 1427 } 1428 1429 1430 static int 1431 iflib_fast_intr_ctx(void *arg) 1432 { 1433 iflib_filter_info_t info = arg; 1434 struct grouptask *gtask = info->ifi_task; 1435 1436 if (!iflib_started) 1437 return (FILTER_HANDLED); 1438 1439 DBG_COUNTER_INC(fast_intrs); 1440 if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) 1441 return (FILTER_HANDLED); 1442 1443 GROUPTASK_ENQUEUE(gtask); 1444 return (FILTER_HANDLED); 1445 } 1446 1447 static int 1448 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1449 driver_filter_t filter, driver_intr_t handler, void *arg, 1450 char *name) 1451 { 1452 int rc, flags; 1453 struct resource *res; 1454 void *tag = NULL; 1455 device_t dev = ctx->ifc_dev; 1456 1457 flags = RF_ACTIVE; 1458 if (ctx->ifc_flags & IFC_LEGACY) 1459 flags |= RF_SHAREABLE; 1460 MPASS(rid < 512); 1461 irq->ii_rid = rid; 1462 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); 1463 if (res == NULL) { 1464 device_printf(dev, 1465 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1466 return (ENOMEM); 1467 } 1468 irq->ii_res = res; 1469 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1470 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1471 filter, handler, arg, &tag); 1472 if (rc != 0) { 1473 device_printf(dev, 1474 "failed to setup interrupt for rid %d, name %s: %d\n", 1475 rid, name ? name : "unknown", rc); 1476 return (rc); 1477 } else if (name) 1478 bus_describe_intr(dev, res, tag, "%s", name); 1479 1480 irq->ii_tag = tag; 1481 return (0); 1482 } 1483 1484 1485 /********************************************************************* 1486 * 1487 * Allocate memory for tx_buffer structures. The tx_buffer stores all 1488 * the information needed to transmit a packet on the wire. This is 1489 * called only once at attach, setup is done every reset. 1490 * 1491 **********************************************************************/ 1492 1493 static int 1494 iflib_txsd_alloc(iflib_txq_t txq) 1495 { 1496 if_ctx_t ctx = txq->ift_ctx; 1497 if_shared_ctx_t sctx = ctx->ifc_sctx; 1498 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1499 device_t dev = ctx->ifc_dev; 1500 int err, nsegments, ntsosegments; 1501 1502 nsegments = scctx->isc_tx_nsegments; 1503 ntsosegments = scctx->isc_tx_tso_segments_max; 1504 MPASS(scctx->isc_ntxd[0] > 0); 1505 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1506 MPASS(nsegments > 0); 1507 MPASS(ntsosegments > 0); 1508 /* 1509 * Setup DMA descriptor areas. 1510 */ 1511 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1512 1, 0, /* alignment, bounds */ 1513 BUS_SPACE_MAXADDR, /* lowaddr */ 1514 BUS_SPACE_MAXADDR, /* highaddr */ 1515 NULL, NULL, /* filter, filterarg */ 1516 sctx->isc_tx_maxsize, /* maxsize */ 1517 nsegments, /* nsegments */ 1518 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1519 0, /* flags */ 1520 NULL, /* lockfunc */ 1521 NULL, /* lockfuncarg */ 1522 &txq->ift_desc_tag))) { 1523 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1524 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1525 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1526 goto fail; 1527 } 1528 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1529 1, 0, /* alignment, bounds */ 1530 BUS_SPACE_MAXADDR, /* lowaddr */ 1531 BUS_SPACE_MAXADDR, /* highaddr */ 1532 NULL, NULL, /* filter, filterarg */ 1533 scctx->isc_tx_tso_size_max, /* maxsize */ 1534 ntsosegments, /* nsegments */ 1535 scctx->isc_tx_tso_segsize_max, /* maxsegsize */ 1536 0, /* flags */ 1537 NULL, /* lockfunc */ 1538 NULL, /* lockfuncarg */ 1539 &txq->ift_tso_desc_tag))) { 1540 device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); 1541 1542 goto fail; 1543 } 1544 if (!(txq->ift_sds.ifsd_flags = 1545 (uint8_t *) malloc(sizeof(uint8_t) * 1546 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1547 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1548 err = ENOMEM; 1549 goto fail; 1550 } 1551 if (!(txq->ift_sds.ifsd_m = 1552 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1553 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1554 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1555 err = ENOMEM; 1556 goto fail; 1557 } 1558 1559 /* Create the descriptor buffer dma maps */ 1560 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1561 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1562 return (0); 1563 1564 if (!(txq->ift_sds.ifsd_map = 1565 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1566 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1567 err = ENOMEM; 1568 goto fail; 1569 } 1570 1571 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1572 err = bus_dmamap_create(txq->ift_desc_tag, 0, &txq->ift_sds.ifsd_map[i]); 1573 if (err != 0) { 1574 device_printf(dev, "Unable to create TX DMA map\n"); 1575 goto fail; 1576 } 1577 } 1578 #endif 1579 return (0); 1580 fail: 1581 /* We free all, it handles case where we are in the middle */ 1582 iflib_tx_structures_free(ctx); 1583 return (err); 1584 } 1585 1586 static void 1587 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1588 { 1589 bus_dmamap_t map; 1590 1591 map = NULL; 1592 if (txq->ift_sds.ifsd_map != NULL) 1593 map = txq->ift_sds.ifsd_map[i]; 1594 if (map != NULL) { 1595 bus_dmamap_unload(txq->ift_desc_tag, map); 1596 bus_dmamap_destroy(txq->ift_desc_tag, map); 1597 txq->ift_sds.ifsd_map[i] = NULL; 1598 } 1599 } 1600 1601 static void 1602 iflib_txq_destroy(iflib_txq_t txq) 1603 { 1604 if_ctx_t ctx = txq->ift_ctx; 1605 1606 for (int i = 0; i < txq->ift_size; i++) 1607 iflib_txsd_destroy(ctx, txq, i); 1608 if (txq->ift_sds.ifsd_map != NULL) { 1609 free(txq->ift_sds.ifsd_map, M_IFLIB); 1610 txq->ift_sds.ifsd_map = NULL; 1611 } 1612 if (txq->ift_sds.ifsd_m != NULL) { 1613 free(txq->ift_sds.ifsd_m, M_IFLIB); 1614 txq->ift_sds.ifsd_m = NULL; 1615 } 1616 if (txq->ift_sds.ifsd_flags != NULL) { 1617 free(txq->ift_sds.ifsd_flags, M_IFLIB); 1618 txq->ift_sds.ifsd_flags = NULL; 1619 } 1620 if (txq->ift_desc_tag != NULL) { 1621 bus_dma_tag_destroy(txq->ift_desc_tag); 1622 txq->ift_desc_tag = NULL; 1623 } 1624 if (txq->ift_tso_desc_tag != NULL) { 1625 bus_dma_tag_destroy(txq->ift_tso_desc_tag); 1626 txq->ift_tso_desc_tag = NULL; 1627 } 1628 } 1629 1630 static void 1631 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1632 { 1633 struct mbuf **mp; 1634 1635 mp = &txq->ift_sds.ifsd_m[i]; 1636 if (*mp == NULL) 1637 return; 1638 1639 if (txq->ift_sds.ifsd_map != NULL) { 1640 bus_dmamap_sync(txq->ift_desc_tag, 1641 txq->ift_sds.ifsd_map[i], 1642 BUS_DMASYNC_POSTWRITE); 1643 bus_dmamap_unload(txq->ift_desc_tag, 1644 txq->ift_sds.ifsd_map[i]); 1645 } 1646 m_free(*mp); 1647 DBG_COUNTER_INC(tx_frees); 1648 *mp = NULL; 1649 } 1650 1651 static int 1652 iflib_txq_setup(iflib_txq_t txq) 1653 { 1654 if_ctx_t ctx = txq->ift_ctx; 1655 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1656 iflib_dma_info_t di; 1657 int i; 1658 1659 /* Set number of descriptors available */ 1660 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1661 /* XXX make configurable */ 1662 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1663 1664 /* Reset indices */ 1665 txq->ift_cidx_processed = 0; 1666 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1667 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1668 1669 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1670 bzero((void *)di->idi_vaddr, di->idi_size); 1671 1672 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1673 for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) 1674 bus_dmamap_sync(di->idi_tag, di->idi_map, 1675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1676 return (0); 1677 } 1678 1679 /********************************************************************* 1680 * 1681 * Allocate memory for rx_buffer structures. Since we use one 1682 * rx_buffer per received packet, the maximum number of rx_buffer's 1683 * that we'll need is equal to the number of receive descriptors 1684 * that we've allocated. 1685 * 1686 **********************************************************************/ 1687 static int 1688 iflib_rxsd_alloc(iflib_rxq_t rxq) 1689 { 1690 if_ctx_t ctx = rxq->ifr_ctx; 1691 if_shared_ctx_t sctx = ctx->ifc_sctx; 1692 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1693 device_t dev = ctx->ifc_dev; 1694 iflib_fl_t fl; 1695 int err; 1696 1697 MPASS(scctx->isc_nrxd[0] > 0); 1698 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1699 1700 fl = rxq->ifr_fl; 1701 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1702 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1703 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1704 1, 0, /* alignment, bounds */ 1705 BUS_SPACE_MAXADDR, /* lowaddr */ 1706 BUS_SPACE_MAXADDR, /* highaddr */ 1707 NULL, NULL, /* filter, filterarg */ 1708 sctx->isc_rx_maxsize, /* maxsize */ 1709 sctx->isc_rx_nsegments, /* nsegments */ 1710 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1711 0, /* flags */ 1712 NULL, /* lockfunc */ 1713 NULL, /* lockarg */ 1714 &fl->ifl_desc_tag); 1715 if (err) { 1716 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 1717 __func__, err); 1718 goto fail; 1719 } 1720 if (!(fl->ifl_sds.ifsd_flags = 1721 (uint8_t *) malloc(sizeof(uint8_t) * 1722 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1723 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1724 err = ENOMEM; 1725 goto fail; 1726 } 1727 if (!(fl->ifl_sds.ifsd_m = 1728 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1729 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1730 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1731 err = ENOMEM; 1732 goto fail; 1733 } 1734 if (!(fl->ifl_sds.ifsd_cl = 1735 (caddr_t *) malloc(sizeof(caddr_t) * 1736 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1737 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 1738 err = ENOMEM; 1739 goto fail; 1740 } 1741 1742 /* Create the descriptor buffer dma maps */ 1743 #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) 1744 if ((ctx->ifc_flags & IFC_DMAR) == 0) 1745 continue; 1746 1747 if (!(fl->ifl_sds.ifsd_map = 1748 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1749 device_printf(dev, "Unable to allocate tx_buffer map memory\n"); 1750 err = ENOMEM; 1751 goto fail; 1752 } 1753 1754 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1755 err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); 1756 if (err != 0) { 1757 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1758 goto fail; 1759 } 1760 } 1761 #endif 1762 } 1763 return (0); 1764 1765 fail: 1766 iflib_rx_structures_free(ctx); 1767 return (err); 1768 } 1769 1770 1771 /* 1772 * Internal service routines 1773 */ 1774 1775 struct rxq_refill_cb_arg { 1776 int error; 1777 bus_dma_segment_t seg; 1778 int nseg; 1779 }; 1780 1781 static void 1782 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1783 { 1784 struct rxq_refill_cb_arg *cb_arg = arg; 1785 1786 cb_arg->error = error; 1787 cb_arg->seg = segs[0]; 1788 cb_arg->nseg = nseg; 1789 } 1790 1791 1792 #ifdef ACPI_DMAR 1793 #define IS_DMAR(ctx) (ctx->ifc_flags & IFC_DMAR) 1794 #else 1795 #define IS_DMAR(ctx) (0) 1796 #endif 1797 1798 /** 1799 * rxq_refill - refill an rxq free-buffer list 1800 * @ctx: the iflib context 1801 * @rxq: the free-list to refill 1802 * @n: the number of new buffers to allocate 1803 * 1804 * (Re)populate an rxq free-buffer list with up to @n new packet buffers. 1805 * The caller must assure that @n does not exceed the queue's capacity. 1806 */ 1807 static void 1808 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1809 { 1810 struct mbuf *m; 1811 int idx, frag_idx = fl->ifl_fragidx; 1812 int pidx = fl->ifl_pidx; 1813 caddr_t cl, *sd_cl; 1814 struct mbuf **sd_m; 1815 uint8_t *sd_flags; 1816 struct if_rxd_update iru; 1817 bus_dmamap_t *sd_map; 1818 int n, i = 0; 1819 uint64_t bus_addr; 1820 int err; 1821 1822 sd_m = fl->ifl_sds.ifsd_m; 1823 sd_map = fl->ifl_sds.ifsd_map; 1824 sd_cl = fl->ifl_sds.ifsd_cl; 1825 sd_flags = fl->ifl_sds.ifsd_flags; 1826 idx = pidx; 1827 1828 n = count; 1829 MPASS(n > 0); 1830 MPASS(fl->ifl_credits + n <= fl->ifl_size); 1831 1832 if (pidx < fl->ifl_cidx) 1833 MPASS(pidx + n <= fl->ifl_cidx); 1834 if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) 1835 MPASS(fl->ifl_gen == 0); 1836 if (pidx > fl->ifl_cidx) 1837 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1838 1839 DBG_COUNTER_INC(fl_refills); 1840 if (n > 8) 1841 DBG_COUNTER_INC(fl_refills_large); 1842 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1843 while (n--) { 1844 /* 1845 * We allocate an uninitialized mbuf + cluster, mbuf is 1846 * initialized after rx. 1847 * 1848 * If the cluster is still set then we know a minimum sized packet was received 1849 */ 1850 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); 1851 if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) 1852 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1853 if ((cl = sd_cl[frag_idx]) == NULL) { 1854 if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1855 break; 1856 #if MEMORY_LOGGING 1857 fl->ifl_cl_enqueued++; 1858 #endif 1859 } 1860 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1861 break; 1862 } 1863 #if MEMORY_LOGGING 1864 fl->ifl_m_enqueued++; 1865 #endif 1866 1867 DBG_COUNTER_INC(rx_allocs); 1868 #if defined(__i386__) || defined(__amd64__) 1869 if (!IS_DMAR(ctx)) { 1870 bus_addr = pmap_kextract((vm_offset_t)cl); 1871 } else 1872 #endif 1873 { 1874 struct rxq_refill_cb_arg cb_arg; 1875 iflib_rxq_t q; 1876 1877 cb_arg.error = 0; 1878 q = fl->ifl_rxq; 1879 MPASS(sd_map != NULL); 1880 MPASS(sd_map[frag_idx] != NULL); 1881 err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], 1882 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); 1883 bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], 1884 BUS_DMASYNC_PREREAD); 1885 1886 if (err != 0 || cb_arg.error) { 1887 /* 1888 * !zone_pack ? 1889 */ 1890 if (fl->ifl_zone == zone_pack) 1891 uma_zfree(fl->ifl_zone, cl); 1892 m_free(m); 1893 n = 0; 1894 goto done; 1895 } 1896 bus_addr = cb_arg.seg.ds_addr; 1897 } 1898 bit_set(fl->ifl_rx_bitmap, frag_idx); 1899 sd_flags[frag_idx] |= RX_SW_DESC_INUSE; 1900 1901 MPASS(sd_m[frag_idx] == NULL); 1902 sd_cl[frag_idx] = cl; 1903 sd_m[frag_idx] = m; 1904 fl->ifl_rxd_idxs[i] = frag_idx; 1905 fl->ifl_bus_addrs[i] = bus_addr; 1906 fl->ifl_vm_addrs[i] = cl; 1907 fl->ifl_credits++; 1908 i++; 1909 MPASS(fl->ifl_credits <= fl->ifl_size); 1910 if (++idx == fl->ifl_size) { 1911 fl->ifl_gen = 1; 1912 idx = 0; 1913 } 1914 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 1915 iru.iru_pidx = pidx; 1916 iru.iru_count = i; 1917 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 1918 i = 0; 1919 pidx = idx; 1920 fl->ifl_pidx = idx; 1921 } 1922 1923 } 1924 done: 1925 DBG_COUNTER_INC(rxd_flush); 1926 if (fl->ifl_pidx == 0) 1927 pidx = fl->ifl_size - 1; 1928 else 1929 pidx = fl->ifl_pidx - 1; 1930 1931 if (sd_map) 1932 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1933 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1934 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 1935 fl->ifl_fragidx = frag_idx; 1936 } 1937 1938 static __inline void 1939 __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) 1940 { 1941 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 1942 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 1943 #ifdef INVARIANTS 1944 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 1945 #endif 1946 1947 MPASS(fl->ifl_credits <= fl->ifl_size); 1948 MPASS(reclaimable == delta); 1949 1950 if (reclaimable > 0) 1951 _iflib_fl_refill(ctx, fl, min(max, reclaimable)); 1952 } 1953 1954 static void 1955 iflib_fl_bufs_free(iflib_fl_t fl) 1956 { 1957 iflib_dma_info_t idi = fl->ifl_ifdi; 1958 uint32_t i; 1959 1960 for (i = 0; i < fl->ifl_size; i++) { 1961 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 1962 uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; 1963 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 1964 1965 if (*sd_flags & RX_SW_DESC_INUSE) { 1966 if (fl->ifl_sds.ifsd_map != NULL) { 1967 bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; 1968 bus_dmamap_unload(fl->ifl_desc_tag, sd_map); 1969 bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); 1970 } 1971 if (*sd_m != NULL) { 1972 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 1973 uma_zfree(zone_mbuf, *sd_m); 1974 } 1975 if (*sd_cl != NULL) 1976 uma_zfree(fl->ifl_zone, *sd_cl); 1977 *sd_flags = 0; 1978 } else { 1979 MPASS(*sd_cl == NULL); 1980 MPASS(*sd_m == NULL); 1981 } 1982 #if MEMORY_LOGGING 1983 fl->ifl_m_dequeued++; 1984 fl->ifl_cl_dequeued++; 1985 #endif 1986 *sd_cl = NULL; 1987 *sd_m = NULL; 1988 } 1989 #ifdef INVARIANTS 1990 for (i = 0; i < fl->ifl_size; i++) { 1991 MPASS(fl->ifl_sds.ifsd_flags[i] == 0); 1992 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 1993 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 1994 } 1995 #endif 1996 /* 1997 * Reset free list values 1998 */ 1999 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2000 bzero(idi->idi_vaddr, idi->idi_size); 2001 } 2002 2003 /********************************************************************* 2004 * 2005 * Initialize a receive ring and its buffers. 2006 * 2007 **********************************************************************/ 2008 static int 2009 iflib_fl_setup(iflib_fl_t fl) 2010 { 2011 iflib_rxq_t rxq = fl->ifl_rxq; 2012 if_ctx_t ctx = rxq->ifr_ctx; 2013 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2014 2015 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size); 2016 /* 2017 ** Free current RX buffer structs and their mbufs 2018 */ 2019 iflib_fl_bufs_free(fl); 2020 /* Now replenish the mbufs */ 2021 MPASS(fl->ifl_credits == 0); 2022 /* 2023 * XXX don't set the max_frame_size to larger 2024 * than the hardware can handle 2025 */ 2026 if (sctx->isc_max_frame_size <= 2048) 2027 fl->ifl_buf_size = MCLBYTES; 2028 #ifndef CONTIGMALLOC_WORKS 2029 else 2030 fl->ifl_buf_size = MJUMPAGESIZE; 2031 #else 2032 else if (sctx->isc_max_frame_size <= 4096) 2033 fl->ifl_buf_size = MJUMPAGESIZE; 2034 else if (sctx->isc_max_frame_size <= 9216) 2035 fl->ifl_buf_size = MJUM9BYTES; 2036 else 2037 fl->ifl_buf_size = MJUM16BYTES; 2038 #endif 2039 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2040 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2041 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2042 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2043 2044 2045 /* avoid pre-allocating zillions of clusters to an idle card 2046 * potentially speeding up attach 2047 */ 2048 _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2049 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2050 if (min(128, fl->ifl_size) != fl->ifl_credits) 2051 return (ENOBUFS); 2052 /* 2053 * handle failure 2054 */ 2055 MPASS(rxq != NULL); 2056 MPASS(fl->ifl_ifdi != NULL); 2057 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2058 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2059 return (0); 2060 } 2061 2062 /********************************************************************* 2063 * 2064 * Free receive ring data structures 2065 * 2066 **********************************************************************/ 2067 static void 2068 iflib_rx_sds_free(iflib_rxq_t rxq) 2069 { 2070 iflib_fl_t fl; 2071 int i; 2072 2073 if (rxq->ifr_fl != NULL) { 2074 for (i = 0; i < rxq->ifr_nfl; i++) { 2075 fl = &rxq->ifr_fl[i]; 2076 if (fl->ifl_desc_tag != NULL) { 2077 bus_dma_tag_destroy(fl->ifl_desc_tag); 2078 fl->ifl_desc_tag = NULL; 2079 } 2080 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2081 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2082 /* XXX destroy maps first */ 2083 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2084 fl->ifl_sds.ifsd_m = NULL; 2085 fl->ifl_sds.ifsd_cl = NULL; 2086 fl->ifl_sds.ifsd_map = NULL; 2087 } 2088 free(rxq->ifr_fl, M_IFLIB); 2089 rxq->ifr_fl = NULL; 2090 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 2091 } 2092 } 2093 2094 /* 2095 * MI independent logic 2096 * 2097 */ 2098 static void 2099 iflib_timer(void *arg) 2100 { 2101 iflib_txq_t txq = arg; 2102 if_ctx_t ctx = txq->ift_ctx; 2103 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2104 2105 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2106 return; 2107 /* 2108 ** Check on the state of the TX queue(s), this 2109 ** can be done without the lock because its RO 2110 ** and the HUNG state will be static if set. 2111 */ 2112 IFDI_TIMER(ctx, txq->ift_id); 2113 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2114 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2115 (sctx->isc_pause_frames == 0))) 2116 goto hung; 2117 2118 if (ifmp_ring_is_stalled(txq->ift_br)) 2119 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2120 txq->ift_cleaned_prev = txq->ift_cleaned; 2121 /* handle any laggards */ 2122 if (txq->ift_db_pending) 2123 GROUPTASK_ENQUEUE(&txq->ift_task); 2124 2125 sctx->isc_pause_frames = 0; 2126 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2127 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 2128 return; 2129 hung: 2130 CTX_LOCK(ctx); 2131 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2132 device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", 2133 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2134 2135 IFDI_WATCHDOG_RESET(ctx); 2136 ctx->ifc_watchdog_events++; 2137 2138 ctx->ifc_flags |= IFC_DO_RESET; 2139 iflib_admin_intr_deferred(ctx); 2140 CTX_UNLOCK(ctx); 2141 } 2142 2143 static void 2144 iflib_init_locked(if_ctx_t ctx) 2145 { 2146 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2147 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2148 if_t ifp = ctx->ifc_ifp; 2149 iflib_fl_t fl; 2150 iflib_txq_t txq; 2151 iflib_rxq_t rxq; 2152 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2153 2154 2155 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2156 IFDI_INTR_DISABLE(ctx); 2157 2158 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2159 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2160 /* Set hardware offload abilities */ 2161 if_clearhwassist(ifp); 2162 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2163 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2164 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2165 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2166 if (if_getcapenable(ifp) & IFCAP_TSO4) 2167 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2168 if (if_getcapenable(ifp) & IFCAP_TSO6) 2169 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2170 2171 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2172 CALLOUT_LOCK(txq); 2173 callout_stop(&txq->ift_timer); 2174 CALLOUT_UNLOCK(txq); 2175 iflib_netmap_txq_init(ctx, txq); 2176 } 2177 #ifdef INVARIANTS 2178 i = if_getdrvflags(ifp); 2179 #endif 2180 IFDI_INIT(ctx); 2181 MPASS(if_getdrvflags(ifp) == i); 2182 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2183 /* XXX this should really be done on a per-queue basis */ 2184 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2185 MPASS(rxq->ifr_id == i); 2186 iflib_netmap_rxq_init(ctx, rxq); 2187 continue; 2188 } 2189 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2190 if (iflib_fl_setup(fl)) { 2191 device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); 2192 goto done; 2193 } 2194 } 2195 } 2196 done: 2197 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2198 IFDI_INTR_ENABLE(ctx); 2199 txq = ctx->ifc_txqs; 2200 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2201 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2202 txq->ift_timer.c_cpu); 2203 } 2204 2205 static int 2206 iflib_media_change(if_t ifp) 2207 { 2208 if_ctx_t ctx = if_getsoftc(ifp); 2209 int err; 2210 2211 CTX_LOCK(ctx); 2212 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2213 iflib_init_locked(ctx); 2214 CTX_UNLOCK(ctx); 2215 return (err); 2216 } 2217 2218 static void 2219 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2220 { 2221 if_ctx_t ctx = if_getsoftc(ifp); 2222 2223 CTX_LOCK(ctx); 2224 IFDI_UPDATE_ADMIN_STATUS(ctx); 2225 IFDI_MEDIA_STATUS(ctx, ifmr); 2226 CTX_UNLOCK(ctx); 2227 } 2228 2229 static void 2230 iflib_stop(if_ctx_t ctx) 2231 { 2232 iflib_txq_t txq = ctx->ifc_txqs; 2233 iflib_rxq_t rxq = ctx->ifc_rxqs; 2234 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2235 iflib_dma_info_t di; 2236 iflib_fl_t fl; 2237 int i, j; 2238 2239 /* Tell the stack that the interface is no longer active */ 2240 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2241 2242 IFDI_INTR_DISABLE(ctx); 2243 DELAY(1000); 2244 IFDI_STOP(ctx); 2245 DELAY(1000); 2246 2247 iflib_debug_reset(); 2248 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2249 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2250 /* make sure all transmitters have completed before proceeding XXX */ 2251 2252 /* clean any enqueued buffers */ 2253 iflib_ifmp_purge(txq); 2254 /* Free any existing tx buffers. */ 2255 for (j = 0; j < txq->ift_size; j++) { 2256 iflib_txsd_free(ctx, txq, j); 2257 } 2258 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2259 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2260 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2261 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2262 txq->ift_pullups = 0; 2263 ifmp_ring_reset_stats(txq->ift_br); 2264 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) 2265 bzero((void *)di->idi_vaddr, di->idi_size); 2266 } 2267 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2268 /* make sure all transmitters have completed before proceeding XXX */ 2269 2270 for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) 2271 bzero((void *)di->idi_vaddr, di->idi_size); 2272 /* also resets the free lists pidx/cidx */ 2273 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2274 iflib_fl_bufs_free(fl); 2275 } 2276 } 2277 2278 static inline caddr_t 2279 calc_next_rxd(iflib_fl_t fl, int cidx) 2280 { 2281 qidx_t size; 2282 int nrxd; 2283 caddr_t start, end, cur, next; 2284 2285 nrxd = fl->ifl_size; 2286 size = fl->ifl_rxd_size; 2287 start = fl->ifl_ifdi->idi_vaddr; 2288 2289 if (__predict_false(size == 0)) 2290 return (start); 2291 cur = start + size*cidx; 2292 end = start + size*nrxd; 2293 next = CACHE_PTR_NEXT(cur); 2294 return (next < end ? next : start); 2295 } 2296 2297 static inline void 2298 prefetch_pkts(iflib_fl_t fl, int cidx) 2299 { 2300 int nextptr; 2301 int nrxd = fl->ifl_size; 2302 caddr_t next_rxd; 2303 2304 2305 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2306 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2307 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2308 next_rxd = calc_next_rxd(fl, cidx); 2309 prefetch(next_rxd); 2310 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2311 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2312 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2313 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2314 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2315 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2316 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2317 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2318 } 2319 2320 static void 2321 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) 2322 { 2323 int flid, cidx; 2324 bus_dmamap_t map; 2325 iflib_fl_t fl; 2326 iflib_dma_info_t di; 2327 int next; 2328 2329 map = NULL; 2330 flid = irf->irf_flid; 2331 cidx = irf->irf_idx; 2332 fl = &rxq->ifr_fl[flid]; 2333 sd->ifsd_fl = fl; 2334 sd->ifsd_cidx = cidx; 2335 sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; 2336 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2337 fl->ifl_credits--; 2338 #if MEMORY_LOGGING 2339 fl->ifl_m_dequeued++; 2340 #endif 2341 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2342 prefetch_pkts(fl, cidx); 2343 if (fl->ifl_sds.ifsd_map != NULL) { 2344 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2345 prefetch(&fl->ifl_sds.ifsd_map[next]); 2346 map = fl->ifl_sds.ifsd_map[cidx]; 2347 di = fl->ifl_ifdi; 2348 next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); 2349 prefetch(&fl->ifl_sds.ifsd_flags[next]); 2350 bus_dmamap_sync(di->idi_tag, di->idi_map, 2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2352 2353 /* not valid assert if bxe really does SGE from non-contiguous elements */ 2354 MPASS(fl->ifl_cidx == cidx); 2355 if (unload) 2356 bus_dmamap_unload(fl->ifl_desc_tag, map); 2357 } 2358 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2359 if (__predict_false(fl->ifl_cidx == 0)) 2360 fl->ifl_gen = 0; 2361 if (map != NULL) 2362 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2364 bit_clear(fl->ifl_rx_bitmap, cidx); 2365 } 2366 2367 static struct mbuf * 2368 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) 2369 { 2370 int i, padlen , flags; 2371 struct mbuf *m, *mh, *mt; 2372 caddr_t cl; 2373 2374 i = 0; 2375 mh = NULL; 2376 do { 2377 rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); 2378 2379 MPASS(*sd->ifsd_cl != NULL); 2380 MPASS(*sd->ifsd_m != NULL); 2381 2382 /* Don't include zero-length frags */ 2383 if (ri->iri_frags[i].irf_len == 0) { 2384 /* XXX we can save the cluster here, but not the mbuf */ 2385 m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); 2386 m_free(*sd->ifsd_m); 2387 *sd->ifsd_m = NULL; 2388 continue; 2389 } 2390 m = *sd->ifsd_m; 2391 *sd->ifsd_m = NULL; 2392 if (mh == NULL) { 2393 flags = M_PKTHDR|M_EXT; 2394 mh = mt = m; 2395 padlen = ri->iri_pad; 2396 } else { 2397 flags = M_EXT; 2398 mt->m_next = m; 2399 mt = m; 2400 /* assuming padding is only on the first fragment */ 2401 padlen = 0; 2402 } 2403 cl = *sd->ifsd_cl; 2404 *sd->ifsd_cl = NULL; 2405 2406 /* Can these two be made one ? */ 2407 m_init(m, M_NOWAIT, MT_DATA, flags); 2408 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2409 /* 2410 * These must follow m_init and m_cljset 2411 */ 2412 m->m_data += padlen; 2413 ri->iri_len -= padlen; 2414 m->m_len = ri->iri_frags[i].irf_len; 2415 } while (++i < ri->iri_nfrags); 2416 2417 return (mh); 2418 } 2419 2420 /* 2421 * Process one software descriptor 2422 */ 2423 static struct mbuf * 2424 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2425 { 2426 struct if_rxsd sd; 2427 struct mbuf *m; 2428 2429 /* should I merge this back in now that the two paths are basically duplicated? */ 2430 if (ri->iri_nfrags == 1 && 2431 ri->iri_frags[0].irf_len <= IFLIB_RX_COPY_THRESH) { 2432 rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); 2433 m = *sd.ifsd_m; 2434 *sd.ifsd_m = NULL; 2435 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2436 #ifndef __NO_STRICT_ALIGNMENT 2437 if (!IP_ALIGNED(m)) 2438 m->m_data += 2; 2439 #endif 2440 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2441 m->m_len = ri->iri_frags[0].irf_len; 2442 } else { 2443 m = assemble_segments(rxq, ri, &sd); 2444 } 2445 m->m_pkthdr.len = ri->iri_len; 2446 m->m_pkthdr.rcvif = ri->iri_ifp; 2447 m->m_flags |= ri->iri_flags; 2448 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2449 m->m_pkthdr.flowid = ri->iri_flowid; 2450 M_HASHTYPE_SET(m, ri->iri_rsstype); 2451 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2452 m->m_pkthdr.csum_data = ri->iri_csum_data; 2453 return (m); 2454 } 2455 2456 static bool 2457 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2458 { 2459 if_ctx_t ctx = rxq->ifr_ctx; 2460 if_shared_ctx_t sctx = ctx->ifc_sctx; 2461 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2462 int avail, i; 2463 qidx_t *cidxp; 2464 struct if_rxd_info ri; 2465 int err, budget_left, rx_bytes, rx_pkts; 2466 iflib_fl_t fl; 2467 struct ifnet *ifp; 2468 int lro_enabled; 2469 2470 /* 2471 * XXX early demux data packets so that if_input processing only handles 2472 * acks in interrupt context 2473 */ 2474 struct mbuf *m, *mh, *mt, *mf; 2475 2476 ifp = ctx->ifc_ifp; 2477 mh = mt = NULL; 2478 MPASS(budget > 0); 2479 rx_pkts = rx_bytes = 0; 2480 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2481 cidxp = &rxq->ifr_cq_cidx; 2482 else 2483 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2484 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2485 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2486 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2487 DBG_COUNTER_INC(rx_unavail); 2488 return (false); 2489 } 2490 2491 for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { 2492 if (__predict_false(!CTX_ACTIVE(ctx))) { 2493 DBG_COUNTER_INC(rx_ctx_inactive); 2494 break; 2495 } 2496 /* 2497 * Reset client set fields to their default values 2498 */ 2499 rxd_info_zero(&ri); 2500 ri.iri_qsidx = rxq->ifr_id; 2501 ri.iri_cidx = *cidxp; 2502 ri.iri_ifp = ifp; 2503 ri.iri_frags = rxq->ifr_frags; 2504 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2505 2506 if (err) 2507 goto err; 2508 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2509 *cidxp = ri.iri_cidx; 2510 /* Update our consumer index */ 2511 /* XXX NB: shurd - check if this is still safe */ 2512 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { 2513 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2514 rxq->ifr_cq_gen = 0; 2515 } 2516 /* was this only a completion queue message? */ 2517 if (__predict_false(ri.iri_nfrags == 0)) 2518 continue; 2519 } 2520 MPASS(ri.iri_nfrags != 0); 2521 MPASS(ri.iri_len != 0); 2522 2523 /* will advance the cidx on the corresponding free lists */ 2524 m = iflib_rxd_pkt_get(rxq, &ri); 2525 if (avail == 0 && budget_left) 2526 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2527 2528 if (__predict_false(m == NULL)) { 2529 DBG_COUNTER_INC(rx_mbuf_null); 2530 continue; 2531 } 2532 /* imm_pkt: -- cxgb */ 2533 if (mh == NULL) 2534 mh = mt = m; 2535 else { 2536 mt->m_nextpkt = m; 2537 mt = m; 2538 } 2539 } 2540 /* make sure that we can refill faster than drain */ 2541 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2542 __iflib_fl_refill_lt(ctx, fl, budget + 8); 2543 2544 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2545 mt = mf = NULL; 2546 while (mh != NULL) { 2547 m = mh; 2548 if (mf == NULL) 2549 mf = m; 2550 mh = mh->m_nextpkt; 2551 m->m_nextpkt = NULL; 2552 #ifndef __NO_STRICT_ALIGNMENT 2553 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2554 continue; 2555 #endif 2556 rx_bytes += m->m_pkthdr.len; 2557 rx_pkts++; 2558 #if defined(INET6) || defined(INET) 2559 if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) { 2560 if (mf == m) 2561 mf = NULL; 2562 continue; 2563 } 2564 #endif 2565 if (mt != NULL) 2566 mt->m_nextpkt = m; 2567 mt = m; 2568 } 2569 if (mf != NULL) { 2570 ifp->if_input(ifp, mf); 2571 DBG_COUNTER_INC(rx_if_input); 2572 } 2573 2574 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2575 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2576 2577 /* 2578 * Flush any outstanding LRO work 2579 */ 2580 #if defined(INET6) || defined(INET) 2581 tcp_lro_flush_all(&rxq->ifr_lc); 2582 #endif 2583 if (avail) 2584 return true; 2585 return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); 2586 err: 2587 CTX_LOCK(ctx); 2588 ctx->ifc_flags |= IFC_DO_RESET; 2589 iflib_admin_intr_deferred(ctx); 2590 CTX_UNLOCK(ctx); 2591 return (false); 2592 } 2593 2594 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2595 static inline qidx_t 2596 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2597 { 2598 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2599 qidx_t minthresh = txq->ift_size / 8; 2600 if (in_use > 4*minthresh) 2601 return (notify_count); 2602 if (in_use > 2*minthresh) 2603 return (notify_count >> 1); 2604 if (in_use > minthresh) 2605 return (notify_count >> 3); 2606 return (0); 2607 } 2608 2609 static inline qidx_t 2610 txq_max_rs_deferred(iflib_txq_t txq) 2611 { 2612 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2613 qidx_t minthresh = txq->ift_size / 8; 2614 if (txq->ift_in_use > 4*minthresh) 2615 return (notify_count); 2616 if (txq->ift_in_use > 2*minthresh) 2617 return (notify_count >> 1); 2618 if (txq->ift_in_use > minthresh) 2619 return (notify_count >> 2); 2620 return (2); 2621 } 2622 2623 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2624 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2625 2626 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2627 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2628 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2629 2630 /* forward compatibility for cxgb */ 2631 #define FIRST_QSET(ctx) 0 2632 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2633 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2634 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2635 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2636 2637 /* XXX we should be setting this to something other than zero */ 2638 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2639 #define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) 2640 2641 static inline bool 2642 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2643 { 2644 qidx_t dbval, max; 2645 bool rang; 2646 2647 rang = false; 2648 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2649 if (ring || txq->ift_db_pending >= max) { 2650 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2651 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2652 txq->ift_db_pending = txq->ift_npending = 0; 2653 rang = true; 2654 } 2655 return (rang); 2656 } 2657 2658 #ifdef PKT_DEBUG 2659 static void 2660 print_pkt(if_pkt_info_t pi) 2661 { 2662 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2663 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2664 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2665 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2666 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2667 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2668 } 2669 #endif 2670 2671 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2672 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2673 2674 static int 2675 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2676 { 2677 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2678 struct ether_vlan_header *eh; 2679 struct mbuf *m, *n; 2680 2681 n = m = *mp; 2682 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 2683 M_WRITABLE(m) == 0) { 2684 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 2685 return (ENOMEM); 2686 } else { 2687 m_freem(*mp); 2688 n = *mp = m; 2689 } 2690 } 2691 2692 /* 2693 * Determine where frame payload starts. 2694 * Jump over vlan headers if already present, 2695 * helpful for QinQ too. 2696 */ 2697 if (__predict_false(m->m_len < sizeof(*eh))) { 2698 txq->ift_pullups++; 2699 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 2700 return (ENOMEM); 2701 } 2702 eh = mtod(m, struct ether_vlan_header *); 2703 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2704 pi->ipi_etype = ntohs(eh->evl_proto); 2705 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2706 } else { 2707 pi->ipi_etype = ntohs(eh->evl_encap_proto); 2708 pi->ipi_ehdrlen = ETHER_HDR_LEN; 2709 } 2710 2711 if (if_getmtu(txq->ift_ctx->ifc_ifp) >= pi->ipi_len) { 2712 pi->ipi_csum_flags &= ~(CSUM_IP_TSO|CSUM_IP6_TSO); 2713 } 2714 2715 switch (pi->ipi_etype) { 2716 #ifdef INET 2717 case ETHERTYPE_IP: 2718 { 2719 struct ip *ip = NULL; 2720 struct tcphdr *th = NULL; 2721 int minthlen; 2722 2723 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 2724 if (__predict_false(m->m_len < minthlen)) { 2725 /* 2726 * if this code bloat is causing too much of a hit 2727 * move it to a separate function and mark it noinline 2728 */ 2729 if (m->m_len == pi->ipi_ehdrlen) { 2730 n = m->m_next; 2731 MPASS(n); 2732 if (n->m_len >= sizeof(*ip)) { 2733 ip = (struct ip *)n->m_data; 2734 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2735 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2736 } else { 2737 txq->ift_pullups++; 2738 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2739 return (ENOMEM); 2740 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2741 } 2742 } else { 2743 txq->ift_pullups++; 2744 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 2745 return (ENOMEM); 2746 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2747 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2748 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2749 } 2750 } else { 2751 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 2752 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 2753 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 2754 } 2755 pi->ipi_ip_hlen = ip->ip_hl << 2; 2756 pi->ipi_ipproto = ip->ip_p; 2757 pi->ipi_flags |= IPI_TX_IPV4; 2758 2759 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 2760 ip->ip_sum = 0; 2761 2762 if (IS_TSO4(pi)) { 2763 if (pi->ipi_ipproto == IPPROTO_TCP) { 2764 if (__predict_false(th == NULL)) { 2765 txq->ift_pullups++; 2766 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 2767 return (ENOMEM); 2768 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 2769 } 2770 pi->ipi_tcp_hflags = th->th_flags; 2771 pi->ipi_tcp_hlen = th->th_off << 2; 2772 pi->ipi_tcp_seq = th->th_seq; 2773 } 2774 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 2775 return (ENXIO); 2776 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2777 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2778 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2779 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 2780 ip->ip_sum = 0; 2781 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 2782 } 2783 } 2784 break; 2785 } 2786 #endif 2787 #ifdef INET6 2788 case ETHERTYPE_IPV6: 2789 { 2790 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 2791 struct tcphdr *th; 2792 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 2793 2794 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 2795 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 2796 return (ENOMEM); 2797 } 2798 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 2799 2800 /* XXX-BZ this will go badly in case of ext hdrs. */ 2801 pi->ipi_ipproto = ip6->ip6_nxt; 2802 pi->ipi_flags |= IPI_TX_IPV6; 2803 2804 if (IS_TSO6(pi)) { 2805 if (pi->ipi_ipproto == IPPROTO_TCP) { 2806 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 2807 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 2808 return (ENOMEM); 2809 } 2810 pi->ipi_tcp_hflags = th->th_flags; 2811 pi->ipi_tcp_hlen = th->th_off << 2; 2812 } 2813 2814 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 2815 return (ENXIO); 2816 /* 2817 * The corresponding flag is set by the stack in the IPv4 2818 * TSO case, but not in IPv6 (at least in FreeBSD 10.2). 2819 * So, set it here because the rest of the flow requires it. 2820 */ 2821 pi->ipi_csum_flags |= CSUM_TCP_IPV6; 2822 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 2823 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 2824 } 2825 break; 2826 } 2827 #endif 2828 default: 2829 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 2830 pi->ipi_ip_hlen = 0; 2831 break; 2832 } 2833 *mp = m; 2834 2835 return (0); 2836 } 2837 2838 static __noinline struct mbuf * 2839 collapse_pkthdr(struct mbuf *m0) 2840 { 2841 struct mbuf *m, *m_next, *tmp; 2842 2843 m = m0; 2844 m_next = m->m_next; 2845 while (m_next != NULL && m_next->m_len == 0) { 2846 m = m_next; 2847 m->m_next = NULL; 2848 m_free(m); 2849 m_next = m_next->m_next; 2850 } 2851 m = m0; 2852 m->m_next = m_next; 2853 if ((m_next->m_flags & M_EXT) == 0) { 2854 m = m_defrag(m, M_NOWAIT); 2855 } else { 2856 tmp = m_next->m_next; 2857 memcpy(m_next, m, MPKTHSIZE); 2858 m = m_next; 2859 m->m_next = tmp; 2860 } 2861 return (m); 2862 } 2863 2864 /* 2865 * If dodgy hardware rejects the scatter gather chain we've handed it 2866 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 2867 * m_defrag'd mbufs 2868 */ 2869 static __noinline struct mbuf * 2870 iflib_remove_mbuf(iflib_txq_t txq) 2871 { 2872 int ntxd, i, pidx; 2873 struct mbuf *m, *mh, **ifsd_m; 2874 2875 pidx = txq->ift_pidx; 2876 ifsd_m = txq->ift_sds.ifsd_m; 2877 ntxd = txq->ift_size; 2878 mh = m = ifsd_m[pidx]; 2879 ifsd_m[pidx] = NULL; 2880 #if MEMORY_LOGGING 2881 txq->ift_dequeued++; 2882 #endif 2883 i = 1; 2884 2885 while (m) { 2886 ifsd_m[(pidx + i) & (ntxd -1)] = NULL; 2887 #if MEMORY_LOGGING 2888 txq->ift_dequeued++; 2889 #endif 2890 m = m->m_next; 2891 i++; 2892 } 2893 return (mh); 2894 } 2895 2896 static int 2897 iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, 2898 struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, 2899 int max_segs, int flags) 2900 { 2901 if_ctx_t ctx; 2902 if_shared_ctx_t sctx; 2903 if_softc_ctx_t scctx; 2904 int i, next, pidx, err, ntxd, count; 2905 struct mbuf *m, *tmp, **ifsd_m; 2906 2907 m = *m0; 2908 2909 /* 2910 * Please don't ever do this 2911 */ 2912 if (__predict_false(m->m_len == 0)) 2913 *m0 = m = collapse_pkthdr(m); 2914 2915 ctx = txq->ift_ctx; 2916 sctx = ctx->ifc_sctx; 2917 scctx = &ctx->ifc_softc_ctx; 2918 ifsd_m = txq->ift_sds.ifsd_m; 2919 ntxd = txq->ift_size; 2920 pidx = txq->ift_pidx; 2921 if (map != NULL) { 2922 uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; 2923 2924 err = bus_dmamap_load_mbuf_sg(tag, map, 2925 *m0, segs, nsegs, BUS_DMA_NOWAIT); 2926 if (err) 2927 return (err); 2928 ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; 2929 count = 0; 2930 m = *m0; 2931 do { 2932 if (__predict_false(m->m_len <= 0)) { 2933 tmp = m; 2934 m = m->m_next; 2935 tmp->m_next = NULL; 2936 m_free(tmp); 2937 continue; 2938 } 2939 m = m->m_next; 2940 count++; 2941 } while (m != NULL); 2942 if (count > *nsegs) { 2943 ifsd_m[pidx] = *m0; 2944 ifsd_m[pidx]->m_flags |= M_TOOBIG; 2945 return (0); 2946 } 2947 m = *m0; 2948 count = 0; 2949 do { 2950 next = (pidx + count) & (ntxd-1); 2951 MPASS(ifsd_m[next] == NULL); 2952 ifsd_m[next] = m; 2953 count++; 2954 tmp = m; 2955 m = m->m_next; 2956 } while (m != NULL); 2957 } else { 2958 int buflen, sgsize, maxsegsz, max_sgsize; 2959 vm_offset_t vaddr; 2960 vm_paddr_t curaddr; 2961 2962 count = i = 0; 2963 m = *m0; 2964 if (m->m_pkthdr.csum_flags & CSUM_TSO) 2965 maxsegsz = scctx->isc_tx_tso_segsize_max; 2966 else 2967 maxsegsz = sctx->isc_tx_maxsegsize; 2968 2969 do { 2970 if (__predict_false(m->m_len <= 0)) { 2971 tmp = m; 2972 m = m->m_next; 2973 tmp->m_next = NULL; 2974 m_free(tmp); 2975 continue; 2976 } 2977 buflen = m->m_len; 2978 vaddr = (vm_offset_t)m->m_data; 2979 /* 2980 * see if we can't be smarter about physically 2981 * contiguous mappings 2982 */ 2983 next = (pidx + count) & (ntxd-1); 2984 MPASS(ifsd_m[next] == NULL); 2985 #if MEMORY_LOGGING 2986 txq->ift_enqueued++; 2987 #endif 2988 ifsd_m[next] = m; 2989 while (buflen > 0) { 2990 if (i >= max_segs) 2991 goto err; 2992 max_sgsize = MIN(buflen, maxsegsz); 2993 curaddr = pmap_kextract(vaddr); 2994 sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); 2995 sgsize = MIN(sgsize, max_sgsize); 2996 segs[i].ds_addr = curaddr; 2997 segs[i].ds_len = sgsize; 2998 vaddr += sgsize; 2999 buflen -= sgsize; 3000 i++; 3001 } 3002 count++; 3003 tmp = m; 3004 m = m->m_next; 3005 } while (m != NULL); 3006 *nsegs = i; 3007 } 3008 return (0); 3009 err: 3010 *m0 = iflib_remove_mbuf(txq); 3011 return (EFBIG); 3012 } 3013 3014 static inline caddr_t 3015 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3016 { 3017 qidx_t size; 3018 int ntxd; 3019 caddr_t start, end, cur, next; 3020 3021 ntxd = txq->ift_size; 3022 size = txq->ift_txd_size[qid]; 3023 start = txq->ift_ifdi[qid].idi_vaddr; 3024 3025 if (__predict_false(size == 0)) 3026 return (start); 3027 cur = start + size*cidx; 3028 end = start + size*ntxd; 3029 next = CACHE_PTR_NEXT(cur); 3030 return (next < end ? next : start); 3031 } 3032 3033 static int 3034 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3035 { 3036 if_ctx_t ctx; 3037 if_shared_ctx_t sctx; 3038 if_softc_ctx_t scctx; 3039 bus_dma_segment_t *segs; 3040 struct mbuf *m_head; 3041 void *next_txd; 3042 bus_dmamap_t map; 3043 struct if_pkt_info pi; 3044 int remap = 0; 3045 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3046 bus_dma_tag_t desc_tag; 3047 3048 segs = txq->ift_segs; 3049 ctx = txq->ift_ctx; 3050 sctx = ctx->ifc_sctx; 3051 scctx = &ctx->ifc_softc_ctx; 3052 segs = txq->ift_segs; 3053 ntxd = txq->ift_size; 3054 m_head = *m_headp; 3055 map = NULL; 3056 3057 /* 3058 * If we're doing TSO the next descriptor to clean may be quite far ahead 3059 */ 3060 cidx = txq->ift_cidx; 3061 pidx = txq->ift_pidx; 3062 if (ctx->ifc_flags & IFC_PREFETCH) { 3063 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3064 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3065 next_txd = calc_next_txd(txq, cidx, 0); 3066 prefetch(next_txd); 3067 } 3068 3069 /* prefetch the next cache line of mbuf pointers and flags */ 3070 prefetch(&txq->ift_sds.ifsd_m[next]); 3071 if (txq->ift_sds.ifsd_map != NULL) { 3072 prefetch(&txq->ift_sds.ifsd_map[next]); 3073 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3074 prefetch(&txq->ift_sds.ifsd_flags[next]); 3075 } 3076 } else if (txq->ift_sds.ifsd_map != NULL) 3077 map = txq->ift_sds.ifsd_map[pidx]; 3078 3079 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3080 desc_tag = txq->ift_tso_desc_tag; 3081 max_segs = scctx->isc_tx_tso_segments_max; 3082 } else { 3083 desc_tag = txq->ift_desc_tag; 3084 max_segs = scctx->isc_tx_nsegments; 3085 } 3086 m_head = *m_headp; 3087 3088 pkt_info_zero(&pi); 3089 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3090 pi.ipi_pidx = pidx; 3091 pi.ipi_qsidx = txq->ift_id; 3092 pi.ipi_len = m_head->m_pkthdr.len; 3093 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3094 pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; 3095 3096 /* deliberate bitwise OR to make one condition */ 3097 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3098 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) 3099 return (err); 3100 m_head = *m_headp; 3101 } 3102 3103 retry: 3104 err = iflib_busdma_load_mbuf_sg(txq, desc_tag, map, m_headp, segs, &nsegs, max_segs, BUS_DMA_NOWAIT); 3105 defrag: 3106 if (__predict_false(err)) { 3107 switch (err) { 3108 case EFBIG: 3109 /* try collapse once and defrag once */ 3110 if (remap == 0) 3111 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3112 if (remap == 1) 3113 m_head = m_defrag(*m_headp, M_NOWAIT); 3114 remap++; 3115 if (__predict_false(m_head == NULL)) 3116 goto defrag_failed; 3117 txq->ift_mbuf_defrag++; 3118 *m_headp = m_head; 3119 goto retry; 3120 break; 3121 case ENOMEM: 3122 txq->ift_no_tx_dma_setup++; 3123 break; 3124 default: 3125 txq->ift_no_tx_dma_setup++; 3126 m_freem(*m_headp); 3127 DBG_COUNTER_INC(tx_frees); 3128 *m_headp = NULL; 3129 break; 3130 } 3131 txq->ift_map_failed++; 3132 DBG_COUNTER_INC(encap_load_mbuf_fail); 3133 return (err); 3134 } 3135 3136 /* 3137 * XXX assumes a 1 to 1 relationship between segments and 3138 * descriptors - this does not hold true on all drivers, e.g. 3139 * cxgb 3140 */ 3141 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3142 txq->ift_no_desc_avail++; 3143 if (map != NULL) 3144 bus_dmamap_unload(desc_tag, map); 3145 DBG_COUNTER_INC(encap_txq_avail_fail); 3146 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3147 GROUPTASK_ENQUEUE(&txq->ift_task); 3148 return (ENOBUFS); 3149 } 3150 /* 3151 * On Intel cards we can greatly reduce the number of TX interrupts 3152 * we see by only setting report status on every Nth descriptor. 3153 * However, this also means that the driver will need to keep track 3154 * of the descriptors that RS was set on to check them for the DD bit. 3155 */ 3156 txq->ift_rs_pending += nsegs + 1; 3157 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3158 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { 3159 pi.ipi_flags |= IPI_TX_INTR; 3160 txq->ift_rs_pending = 0; 3161 } 3162 3163 pi.ipi_segs = segs; 3164 pi.ipi_nsegs = nsegs; 3165 3166 MPASS(pidx >= 0 && pidx < txq->ift_size); 3167 #ifdef PKT_DEBUG 3168 print_pkt(&pi); 3169 #endif 3170 if (map != NULL) 3171 bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); 3172 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3173 if (map != NULL) 3174 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3175 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3176 DBG_COUNTER_INC(tx_encap); 3177 MPASS(pi.ipi_new_pidx < txq->ift_size); 3178 3179 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3180 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3181 ndesc += txq->ift_size; 3182 txq->ift_gen = 1; 3183 } 3184 /* 3185 * drivers can need as many as 3186 * two sentinels 3187 */ 3188 MPASS(ndesc <= pi.ipi_nsegs + 2); 3189 MPASS(pi.ipi_new_pidx != pidx); 3190 MPASS(ndesc > 0); 3191 txq->ift_in_use += ndesc; 3192 3193 /* 3194 * We update the last software descriptor again here because there may 3195 * be a sentinel and/or there may be more mbufs than segments 3196 */ 3197 txq->ift_pidx = pi.ipi_new_pidx; 3198 txq->ift_npending += pi.ipi_ndescs; 3199 } else if (__predict_false(err == EFBIG && remap < 2)) { 3200 *m_headp = m_head = iflib_remove_mbuf(txq); 3201 remap = 1; 3202 txq->ift_txd_encap_efbig++; 3203 goto defrag; 3204 } else 3205 DBG_COUNTER_INC(encap_txd_encap_fail); 3206 return (err); 3207 3208 defrag_failed: 3209 txq->ift_mbuf_defrag_failed++; 3210 txq->ift_map_failed++; 3211 m_freem(*m_headp); 3212 DBG_COUNTER_INC(tx_frees); 3213 *m_headp = NULL; 3214 return (ENOMEM); 3215 } 3216 3217 static void 3218 iflib_tx_desc_free(iflib_txq_t txq, int n) 3219 { 3220 int hasmap; 3221 uint32_t qsize, cidx, mask, gen; 3222 struct mbuf *m, **ifsd_m; 3223 uint8_t *ifsd_flags; 3224 bus_dmamap_t *ifsd_map; 3225 bool do_prefetch; 3226 3227 cidx = txq->ift_cidx; 3228 gen = txq->ift_gen; 3229 qsize = txq->ift_size; 3230 mask = qsize-1; 3231 hasmap = txq->ift_sds.ifsd_map != NULL; 3232 ifsd_flags = txq->ift_sds.ifsd_flags; 3233 ifsd_m = txq->ift_sds.ifsd_m; 3234 ifsd_map = txq->ift_sds.ifsd_map; 3235 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3236 3237 while (n--) { 3238 if (do_prefetch) { 3239 prefetch(ifsd_m[(cidx + 3) & mask]); 3240 prefetch(ifsd_m[(cidx + 4) & mask]); 3241 } 3242 if (ifsd_m[cidx] != NULL) { 3243 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3244 prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); 3245 if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { 3246 /* 3247 * does it matter if it's not the TSO tag? If so we'll 3248 * have to add the type to flags 3249 */ 3250 bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); 3251 ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; 3252 } 3253 if ((m = ifsd_m[cidx]) != NULL) { 3254 /* XXX we don't support any drivers that batch packets yet */ 3255 MPASS(m->m_nextpkt == NULL); 3256 /* if the number of clusters exceeds the number of segments 3257 * there won't be space on the ring to save a pointer to each 3258 * cluster so we simply free the list here 3259 */ 3260 if (m->m_flags & M_TOOBIG) { 3261 m_freem(m); 3262 } else { 3263 m_free(m); 3264 } 3265 ifsd_m[cidx] = NULL; 3266 #if MEMORY_LOGGING 3267 txq->ift_dequeued++; 3268 #endif 3269 DBG_COUNTER_INC(tx_frees); 3270 } 3271 } 3272 if (__predict_false(++cidx == qsize)) { 3273 cidx = 0; 3274 gen = 0; 3275 } 3276 } 3277 txq->ift_cidx = cidx; 3278 txq->ift_gen = gen; 3279 } 3280 3281 static __inline int 3282 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3283 { 3284 int reclaim; 3285 if_ctx_t ctx = txq->ift_ctx; 3286 3287 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3288 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3289 3290 /* 3291 * Need a rate-limiting check so that this isn't called every time 3292 */ 3293 iflib_tx_credits_update(ctx, txq); 3294 reclaim = DESC_RECLAIMABLE(txq); 3295 3296 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3297 #ifdef INVARIANTS 3298 if (iflib_verbose_debug) { 3299 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3300 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3301 reclaim, thresh); 3302 3303 } 3304 #endif 3305 return (0); 3306 } 3307 iflib_tx_desc_free(txq, reclaim); 3308 txq->ift_cleaned += reclaim; 3309 txq->ift_in_use -= reclaim; 3310 3311 return (reclaim); 3312 } 3313 3314 static struct mbuf ** 3315 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3316 { 3317 int next, size; 3318 struct mbuf **items; 3319 3320 size = r->size; 3321 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3322 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3323 3324 prefetch(items[(cidx + offset) & (size-1)]); 3325 if (remaining > 1) { 3326 prefetch2cachelines(&items[next]); 3327 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3328 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3329 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3330 } 3331 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3332 } 3333 3334 static void 3335 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3336 { 3337 3338 ifmp_ring_check_drainage(txq->ift_br, budget); 3339 } 3340 3341 static uint32_t 3342 iflib_txq_can_drain(struct ifmp_ring *r) 3343 { 3344 iflib_txq_t txq = r->cookie; 3345 if_ctx_t ctx = txq->ift_ctx; 3346 3347 return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || 3348 ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); 3349 } 3350 3351 static uint32_t 3352 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3353 { 3354 iflib_txq_t txq = r->cookie; 3355 if_ctx_t ctx = txq->ift_ctx; 3356 struct ifnet *ifp = ctx->ifc_ifp; 3357 struct mbuf **mp, *m; 3358 int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; 3359 int reclaimed, err, in_use_prev, desc_used; 3360 bool do_prefetch, ring, rang; 3361 3362 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3363 !LINK_ACTIVE(ctx))) { 3364 DBG_COUNTER_INC(txq_drain_notready); 3365 return (0); 3366 } 3367 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3368 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3369 avail = IDXDIFF(pidx, cidx, r->size); 3370 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3371 DBG_COUNTER_INC(txq_drain_flushing); 3372 for (i = 0; i < avail; i++) { 3373 m_free(r->items[(cidx + i) & (r->size-1)]); 3374 r->items[(cidx + i) & (r->size-1)] = NULL; 3375 } 3376 return (avail); 3377 } 3378 3379 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3380 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3381 CALLOUT_LOCK(txq); 3382 callout_stop(&txq->ift_timer); 3383 CALLOUT_UNLOCK(txq); 3384 DBG_COUNTER_INC(txq_drain_oactive); 3385 return (0); 3386 } 3387 if (reclaimed) 3388 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3389 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3390 count = MIN(avail, TX_BATCH_SIZE); 3391 #ifdef INVARIANTS 3392 if (iflib_verbose_debug) 3393 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3394 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3395 #endif 3396 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3397 avail = TXQ_AVAIL(txq); 3398 for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { 3399 int pidx_prev, rem = do_prefetch ? count - i : 0; 3400 3401 mp = _ring_peek_one(r, cidx, i, rem); 3402 MPASS(mp != NULL && *mp != NULL); 3403 if (__predict_false(*mp == (struct mbuf *)txq)) { 3404 consumed++; 3405 reclaimed++; 3406 continue; 3407 } 3408 in_use_prev = txq->ift_in_use; 3409 pidx_prev = txq->ift_pidx; 3410 err = iflib_encap(txq, mp); 3411 if (__predict_false(err)) { 3412 DBG_COUNTER_INC(txq_drain_encapfail); 3413 /* no room - bail out */ 3414 if (err == ENOBUFS) 3415 break; 3416 consumed++; 3417 DBG_COUNTER_INC(txq_drain_encapfail); 3418 /* we can't send this packet - skip it */ 3419 continue; 3420 } 3421 consumed++; 3422 pkt_sent++; 3423 m = *mp; 3424 DBG_COUNTER_INC(tx_sent); 3425 bytes_sent += m->m_pkthdr.len; 3426 mcast_sent += !!(m->m_flags & M_MCAST); 3427 avail = TXQ_AVAIL(txq); 3428 3429 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3430 desc_used += (txq->ift_in_use - in_use_prev); 3431 ETHER_BPF_MTAP(ifp, m); 3432 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3433 break; 3434 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3435 } 3436 3437 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3438 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3439 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3440 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3441 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3442 if (mcast_sent) 3443 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3444 #ifdef INVARIANTS 3445 if (iflib_verbose_debug) 3446 printf("consumed=%d\n", consumed); 3447 #endif 3448 return (consumed); 3449 } 3450 3451 static uint32_t 3452 iflib_txq_drain_always(struct ifmp_ring *r) 3453 { 3454 return (1); 3455 } 3456 3457 static uint32_t 3458 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3459 { 3460 int i, avail; 3461 struct mbuf **mp; 3462 iflib_txq_t txq; 3463 3464 txq = r->cookie; 3465 3466 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3467 CALLOUT_LOCK(txq); 3468 callout_stop(&txq->ift_timer); 3469 CALLOUT_UNLOCK(txq); 3470 3471 avail = IDXDIFF(pidx, cidx, r->size); 3472 for (i = 0; i < avail; i++) { 3473 mp = _ring_peek_one(r, cidx, i, avail - i); 3474 if (__predict_false(*mp == (struct mbuf *)txq)) 3475 continue; 3476 m_freem(*mp); 3477 } 3478 MPASS(ifmp_ring_is_stalled(r) == 0); 3479 return (avail); 3480 } 3481 3482 static void 3483 iflib_ifmp_purge(iflib_txq_t txq) 3484 { 3485 struct ifmp_ring *r; 3486 3487 r = txq->ift_br; 3488 r->drain = iflib_txq_drain_free; 3489 r->can_drain = iflib_txq_drain_always; 3490 3491 ifmp_ring_check_drainage(r, r->size); 3492 3493 r->drain = iflib_txq_drain; 3494 r->can_drain = iflib_txq_can_drain; 3495 } 3496 3497 static void 3498 _task_fn_tx(void *context) 3499 { 3500 iflib_txq_t txq = context; 3501 if_ctx_t ctx = txq->ift_ctx; 3502 struct ifnet *ifp = ctx->ifc_ifp; 3503 int rc; 3504 3505 #ifdef IFLIB_DIAGNOSTICS 3506 txq->ift_cpu_exec_count[curcpu]++; 3507 #endif 3508 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3509 return; 3510 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3511 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3512 netmap_tx_irq(ifp, txq->ift_id); 3513 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3514 return; 3515 } 3516 if (txq->ift_db_pending) 3517 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); 3518 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3519 if (ctx->ifc_flags & IFC_LEGACY) 3520 IFDI_INTR_ENABLE(ctx); 3521 else { 3522 rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3523 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3524 } 3525 } 3526 3527 static void 3528 _task_fn_rx(void *context) 3529 { 3530 iflib_rxq_t rxq = context; 3531 if_ctx_t ctx = rxq->ifr_ctx; 3532 bool more; 3533 int rc; 3534 uint16_t budget; 3535 3536 #ifdef IFLIB_DIAGNOSTICS 3537 rxq->ifr_cpu_exec_count[curcpu]++; 3538 #endif 3539 DBG_COUNTER_INC(task_fn_rxs); 3540 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3541 return; 3542 more = true; 3543 #ifdef DEV_NETMAP 3544 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3545 u_int work = 0; 3546 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3547 more = false; 3548 } 3549 } 3550 #endif 3551 budget = ctx->ifc_sysctl_rx_budget; 3552 if (budget == 0) 3553 budget = 16; /* XXX */ 3554 if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { 3555 if (ctx->ifc_flags & IFC_LEGACY) 3556 IFDI_INTR_ENABLE(ctx); 3557 else { 3558 DBG_COUNTER_INC(rx_intr_enables); 3559 rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3560 KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); 3561 } 3562 } 3563 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3564 return; 3565 if (more) 3566 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3567 } 3568 3569 static void 3570 _task_fn_admin(void *context) 3571 { 3572 if_ctx_t ctx = context; 3573 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3574 iflib_txq_t txq; 3575 int i; 3576 3577 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { 3578 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3579 return; 3580 } 3581 } 3582 3583 CTX_LOCK(ctx); 3584 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3585 CALLOUT_LOCK(txq); 3586 callout_stop(&txq->ift_timer); 3587 CALLOUT_UNLOCK(txq); 3588 } 3589 IFDI_UPDATE_ADMIN_STATUS(ctx); 3590 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3591 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); 3592 IFDI_LINK_INTR_ENABLE(ctx); 3593 if (ctx->ifc_flags & IFC_DO_RESET) { 3594 ctx->ifc_flags &= ~IFC_DO_RESET; 3595 iflib_if_init_locked(ctx); 3596 } 3597 CTX_UNLOCK(ctx); 3598 3599 if (LINK_ACTIVE(ctx) == 0) 3600 return; 3601 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3602 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3603 } 3604 3605 3606 static void 3607 _task_fn_iov(void *context) 3608 { 3609 if_ctx_t ctx = context; 3610 3611 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3612 return; 3613 3614 CTX_LOCK(ctx); 3615 IFDI_VFLR_HANDLE(ctx); 3616 CTX_UNLOCK(ctx); 3617 } 3618 3619 static int 3620 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3621 { 3622 int err; 3623 if_int_delay_info_t info; 3624 if_ctx_t ctx; 3625 3626 info = (if_int_delay_info_t)arg1; 3627 ctx = info->iidi_ctx; 3628 info->iidi_req = req; 3629 info->iidi_oidp = oidp; 3630 CTX_LOCK(ctx); 3631 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3632 CTX_UNLOCK(ctx); 3633 return (err); 3634 } 3635 3636 /********************************************************************* 3637 * 3638 * IFNET FUNCTIONS 3639 * 3640 **********************************************************************/ 3641 3642 static void 3643 iflib_if_init_locked(if_ctx_t ctx) 3644 { 3645 iflib_stop(ctx); 3646 iflib_init_locked(ctx); 3647 } 3648 3649 3650 static void 3651 iflib_if_init(void *arg) 3652 { 3653 if_ctx_t ctx = arg; 3654 3655 CTX_LOCK(ctx); 3656 iflib_if_init_locked(ctx); 3657 CTX_UNLOCK(ctx); 3658 } 3659 3660 static int 3661 iflib_if_transmit(if_t ifp, struct mbuf *m) 3662 { 3663 if_ctx_t ctx = if_getsoftc(ifp); 3664 3665 iflib_txq_t txq; 3666 int err, qidx; 3667 3668 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3669 DBG_COUNTER_INC(tx_frees); 3670 m_freem(m); 3671 return (ENOBUFS); 3672 } 3673 3674 MPASS(m->m_nextpkt == NULL); 3675 qidx = 0; 3676 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) 3677 qidx = QIDX(ctx, m); 3678 /* 3679 * XXX calculate buf_ring based on flowid (divvy up bits?) 3680 */ 3681 txq = &ctx->ifc_txqs[qidx]; 3682 3683 #ifdef DRIVER_BACKPRESSURE 3684 if (txq->ift_closed) { 3685 while (m != NULL) { 3686 next = m->m_nextpkt; 3687 m->m_nextpkt = NULL; 3688 m_freem(m); 3689 m = next; 3690 } 3691 return (ENOBUFS); 3692 } 3693 #endif 3694 #ifdef notyet 3695 qidx = count = 0; 3696 mp = marr; 3697 next = m; 3698 do { 3699 count++; 3700 next = next->m_nextpkt; 3701 } while (next != NULL); 3702 3703 if (count > nitems(marr)) 3704 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3705 /* XXX check nextpkt */ 3706 m_freem(m); 3707 /* XXX simplify for now */ 3708 DBG_COUNTER_INC(tx_frees); 3709 return (ENOBUFS); 3710 } 3711 for (next = m, i = 0; next != NULL; i++) { 3712 mp[i] = next; 3713 next = next->m_nextpkt; 3714 mp[i]->m_nextpkt = NULL; 3715 } 3716 #endif 3717 DBG_COUNTER_INC(tx_seen); 3718 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); 3719 3720 GROUPTASK_ENQUEUE(&txq->ift_task); 3721 if (err) { 3722 /* support forthcoming later */ 3723 #ifdef DRIVER_BACKPRESSURE 3724 txq->ift_closed = TRUE; 3725 #endif 3726 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3727 m_freem(m); 3728 } 3729 3730 return (err); 3731 } 3732 3733 static void 3734 iflib_if_qflush(if_t ifp) 3735 { 3736 if_ctx_t ctx = if_getsoftc(ifp); 3737 iflib_txq_t txq = ctx->ifc_txqs; 3738 int i; 3739 3740 CTX_LOCK(ctx); 3741 ctx->ifc_flags |= IFC_QFLUSH; 3742 CTX_UNLOCK(ctx); 3743 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 3744 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 3745 iflib_txq_check_drain(txq, 0); 3746 CTX_LOCK(ctx); 3747 ctx->ifc_flags &= ~IFC_QFLUSH; 3748 CTX_UNLOCK(ctx); 3749 3750 if_qflush(ifp); 3751 } 3752 3753 3754 #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 3755 IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 3756 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) 3757 3758 static int 3759 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 3760 { 3761 if_ctx_t ctx = if_getsoftc(ifp); 3762 struct ifreq *ifr = (struct ifreq *)data; 3763 #if defined(INET) || defined(INET6) 3764 struct ifaddr *ifa = (struct ifaddr *)data; 3765 #endif 3766 bool avoid_reset = FALSE; 3767 int err = 0, reinit = 0, bits; 3768 3769 switch (command) { 3770 case SIOCSIFADDR: 3771 #ifdef INET 3772 if (ifa->ifa_addr->sa_family == AF_INET) 3773 avoid_reset = TRUE; 3774 #endif 3775 #ifdef INET6 3776 if (ifa->ifa_addr->sa_family == AF_INET6) 3777 avoid_reset = TRUE; 3778 #endif 3779 /* 3780 ** Calling init results in link renegotiation, 3781 ** so we avoid doing it when possible. 3782 */ 3783 if (avoid_reset) { 3784 if_setflagbits(ifp, IFF_UP,0); 3785 if (!(if_getdrvflags(ifp)& IFF_DRV_RUNNING)) 3786 reinit = 1; 3787 #ifdef INET 3788 if (!(if_getflags(ifp) & IFF_NOARP)) 3789 arp_ifinit(ifp, ifa); 3790 #endif 3791 } else 3792 err = ether_ioctl(ifp, command, data); 3793 break; 3794 case SIOCSIFMTU: 3795 CTX_LOCK(ctx); 3796 if (ifr->ifr_mtu == if_getmtu(ifp)) { 3797 CTX_UNLOCK(ctx); 3798 break; 3799 } 3800 bits = if_getdrvflags(ifp); 3801 /* stop the driver and free any clusters before proceeding */ 3802 iflib_stop(ctx); 3803 3804 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 3805 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 3806 ctx->ifc_flags |= IFC_MULTISEG; 3807 else 3808 ctx->ifc_flags &= ~IFC_MULTISEG; 3809 err = if_setmtu(ifp, ifr->ifr_mtu); 3810 } 3811 iflib_init_locked(ctx); 3812 if_setdrvflags(ifp, bits); 3813 CTX_UNLOCK(ctx); 3814 break; 3815 case SIOCSIFFLAGS: 3816 CTX_LOCK(ctx); 3817 if (if_getflags(ifp) & IFF_UP) { 3818 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3819 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 3820 (IFF_PROMISC | IFF_ALLMULTI)) { 3821 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 3822 } 3823 } else 3824 reinit = 1; 3825 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3826 iflib_stop(ctx); 3827 } 3828 ctx->ifc_if_flags = if_getflags(ifp); 3829 CTX_UNLOCK(ctx); 3830 break; 3831 case SIOCADDMULTI: 3832 case SIOCDELMULTI: 3833 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3834 CTX_LOCK(ctx); 3835 IFDI_INTR_DISABLE(ctx); 3836 IFDI_MULTI_SET(ctx); 3837 IFDI_INTR_ENABLE(ctx); 3838 CTX_UNLOCK(ctx); 3839 } 3840 break; 3841 case SIOCSIFMEDIA: 3842 CTX_LOCK(ctx); 3843 IFDI_MEDIA_SET(ctx); 3844 CTX_UNLOCK(ctx); 3845 /* falls thru */ 3846 case SIOCGIFMEDIA: 3847 err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); 3848 break; 3849 case SIOCGI2C: 3850 { 3851 struct ifi2creq i2c; 3852 3853 err = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 3854 if (err != 0) 3855 break; 3856 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 3857 err = EINVAL; 3858 break; 3859 } 3860 if (i2c.len > sizeof(i2c.data)) { 3861 err = EINVAL; 3862 break; 3863 } 3864 3865 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 3866 err = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 3867 break; 3868 } 3869 case SIOCSIFCAP: 3870 { 3871 int mask, setmask; 3872 3873 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3874 setmask = 0; 3875 #ifdef TCP_OFFLOAD 3876 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 3877 #endif 3878 setmask |= (mask & IFCAP_FLAGS); 3879 3880 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) 3881 setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 3882 if ((mask & IFCAP_WOL) && 3883 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) 3884 setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); 3885 if_vlancap(ifp); 3886 /* 3887 * want to ensure that traffic has stopped before we change any of the flags 3888 */ 3889 if (setmask) { 3890 CTX_LOCK(ctx); 3891 bits = if_getdrvflags(ifp); 3892 if (bits & IFF_DRV_RUNNING) 3893 iflib_stop(ctx); 3894 if_togglecapenable(ifp, setmask); 3895 if (bits & IFF_DRV_RUNNING) 3896 iflib_init_locked(ctx); 3897 if_setdrvflags(ifp, bits); 3898 CTX_UNLOCK(ctx); 3899 } 3900 break; 3901 } 3902 case SIOCGPRIVATE_0: 3903 case SIOCSDRVSPEC: 3904 case SIOCGDRVSPEC: 3905 CTX_LOCK(ctx); 3906 err = IFDI_PRIV_IOCTL(ctx, command, data); 3907 CTX_UNLOCK(ctx); 3908 break; 3909 default: 3910 err = ether_ioctl(ifp, command, data); 3911 break; 3912 } 3913 if (reinit) 3914 iflib_if_init(ctx); 3915 return (err); 3916 } 3917 3918 static uint64_t 3919 iflib_if_get_counter(if_t ifp, ift_counter cnt) 3920 { 3921 if_ctx_t ctx = if_getsoftc(ifp); 3922 3923 return (IFDI_GET_COUNTER(ctx, cnt)); 3924 } 3925 3926 /********************************************************************* 3927 * 3928 * OTHER FUNCTIONS EXPORTED TO THE STACK 3929 * 3930 **********************************************************************/ 3931 3932 static void 3933 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 3934 { 3935 if_ctx_t ctx = if_getsoftc(ifp); 3936 3937 if ((void *)ctx != arg) 3938 return; 3939 3940 if ((vtag == 0) || (vtag > 4095)) 3941 return; 3942 3943 CTX_LOCK(ctx); 3944 IFDI_VLAN_REGISTER(ctx, vtag); 3945 /* Re-init to load the changes */ 3946 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3947 iflib_if_init_locked(ctx); 3948 CTX_UNLOCK(ctx); 3949 } 3950 3951 static void 3952 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 3953 { 3954 if_ctx_t ctx = if_getsoftc(ifp); 3955 3956 if ((void *)ctx != arg) 3957 return; 3958 3959 if ((vtag == 0) || (vtag > 4095)) 3960 return; 3961 3962 CTX_LOCK(ctx); 3963 IFDI_VLAN_UNREGISTER(ctx, vtag); 3964 /* Re-init to load the changes */ 3965 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 3966 iflib_if_init_locked(ctx); 3967 CTX_UNLOCK(ctx); 3968 } 3969 3970 static void 3971 iflib_led_func(void *arg, int onoff) 3972 { 3973 if_ctx_t ctx = arg; 3974 3975 CTX_LOCK(ctx); 3976 IFDI_LED_FUNC(ctx, onoff); 3977 CTX_UNLOCK(ctx); 3978 } 3979 3980 /********************************************************************* 3981 * 3982 * BUS FUNCTION DEFINITIONS 3983 * 3984 **********************************************************************/ 3985 3986 int 3987 iflib_device_probe(device_t dev) 3988 { 3989 pci_vendor_info_t *ent; 3990 3991 uint16_t pci_vendor_id, pci_device_id; 3992 uint16_t pci_subvendor_id, pci_subdevice_id; 3993 uint16_t pci_rev_id; 3994 if_shared_ctx_t sctx; 3995 3996 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 3997 return (ENOTSUP); 3998 3999 pci_vendor_id = pci_get_vendor(dev); 4000 pci_device_id = pci_get_device(dev); 4001 pci_subvendor_id = pci_get_subvendor(dev); 4002 pci_subdevice_id = pci_get_subdevice(dev); 4003 pci_rev_id = pci_get_revid(dev); 4004 if (sctx->isc_parse_devinfo != NULL) 4005 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4006 4007 ent = sctx->isc_vendor_info; 4008 while (ent->pvi_vendor_id != 0) { 4009 if (pci_vendor_id != ent->pvi_vendor_id) { 4010 ent++; 4011 continue; 4012 } 4013 if ((pci_device_id == ent->pvi_device_id) && 4014 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4015 (ent->pvi_subvendor_id == 0)) && 4016 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4017 (ent->pvi_subdevice_id == 0)) && 4018 ((pci_rev_id == ent->pvi_rev_id) || 4019 (ent->pvi_rev_id == 0))) { 4020 4021 device_set_desc_copy(dev, ent->pvi_name); 4022 /* this needs to be changed to zero if the bus probing code 4023 * ever stops re-probing on best match because the sctx 4024 * may have its values over written by register calls 4025 * in subsequent probes 4026 */ 4027 return (BUS_PROBE_DEFAULT); 4028 } 4029 ent++; 4030 } 4031 return (ENXIO); 4032 } 4033 4034 int 4035 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4036 { 4037 int err, rid, msix, msix_bar; 4038 if_ctx_t ctx; 4039 if_t ifp; 4040 if_softc_ctx_t scctx; 4041 int i; 4042 uint16_t main_txq; 4043 uint16_t main_rxq; 4044 4045 4046 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4047 4048 if (sc == NULL) { 4049 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4050 device_set_softc(dev, ctx); 4051 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4052 } 4053 4054 ctx->ifc_sctx = sctx; 4055 ctx->ifc_dev = dev; 4056 ctx->ifc_softc = sc; 4057 4058 if ((err = iflib_register(ctx)) != 0) { 4059 device_printf(dev, "iflib_register failed %d\n", err); 4060 return (err); 4061 } 4062 iflib_add_device_sysctl_pre(ctx); 4063 4064 scctx = &ctx->ifc_softc_ctx; 4065 ifp = ctx->ifc_ifp; 4066 4067 /* 4068 * XXX sanity check that ntxd & nrxd are a power of 2 4069 */ 4070 if (ctx->ifc_sysctl_ntxqs != 0) 4071 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4072 if (ctx->ifc_sysctl_nrxqs != 0) 4073 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4074 4075 for (i = 0; i < sctx->isc_ntxqs; i++) { 4076 if (ctx->ifc_sysctl_ntxds[i] != 0) 4077 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4078 else 4079 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4080 } 4081 4082 for (i = 0; i < sctx->isc_nrxqs; i++) { 4083 if (ctx->ifc_sysctl_nrxds[i] != 0) 4084 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4085 else 4086 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4087 } 4088 4089 for (i = 0; i < sctx->isc_nrxqs; i++) { 4090 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4091 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4092 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4093 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4094 } 4095 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4096 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4097 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4098 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4099 } 4100 } 4101 4102 for (i = 0; i < sctx->isc_ntxqs; i++) { 4103 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4104 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4105 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4106 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4107 } 4108 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4109 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4110 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4111 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4112 } 4113 } 4114 4115 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4116 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4117 return (err); 4118 } 4119 _iflib_pre_assert(scctx); 4120 ctx->ifc_txrx = *scctx->isc_txrx; 4121 4122 #ifdef INVARIANTS 4123 MPASS(scctx->isc_capenable); 4124 if (scctx->isc_capenable & IFCAP_TXCSUM) 4125 MPASS(scctx->isc_tx_csum_flags); 4126 #endif 4127 4128 if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4129 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); 4130 4131 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4132 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4133 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4134 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4135 4136 #ifdef ACPI_DMAR 4137 if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) 4138 ctx->ifc_flags |= IFC_DMAR; 4139 #elif !(defined(__i386__) || defined(__amd64__)) 4140 /* set unconditionally for !x86 */ 4141 ctx->ifc_flags |= IFC_DMAR; 4142 #endif 4143 4144 msix_bar = scctx->isc_msix_bar; 4145 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4146 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4147 4148 /* XXX change for per-queue sizes */ 4149 device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", 4150 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4151 for (i = 0; i < sctx->isc_nrxqs; i++) { 4152 if (!powerof2(scctx->isc_nrxd[i])) { 4153 /* round down instead? */ 4154 device_printf(dev, "# rx descriptors must be a power of 2\n"); 4155 err = EINVAL; 4156 goto fail; 4157 } 4158 } 4159 for (i = 0; i < sctx->isc_ntxqs; i++) { 4160 if (!powerof2(scctx->isc_ntxd[i])) { 4161 device_printf(dev, 4162 "# tx descriptors must be a power of 2"); 4163 err = EINVAL; 4164 goto fail; 4165 } 4166 } 4167 4168 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4169 MAX_SINGLE_PACKET_FRACTION) 4170 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4171 MAX_SINGLE_PACKET_FRACTION); 4172 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4173 MAX_SINGLE_PACKET_FRACTION) 4174 scctx->isc_tx_tso_segments_max = max(1, 4175 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4176 4177 /* 4178 * Protect the stack against modern hardware 4179 */ 4180 if (scctx->isc_tx_tso_size_max > FREEBSD_TSO_SIZE_MAX) 4181 scctx->isc_tx_tso_size_max = FREEBSD_TSO_SIZE_MAX; 4182 4183 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4184 ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; 4185 ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; 4186 ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; 4187 if (scctx->isc_rss_table_size == 0) 4188 scctx->isc_rss_table_size = 64; 4189 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4190 4191 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4192 /* XXX format name */ 4193 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); 4194 /* 4195 ** Now setup MSI or MSI/X, should 4196 ** return us the number of supported 4197 ** vectors. (Will be 1 for MSI) 4198 */ 4199 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4200 msix = scctx->isc_vectors; 4201 } else if (scctx->isc_msix_bar != 0) 4202 /* 4203 * The simple fact that isc_msix_bar is not 0 does not mean we 4204 * we have a good value there that is known to work. 4205 */ 4206 msix = iflib_msix_init(ctx); 4207 else { 4208 scctx->isc_vectors = 1; 4209 scctx->isc_ntxqsets = 1; 4210 scctx->isc_nrxqsets = 1; 4211 scctx->isc_intr = IFLIB_INTR_LEGACY; 4212 msix = 0; 4213 } 4214 /* Get memory for the station queues */ 4215 if ((err = iflib_queues_alloc(ctx))) { 4216 device_printf(dev, "Unable to allocate queue memory\n"); 4217 goto fail; 4218 } 4219 4220 if ((err = iflib_qset_structures_setup(ctx))) { 4221 device_printf(dev, "qset structure setup failed %d\n", err); 4222 goto fail_queues; 4223 } 4224 4225 /* 4226 * Group taskqueues aren't properly set up until SMP is started, 4227 * so we disable interrupts until we can handle them post 4228 * SI_SUB_SMP. 4229 * 4230 * XXX: disabling interrupts doesn't actually work, at least for 4231 * the non-MSI case. When they occur before SI_SUB_SMP completes, 4232 * we do null handling and depend on this not causing too large an 4233 * interrupt storm. 4234 */ 4235 IFDI_INTR_DISABLE(ctx); 4236 if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { 4237 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); 4238 goto fail_intr_free; 4239 } 4240 if (msix <= 1) { 4241 rid = 0; 4242 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4243 MPASS(msix == 1); 4244 rid = 1; 4245 } 4246 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4247 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4248 goto fail_intr_free; 4249 } 4250 } 4251 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac); 4252 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4253 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4254 goto fail_detach; 4255 } 4256 if ((err = iflib_netmap_attach(ctx))) { 4257 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4258 goto fail_detach; 4259 } 4260 *ctxp = ctx; 4261 4262 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4263 iflib_add_device_sysctl_post(ctx); 4264 ctx->ifc_flags |= IFC_INIT_DONE; 4265 return (0); 4266 fail_detach: 4267 ether_ifdetach(ctx->ifc_ifp); 4268 fail_intr_free: 4269 if (scctx->isc_intr == IFLIB_INTR_MSIX || scctx->isc_intr == IFLIB_INTR_MSI) 4270 pci_release_msi(ctx->ifc_dev); 4271 fail_queues: 4272 /* XXX free queues */ 4273 fail: 4274 IFDI_DETACH(ctx); 4275 return (err); 4276 } 4277 4278 int 4279 iflib_device_attach(device_t dev) 4280 { 4281 if_ctx_t ctx; 4282 if_shared_ctx_t sctx; 4283 4284 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4285 return (ENOTSUP); 4286 4287 pci_enable_busmaster(dev); 4288 4289 return (iflib_device_register(dev, NULL, sctx, &ctx)); 4290 } 4291 4292 int 4293 iflib_device_deregister(if_ctx_t ctx) 4294 { 4295 if_t ifp = ctx->ifc_ifp; 4296 iflib_txq_t txq; 4297 iflib_rxq_t rxq; 4298 device_t dev = ctx->ifc_dev; 4299 int i, j; 4300 struct taskqgroup *tqg; 4301 iflib_fl_t fl; 4302 4303 /* Make sure VLANS are not using driver */ 4304 if (if_vlantrunkinuse(ifp)) { 4305 device_printf(dev,"Vlan in use, detach first\n"); 4306 return (EBUSY); 4307 } 4308 4309 CTX_LOCK(ctx); 4310 ctx->ifc_in_detach = 1; 4311 iflib_stop(ctx); 4312 CTX_UNLOCK(ctx); 4313 4314 /* Unregister VLAN events */ 4315 if (ctx->ifc_vlan_attach_event != NULL) 4316 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 4317 if (ctx->ifc_vlan_detach_event != NULL) 4318 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 4319 4320 iflib_netmap_detach(ifp); 4321 ether_ifdetach(ifp); 4322 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 4323 CTX_LOCK_DESTROY(ctx); 4324 if (ctx->ifc_led_dev != NULL) 4325 led_destroy(ctx->ifc_led_dev); 4326 /* XXX drain any dependent tasks */ 4327 tqg = qgroup_if_io_tqg; 4328 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 4329 callout_drain(&txq->ift_timer); 4330 if (txq->ift_task.gt_uniq != NULL) 4331 taskqgroup_detach(tqg, &txq->ift_task); 4332 } 4333 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4334 if (rxq->ifr_task.gt_uniq != NULL) 4335 taskqgroup_detach(tqg, &rxq->ifr_task); 4336 4337 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4338 free(fl->ifl_rx_bitmap, M_IFLIB); 4339 4340 } 4341 tqg = qgroup_if_config_tqg; 4342 if (ctx->ifc_admin_task.gt_uniq != NULL) 4343 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 4344 if (ctx->ifc_vflr_task.gt_uniq != NULL) 4345 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 4346 4347 IFDI_DETACH(ctx); 4348 device_set_softc(ctx->ifc_dev, NULL); 4349 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 4350 pci_release_msi(dev); 4351 } 4352 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 4353 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 4354 } 4355 if (ctx->ifc_msix_mem != NULL) { 4356 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 4357 ctx->ifc_softc_ctx.isc_msix_bar, ctx->ifc_msix_mem); 4358 ctx->ifc_msix_mem = NULL; 4359 } 4360 4361 bus_generic_detach(dev); 4362 if_free(ifp); 4363 4364 iflib_tx_structures_free(ctx); 4365 iflib_rx_structures_free(ctx); 4366 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4367 free(ctx->ifc_softc, M_IFLIB); 4368 free(ctx, M_IFLIB); 4369 return (0); 4370 } 4371 4372 4373 int 4374 iflib_device_detach(device_t dev) 4375 { 4376 if_ctx_t ctx = device_get_softc(dev); 4377 4378 return (iflib_device_deregister(ctx)); 4379 } 4380 4381 int 4382 iflib_device_suspend(device_t dev) 4383 { 4384 if_ctx_t ctx = device_get_softc(dev); 4385 4386 CTX_LOCK(ctx); 4387 IFDI_SUSPEND(ctx); 4388 CTX_UNLOCK(ctx); 4389 4390 return bus_generic_suspend(dev); 4391 } 4392 int 4393 iflib_device_shutdown(device_t dev) 4394 { 4395 if_ctx_t ctx = device_get_softc(dev); 4396 4397 CTX_LOCK(ctx); 4398 IFDI_SHUTDOWN(ctx); 4399 CTX_UNLOCK(ctx); 4400 4401 return bus_generic_suspend(dev); 4402 } 4403 4404 4405 int 4406 iflib_device_resume(device_t dev) 4407 { 4408 if_ctx_t ctx = device_get_softc(dev); 4409 iflib_txq_t txq = ctx->ifc_txqs; 4410 4411 CTX_LOCK(ctx); 4412 IFDI_RESUME(ctx); 4413 iflib_init_locked(ctx); 4414 CTX_UNLOCK(ctx); 4415 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 4416 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4417 4418 return (bus_generic_resume(dev)); 4419 } 4420 4421 int 4422 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 4423 { 4424 int error; 4425 if_ctx_t ctx = device_get_softc(dev); 4426 4427 CTX_LOCK(ctx); 4428 error = IFDI_IOV_INIT(ctx, num_vfs, params); 4429 CTX_UNLOCK(ctx); 4430 4431 return (error); 4432 } 4433 4434 void 4435 iflib_device_iov_uninit(device_t dev) 4436 { 4437 if_ctx_t ctx = device_get_softc(dev); 4438 4439 CTX_LOCK(ctx); 4440 IFDI_IOV_UNINIT(ctx); 4441 CTX_UNLOCK(ctx); 4442 } 4443 4444 int 4445 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 4446 { 4447 int error; 4448 if_ctx_t ctx = device_get_softc(dev); 4449 4450 CTX_LOCK(ctx); 4451 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 4452 CTX_UNLOCK(ctx); 4453 4454 return (error); 4455 } 4456 4457 /********************************************************************* 4458 * 4459 * MODULE FUNCTION DEFINITIONS 4460 * 4461 **********************************************************************/ 4462 4463 /* 4464 * - Start a fast taskqueue thread for each core 4465 * - Start a taskqueue for control operations 4466 */ 4467 static int 4468 iflib_module_init(void) 4469 { 4470 return (0); 4471 } 4472 4473 static int 4474 iflib_module_event_handler(module_t mod, int what, void *arg) 4475 { 4476 int err; 4477 4478 switch (what) { 4479 case MOD_LOAD: 4480 if ((err = iflib_module_init()) != 0) 4481 return (err); 4482 break; 4483 case MOD_UNLOAD: 4484 return (EBUSY); 4485 default: 4486 return (EOPNOTSUPP); 4487 } 4488 4489 return (0); 4490 } 4491 4492 /********************************************************************* 4493 * 4494 * PUBLIC FUNCTION DEFINITIONS 4495 * ordered as in iflib.h 4496 * 4497 **********************************************************************/ 4498 4499 4500 static void 4501 _iflib_assert(if_shared_ctx_t sctx) 4502 { 4503 MPASS(sctx->isc_tx_maxsize); 4504 MPASS(sctx->isc_tx_maxsegsize); 4505 4506 MPASS(sctx->isc_rx_maxsize); 4507 MPASS(sctx->isc_rx_nsegments); 4508 MPASS(sctx->isc_rx_maxsegsize); 4509 4510 MPASS(sctx->isc_nrxd_min[0]); 4511 MPASS(sctx->isc_nrxd_max[0]); 4512 MPASS(sctx->isc_nrxd_default[0]); 4513 MPASS(sctx->isc_ntxd_min[0]); 4514 MPASS(sctx->isc_ntxd_max[0]); 4515 MPASS(sctx->isc_ntxd_default[0]); 4516 } 4517 4518 static void 4519 _iflib_pre_assert(if_softc_ctx_t scctx) 4520 { 4521 4522 MPASS(scctx->isc_txrx->ift_txd_encap); 4523 MPASS(scctx->isc_txrx->ift_txd_flush); 4524 MPASS(scctx->isc_txrx->ift_txd_credits_update); 4525 MPASS(scctx->isc_txrx->ift_rxd_available); 4526 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 4527 MPASS(scctx->isc_txrx->ift_rxd_refill); 4528 MPASS(scctx->isc_txrx->ift_rxd_flush); 4529 } 4530 4531 static int 4532 iflib_register(if_ctx_t ctx) 4533 { 4534 if_shared_ctx_t sctx = ctx->ifc_sctx; 4535 driver_t *driver = sctx->isc_driver; 4536 device_t dev = ctx->ifc_dev; 4537 if_t ifp; 4538 4539 _iflib_assert(sctx); 4540 4541 CTX_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 4542 4543 ifp = ctx->ifc_ifp = if_gethandle(IFT_ETHER); 4544 if (ifp == NULL) { 4545 device_printf(dev, "can not allocate ifnet structure\n"); 4546 return (ENOMEM); 4547 } 4548 4549 /* 4550 * Initialize our context's device specific methods 4551 */ 4552 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 4553 kobj_class_compile((kobj_class_t) driver); 4554 driver->refs++; 4555 4556 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 4557 if_setsoftc(ifp, ctx); 4558 if_setdev(ifp, dev); 4559 if_setinitfn(ifp, iflib_if_init); 4560 if_setioctlfn(ifp, iflib_if_ioctl); 4561 if_settransmitfn(ifp, iflib_if_transmit); 4562 if_setqflushfn(ifp, iflib_if_qflush); 4563 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 4564 4565 ctx->ifc_vlan_attach_event = 4566 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 4567 EVENTHANDLER_PRI_FIRST); 4568 ctx->ifc_vlan_detach_event = 4569 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 4570 EVENTHANDLER_PRI_FIRST); 4571 4572 ifmedia_init(&ctx->ifc_media, IFM_IMASK, 4573 iflib_media_change, iflib_media_status); 4574 4575 return (0); 4576 } 4577 4578 4579 static int 4580 iflib_queues_alloc(if_ctx_t ctx) 4581 { 4582 if_shared_ctx_t sctx = ctx->ifc_sctx; 4583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4584 device_t dev = ctx->ifc_dev; 4585 int nrxqsets = scctx->isc_nrxqsets; 4586 int ntxqsets = scctx->isc_ntxqsets; 4587 iflib_txq_t txq; 4588 iflib_rxq_t rxq; 4589 iflib_fl_t fl = NULL; 4590 int i, j, cpu, err, txconf, rxconf; 4591 iflib_dma_info_t ifdip; 4592 uint32_t *rxqsizes = scctx->isc_rxqsizes; 4593 uint32_t *txqsizes = scctx->isc_txqsizes; 4594 uint8_t nrxqs = sctx->isc_nrxqs; 4595 uint8_t ntxqs = sctx->isc_ntxqs; 4596 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 4597 caddr_t *vaddrs; 4598 uint64_t *paddrs; 4599 struct ifmp_ring **brscp; 4600 4601 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 4602 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 4603 4604 brscp = NULL; 4605 txq = NULL; 4606 rxq = NULL; 4607 4608 /* Allocate the TX ring struct memory */ 4609 if (!(txq = 4610 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 4611 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4612 device_printf(dev, "Unable to allocate TX ring memory\n"); 4613 err = ENOMEM; 4614 goto fail; 4615 } 4616 4617 /* Now allocate the RX */ 4618 if (!(rxq = 4619 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 4620 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 4621 device_printf(dev, "Unable to allocate RX ring memory\n"); 4622 err = ENOMEM; 4623 goto rx_fail; 4624 } 4625 4626 ctx->ifc_txqs = txq; 4627 ctx->ifc_rxqs = rxq; 4628 4629 /* 4630 * XXX handle allocation failure 4631 */ 4632 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 4633 /* Set up some basics */ 4634 4635 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4636 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4637 err = ENOMEM; 4638 goto err_tx_desc; 4639 } 4640 txq->ift_ifdi = ifdip; 4641 for (j = 0; j < ntxqs; j++, ifdip++) { 4642 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4643 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4644 err = ENOMEM; 4645 goto err_tx_desc; 4646 } 4647 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 4648 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 4649 } 4650 txq->ift_ctx = ctx; 4651 txq->ift_id = i; 4652 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 4653 txq->ift_br_offset = 1; 4654 } else { 4655 txq->ift_br_offset = 0; 4656 } 4657 /* XXX fix this */ 4658 txq->ift_timer.c_cpu = cpu; 4659 4660 if (iflib_txsd_alloc(txq)) { 4661 device_printf(dev, "Critical Failure setting up TX buffers\n"); 4662 err = ENOMEM; 4663 goto err_tx_desc; 4664 } 4665 4666 /* Initialize the TX lock */ 4667 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", 4668 device_get_nameunit(dev), txq->ift_id); 4669 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 4670 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 4671 4672 snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", 4673 device_get_nameunit(dev), txq->ift_id); 4674 4675 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 4676 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 4677 if (err) { 4678 /* XXX free any allocated rings */ 4679 device_printf(dev, "Unable to allocate buf_ring\n"); 4680 goto err_tx_desc; 4681 } 4682 } 4683 4684 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 4685 /* Set up some basics */ 4686 4687 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { 4688 device_printf(dev, "failed to allocate iflib_dma_info\n"); 4689 err = ENOMEM; 4690 goto err_tx_desc; 4691 } 4692 4693 rxq->ifr_ifdi = ifdip; 4694 /* XXX this needs to be changed if #rx queues != #tx queues */ 4695 rxq->ifr_ntxqirq = 1; 4696 rxq->ifr_txqid[0] = i; 4697 for (j = 0; j < nrxqs; j++, ifdip++) { 4698 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { 4699 device_printf(dev, "Unable to allocate Descriptor memory\n"); 4700 err = ENOMEM; 4701 goto err_tx_desc; 4702 } 4703 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 4704 } 4705 rxq->ifr_ctx = ctx; 4706 rxq->ifr_id = i; 4707 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 4708 rxq->ifr_fl_offset = 1; 4709 } else { 4710 rxq->ifr_fl_offset = 0; 4711 } 4712 rxq->ifr_nfl = nfree_lists; 4713 if (!(fl = 4714 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 4715 device_printf(dev, "Unable to allocate free list memory\n"); 4716 err = ENOMEM; 4717 goto err_tx_desc; 4718 } 4719 rxq->ifr_fl = fl; 4720 for (j = 0; j < nfree_lists; j++) { 4721 fl[j].ifl_rxq = rxq; 4722 fl[j].ifl_id = j; 4723 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 4724 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 4725 } 4726 /* Allocate receive buffers for the ring*/ 4727 if (iflib_rxsd_alloc(rxq)) { 4728 device_printf(dev, 4729 "Critical Failure setting up receive buffers\n"); 4730 err = ENOMEM; 4731 goto err_rx_desc; 4732 } 4733 4734 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 4735 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); 4736 } 4737 4738 /* TXQs */ 4739 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4740 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 4741 for (i = 0; i < ntxqsets; i++) { 4742 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 4743 4744 for (j = 0; j < ntxqs; j++, di++) { 4745 vaddrs[i*ntxqs + j] = di->idi_vaddr; 4746 paddrs[i*ntxqs + j] = di->idi_paddr; 4747 } 4748 } 4749 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 4750 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4751 iflib_tx_structures_free(ctx); 4752 free(vaddrs, M_IFLIB); 4753 free(paddrs, M_IFLIB); 4754 goto err_rx_desc; 4755 } 4756 free(vaddrs, M_IFLIB); 4757 free(paddrs, M_IFLIB); 4758 4759 /* RXQs */ 4760 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4761 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 4762 for (i = 0; i < nrxqsets; i++) { 4763 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 4764 4765 for (j = 0; j < nrxqs; j++, di++) { 4766 vaddrs[i*nrxqs + j] = di->idi_vaddr; 4767 paddrs[i*nrxqs + j] = di->idi_paddr; 4768 } 4769 } 4770 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 4771 device_printf(ctx->ifc_dev, "device queue allocation failed\n"); 4772 iflib_tx_structures_free(ctx); 4773 free(vaddrs, M_IFLIB); 4774 free(paddrs, M_IFLIB); 4775 goto err_rx_desc; 4776 } 4777 free(vaddrs, M_IFLIB); 4778 free(paddrs, M_IFLIB); 4779 4780 return (0); 4781 4782 /* XXX handle allocation failure changes */ 4783 err_rx_desc: 4784 err_tx_desc: 4785 if (ctx->ifc_rxqs != NULL) 4786 free(ctx->ifc_rxqs, M_IFLIB); 4787 ctx->ifc_rxqs = NULL; 4788 if (ctx->ifc_txqs != NULL) 4789 free(ctx->ifc_txqs, M_IFLIB); 4790 ctx->ifc_txqs = NULL; 4791 rx_fail: 4792 if (brscp != NULL) 4793 free(brscp, M_IFLIB); 4794 if (rxq != NULL) 4795 free(rxq, M_IFLIB); 4796 if (txq != NULL) 4797 free(txq, M_IFLIB); 4798 fail: 4799 return (err); 4800 } 4801 4802 static int 4803 iflib_tx_structures_setup(if_ctx_t ctx) 4804 { 4805 iflib_txq_t txq = ctx->ifc_txqs; 4806 int i; 4807 4808 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4809 iflib_txq_setup(txq); 4810 4811 return (0); 4812 } 4813 4814 static void 4815 iflib_tx_structures_free(if_ctx_t ctx) 4816 { 4817 iflib_txq_t txq = ctx->ifc_txqs; 4818 int i, j; 4819 4820 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 4821 iflib_txq_destroy(txq); 4822 for (j = 0; j < ctx->ifc_nhwtxqs; j++) 4823 iflib_dma_free(&txq->ift_ifdi[j]); 4824 } 4825 free(ctx->ifc_txqs, M_IFLIB); 4826 ctx->ifc_txqs = NULL; 4827 IFDI_QUEUES_FREE(ctx); 4828 } 4829 4830 /********************************************************************* 4831 * 4832 * Initialize all receive rings. 4833 * 4834 **********************************************************************/ 4835 static int 4836 iflib_rx_structures_setup(if_ctx_t ctx) 4837 { 4838 iflib_rxq_t rxq = ctx->ifc_rxqs; 4839 int q; 4840 #if defined(INET6) || defined(INET) 4841 int i, err; 4842 #endif 4843 4844 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 4845 #if defined(INET6) || defined(INET) 4846 tcp_lro_free(&rxq->ifr_lc); 4847 if ((err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 4848 TCP_LRO_ENTRIES, min(1024, 4849 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset]))) != 0) { 4850 device_printf(ctx->ifc_dev, "LRO Initialization failed!\n"); 4851 goto fail; 4852 } 4853 rxq->ifr_lro_enabled = TRUE; 4854 #endif 4855 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 4856 } 4857 return (0); 4858 #if defined(INET6) || defined(INET) 4859 fail: 4860 /* 4861 * Free RX software descriptors allocated so far, we will only handle 4862 * the rings that completed, the failing case will have 4863 * cleaned up for itself. 'q' failed, so its the terminus. 4864 */ 4865 rxq = ctx->ifc_rxqs; 4866 for (i = 0; i < q; ++i, rxq++) { 4867 iflib_rx_sds_free(rxq); 4868 rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; 4869 } 4870 return (err); 4871 #endif 4872 } 4873 4874 /********************************************************************* 4875 * 4876 * Free all receive rings. 4877 * 4878 **********************************************************************/ 4879 static void 4880 iflib_rx_structures_free(if_ctx_t ctx) 4881 { 4882 iflib_rxq_t rxq = ctx->ifc_rxqs; 4883 4884 for (int i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 4885 iflib_rx_sds_free(rxq); 4886 } 4887 } 4888 4889 static int 4890 iflib_qset_structures_setup(if_ctx_t ctx) 4891 { 4892 int err; 4893 4894 if ((err = iflib_tx_structures_setup(ctx)) != 0) 4895 return (err); 4896 4897 if ((err = iflib_rx_structures_setup(ctx)) != 0) { 4898 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 4899 iflib_tx_structures_free(ctx); 4900 iflib_rx_structures_free(ctx); 4901 } 4902 return (err); 4903 } 4904 4905 int 4906 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 4907 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) 4908 { 4909 4910 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 4911 } 4912 4913 static int 4914 find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) 4915 { 4916 int i, cpuid, eqid, count; 4917 4918 CPU_COPY(&ctx->ifc_cpus, cpus); 4919 count = CPU_COUNT(&ctx->ifc_cpus); 4920 eqid = qid % count; 4921 /* clear up to the qid'th bit */ 4922 for (i = 0; i < eqid; i++) { 4923 cpuid = CPU_FFS(cpus); 4924 MPASS(cpuid != 0); 4925 CPU_CLR(cpuid-1, cpus); 4926 } 4927 cpuid = CPU_FFS(cpus); 4928 MPASS(cpuid != 0); 4929 return (cpuid-1); 4930 } 4931 4932 int 4933 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 4934 iflib_intr_type_t type, driver_filter_t *filter, 4935 void *filter_arg, int qid, char *name) 4936 { 4937 struct grouptask *gtask; 4938 struct taskqgroup *tqg; 4939 iflib_filter_info_t info; 4940 cpuset_t cpus; 4941 gtask_fn_t *fn; 4942 int tqrid, err, cpuid; 4943 driver_filter_t *intr_fast; 4944 void *q; 4945 4946 info = &ctx->ifc_filter_info; 4947 tqrid = rid; 4948 4949 switch (type) { 4950 /* XXX merge tx/rx for netmap? */ 4951 case IFLIB_INTR_TX: 4952 q = &ctx->ifc_txqs[qid]; 4953 info = &ctx->ifc_txqs[qid].ift_filter_info; 4954 gtask = &ctx->ifc_txqs[qid].ift_task; 4955 tqg = qgroup_if_io_tqg; 4956 fn = _task_fn_tx; 4957 intr_fast = iflib_fast_intr; 4958 GROUPTASK_INIT(gtask, 0, fn, q); 4959 break; 4960 case IFLIB_INTR_RX: 4961 q = &ctx->ifc_rxqs[qid]; 4962 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4963 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4964 tqg = qgroup_if_io_tqg; 4965 fn = _task_fn_rx; 4966 intr_fast = iflib_fast_intr; 4967 GROUPTASK_INIT(gtask, 0, fn, q); 4968 break; 4969 case IFLIB_INTR_RXTX: 4970 q = &ctx->ifc_rxqs[qid]; 4971 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 4972 gtask = &ctx->ifc_rxqs[qid].ifr_task; 4973 tqg = qgroup_if_io_tqg; 4974 fn = _task_fn_rx; 4975 intr_fast = iflib_fast_intr_rxtx; 4976 GROUPTASK_INIT(gtask, 0, fn, q); 4977 break; 4978 case IFLIB_INTR_ADMIN: 4979 q = ctx; 4980 tqrid = -1; 4981 info = &ctx->ifc_filter_info; 4982 gtask = &ctx->ifc_admin_task; 4983 tqg = qgroup_if_config_tqg; 4984 fn = _task_fn_admin; 4985 intr_fast = iflib_fast_intr_ctx; 4986 break; 4987 default: 4988 panic("unknown net intr type"); 4989 } 4990 4991 info->ifi_filter = filter; 4992 info->ifi_filter_arg = filter_arg; 4993 info->ifi_task = gtask; 4994 info->ifi_ctx = q; 4995 4996 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 4997 if (err != 0) { 4998 device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); 4999 return (err); 5000 } 5001 if (type == IFLIB_INTR_ADMIN) 5002 return (0); 5003 5004 if (tqrid != -1) { 5005 cpuid = find_nth(ctx, &cpus, qid); 5006 taskqgroup_attach_cpu(tqg, gtask, q, cpuid, rman_get_start(irq->ii_res), name); 5007 } else { 5008 taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); 5009 } 5010 5011 return (0); 5012 } 5013 5014 void 5015 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) 5016 { 5017 struct grouptask *gtask; 5018 struct taskqgroup *tqg; 5019 gtask_fn_t *fn; 5020 void *q; 5021 int irq_num = -1; 5022 5023 switch (type) { 5024 case IFLIB_INTR_TX: 5025 q = &ctx->ifc_txqs[qid]; 5026 gtask = &ctx->ifc_txqs[qid].ift_task; 5027 tqg = qgroup_if_io_tqg; 5028 fn = _task_fn_tx; 5029 if (irq != NULL) 5030 irq_num = rman_get_start(irq->ii_res); 5031 break; 5032 case IFLIB_INTR_RX: 5033 q = &ctx->ifc_rxqs[qid]; 5034 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5035 tqg = qgroup_if_io_tqg; 5036 fn = _task_fn_rx; 5037 if (irq != NULL) 5038 irq_num = rman_get_start(irq->ii_res); 5039 break; 5040 case IFLIB_INTR_IOV: 5041 q = ctx; 5042 gtask = &ctx->ifc_vflr_task; 5043 tqg = qgroup_if_config_tqg; 5044 fn = _task_fn_iov; 5045 break; 5046 default: 5047 panic("unknown net intr type"); 5048 } 5049 GROUPTASK_INIT(gtask, 0, fn, q); 5050 taskqgroup_attach(tqg, gtask, q, irq_num, name); 5051 } 5052 5053 void 5054 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 5055 { 5056 if (irq->ii_tag) 5057 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 5058 5059 if (irq->ii_res) 5060 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, irq->ii_rid, irq->ii_res); 5061 } 5062 5063 static int 5064 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) 5065 { 5066 iflib_txq_t txq = ctx->ifc_txqs; 5067 iflib_rxq_t rxq = ctx->ifc_rxqs; 5068 if_irq_t irq = &ctx->ifc_legacy_irq; 5069 iflib_filter_info_t info; 5070 struct grouptask *gtask; 5071 struct taskqgroup *tqg; 5072 gtask_fn_t *fn; 5073 int tqrid; 5074 void *q; 5075 int err; 5076 5077 q = &ctx->ifc_rxqs[0]; 5078 info = &rxq[0].ifr_filter_info; 5079 gtask = &rxq[0].ifr_task; 5080 tqg = qgroup_if_io_tqg; 5081 tqrid = irq->ii_rid = *rid; 5082 fn = _task_fn_rx; 5083 5084 ctx->ifc_flags |= IFC_LEGACY; 5085 info->ifi_filter = filter; 5086 info->ifi_filter_arg = filter_arg; 5087 info->ifi_task = gtask; 5088 info->ifi_ctx = ctx; 5089 5090 /* We allocate a single interrupt resource */ 5091 if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) 5092 return (err); 5093 GROUPTASK_INIT(gtask, 0, fn, q); 5094 taskqgroup_attach(tqg, gtask, q, tqrid, name); 5095 5096 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 5097 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, tqrid, "tx"); 5098 return (0); 5099 } 5100 5101 void 5102 iflib_led_create(if_ctx_t ctx) 5103 { 5104 5105 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 5106 device_get_nameunit(ctx->ifc_dev)); 5107 } 5108 5109 void 5110 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 5111 { 5112 5113 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 5114 } 5115 5116 void 5117 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 5118 { 5119 5120 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 5121 } 5122 5123 void 5124 iflib_admin_intr_deferred(if_ctx_t ctx) 5125 { 5126 #ifdef INVARIANTS 5127 struct grouptask *gtask; 5128 5129 gtask = &ctx->ifc_admin_task; 5130 MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); 5131 #endif 5132 5133 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 5134 } 5135 5136 void 5137 iflib_iov_intr_deferred(if_ctx_t ctx) 5138 { 5139 5140 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 5141 } 5142 5143 void 5144 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) 5145 { 5146 5147 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); 5148 } 5149 5150 void 5151 iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, 5152 char *name) 5153 { 5154 5155 GROUPTASK_INIT(gtask, 0, fn, ctx); 5156 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); 5157 } 5158 5159 void 5160 iflib_config_gtask_deinit(struct grouptask *gtask) 5161 { 5162 5163 taskqgroup_detach(qgroup_if_config_tqg, gtask); 5164 } 5165 5166 void 5167 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 5168 { 5169 if_t ifp = ctx->ifc_ifp; 5170 iflib_txq_t txq = ctx->ifc_txqs; 5171 5172 if_setbaudrate(ifp, baudrate); 5173 if (baudrate >= IF_Gbps(10)) 5174 ctx->ifc_flags |= IFC_PREFETCH; 5175 5176 /* If link down, disable watchdog */ 5177 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 5178 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 5179 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 5180 } 5181 ctx->ifc_link_state = link_state; 5182 if_link_state_change(ifp, link_state); 5183 } 5184 5185 static int 5186 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 5187 { 5188 int credits; 5189 #ifdef INVARIANTS 5190 int credits_pre = txq->ift_cidx_processed; 5191 #endif 5192 5193 if (ctx->isc_txd_credits_update == NULL) 5194 return (0); 5195 5196 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 5197 return (0); 5198 5199 txq->ift_processed += credits; 5200 txq->ift_cidx_processed += credits; 5201 5202 MPASS(credits_pre + credits == txq->ift_cidx_processed); 5203 if (txq->ift_cidx_processed >= txq->ift_size) 5204 txq->ift_cidx_processed -= txq->ift_size; 5205 return (credits); 5206 } 5207 5208 static int 5209 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 5210 { 5211 5212 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 5213 budget)); 5214 } 5215 5216 void 5217 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 5218 const char *description, if_int_delay_info_t info, 5219 int offset, int value) 5220 { 5221 info->iidi_ctx = ctx; 5222 info->iidi_offset = offset; 5223 info->iidi_value = value; 5224 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 5225 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 5226 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5227 info, 0, iflib_sysctl_int_delay, "I", description); 5228 } 5229 5230 struct mtx * 5231 iflib_ctx_lock_get(if_ctx_t ctx) 5232 { 5233 5234 return (&ctx->ifc_mtx); 5235 } 5236 5237 static int 5238 iflib_msix_init(if_ctx_t ctx) 5239 { 5240 device_t dev = ctx->ifc_dev; 5241 if_shared_ctx_t sctx = ctx->ifc_sctx; 5242 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5243 int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; 5244 int iflib_num_tx_queues, iflib_num_rx_queues; 5245 int err, admincnt, bar; 5246 5247 iflib_num_tx_queues = scctx->isc_ntxqsets; 5248 iflib_num_rx_queues = scctx->isc_nrxqsets; 5249 5250 device_printf(dev, "msix_init qsets capped at %d\n", iflib_num_tx_queues); 5251 5252 bar = ctx->ifc_softc_ctx.isc_msix_bar; 5253 admincnt = sctx->isc_admin_intrcnt; 5254 /* Override by global tuneable */ 5255 { 5256 int i; 5257 size_t len = sizeof(i); 5258 err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); 5259 if (err == 0) { 5260 if (i == 0) 5261 goto msi; 5262 } 5263 else { 5264 device_printf(dev, "unable to read hw.pci.enable_msix."); 5265 } 5266 } 5267 /* Override by tuneable */ 5268 if (scctx->isc_disable_msix) 5269 goto msi; 5270 5271 /* 5272 ** When used in a virtualized environment 5273 ** PCI BUSMASTER capability may not be set 5274 ** so explicity set it here and rewrite 5275 ** the ENABLE in the MSIX control register 5276 ** at this point to cause the host to 5277 ** successfully initialize us. 5278 */ 5279 { 5280 int msix_ctrl, rid; 5281 5282 pci_enable_busmaster(dev); 5283 rid = 0; 5284 if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { 5285 rid += PCIR_MSIX_CTRL; 5286 msix_ctrl = pci_read_config(dev, rid, 2); 5287 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 5288 pci_write_config(dev, rid, msix_ctrl, 2); 5289 } else { 5290 device_printf(dev, "PCIY_MSIX capability not found; " 5291 "or rid %d == 0.\n", rid); 5292 goto msi; 5293 } 5294 } 5295 5296 /* 5297 * bar == -1 => "trust me I know what I'm doing" 5298 * Some drivers are for hardware that is so shoddily 5299 * documented that no one knows which bars are which 5300 * so the developer has to map all bars. This hack 5301 * allows shoddy garbage to use msix in this framework. 5302 */ 5303 if (bar != -1) { 5304 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 5305 SYS_RES_MEMORY, &bar, RF_ACTIVE); 5306 if (ctx->ifc_msix_mem == NULL) { 5307 /* May not be enabled */ 5308 device_printf(dev, "Unable to map MSIX table \n"); 5309 goto msi; 5310 } 5311 } 5312 /* First try MSI/X */ 5313 if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ 5314 device_printf(dev, "System has MSIX disabled \n"); 5315 bus_release_resource(dev, SYS_RES_MEMORY, 5316 bar, ctx->ifc_msix_mem); 5317 ctx->ifc_msix_mem = NULL; 5318 goto msi; 5319 } 5320 #if IFLIB_DEBUG 5321 /* use only 1 qset in debug mode */ 5322 queuemsgs = min(msgs - admincnt, 1); 5323 #else 5324 queuemsgs = msgs - admincnt; 5325 #endif 5326 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { 5327 #ifdef RSS 5328 queues = imin(queuemsgs, rss_getnumbuckets()); 5329 #else 5330 queues = queuemsgs; 5331 #endif 5332 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 5333 device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", 5334 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 5335 } else { 5336 device_printf(dev, "Unable to fetch CPU list\n"); 5337 /* Figure out a reasonable auto config value */ 5338 queues = min(queuemsgs, mp_ncpus); 5339 } 5340 #ifdef RSS 5341 /* If we're doing RSS, clamp at the number of RSS buckets */ 5342 if (queues > rss_getnumbuckets()) 5343 queues = rss_getnumbuckets(); 5344 #endif 5345 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 5346 rx_queues = iflib_num_rx_queues; 5347 else 5348 rx_queues = queues; 5349 /* 5350 * We want this to be all logical CPUs by default 5351 */ 5352 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 5353 tx_queues = iflib_num_tx_queues; 5354 else 5355 tx_queues = mp_ncpus; 5356 5357 if (ctx->ifc_sysctl_qs_eq_override == 0) { 5358 #ifdef INVARIANTS 5359 if (tx_queues != rx_queues) 5360 device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 5361 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 5362 #endif 5363 tx_queues = min(rx_queues, tx_queues); 5364 rx_queues = min(rx_queues, tx_queues); 5365 } 5366 5367 device_printf(dev, "using %d rx queues %d tx queues \n", rx_queues, tx_queues); 5368 5369 vectors = rx_queues + admincnt; 5370 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 5371 device_printf(dev, 5372 "Using MSIX interrupts with %d vectors\n", vectors); 5373 scctx->isc_vectors = vectors; 5374 scctx->isc_nrxqsets = rx_queues; 5375 scctx->isc_ntxqsets = tx_queues; 5376 scctx->isc_intr = IFLIB_INTR_MSIX; 5377 5378 return (vectors); 5379 } else { 5380 device_printf(dev, "failed to allocate %d msix vectors, err: %d - using MSI\n", vectors, err); 5381 } 5382 msi: 5383 vectors = pci_msi_count(dev); 5384 scctx->isc_nrxqsets = 1; 5385 scctx->isc_ntxqsets = 1; 5386 scctx->isc_vectors = vectors; 5387 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 5388 device_printf(dev,"Using an MSI interrupt\n"); 5389 scctx->isc_intr = IFLIB_INTR_MSI; 5390 } else { 5391 device_printf(dev,"Using a Legacy interrupt\n"); 5392 scctx->isc_intr = IFLIB_INTR_LEGACY; 5393 } 5394 5395 return (vectors); 5396 } 5397 5398 char * ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 5399 5400 static int 5401 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 5402 { 5403 int rc; 5404 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 5405 struct sbuf *sb; 5406 char *ring_state = "UNKNOWN"; 5407 5408 /* XXX needed ? */ 5409 rc = sysctl_wire_old_buffer(req, 0); 5410 MPASS(rc == 0); 5411 if (rc != 0) 5412 return (rc); 5413 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 5414 MPASS(sb != NULL); 5415 if (sb == NULL) 5416 return (ENOMEM); 5417 if (state[3] <= 3) 5418 ring_state = ring_states[state[3]]; 5419 5420 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 5421 state[0], state[1], state[2], ring_state); 5422 rc = sbuf_finish(sb); 5423 sbuf_delete(sb); 5424 return(rc); 5425 } 5426 5427 enum iflib_ndesc_handler { 5428 IFLIB_NTXD_HANDLER, 5429 IFLIB_NRXD_HANDLER, 5430 }; 5431 5432 static int 5433 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 5434 { 5435 if_ctx_t ctx = (void *)arg1; 5436 enum iflib_ndesc_handler type = arg2; 5437 char buf[256] = {0}; 5438 qidx_t *ndesc; 5439 char *p, *next; 5440 int nqs, rc, i; 5441 5442 MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); 5443 5444 nqs = 8; 5445 switch(type) { 5446 case IFLIB_NTXD_HANDLER: 5447 ndesc = ctx->ifc_sysctl_ntxds; 5448 if (ctx->ifc_sctx) 5449 nqs = ctx->ifc_sctx->isc_ntxqs; 5450 break; 5451 case IFLIB_NRXD_HANDLER: 5452 ndesc = ctx->ifc_sysctl_nrxds; 5453 if (ctx->ifc_sctx) 5454 nqs = ctx->ifc_sctx->isc_nrxqs; 5455 break; 5456 } 5457 if (nqs == 0) 5458 nqs = 8; 5459 5460 for (i=0; i<8; i++) { 5461 if (i >= nqs) 5462 break; 5463 if (i) 5464 strcat(buf, ","); 5465 sprintf(strchr(buf, 0), "%d", ndesc[i]); 5466 } 5467 5468 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 5469 if (rc || req->newptr == NULL) 5470 return rc; 5471 5472 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 5473 i++, p = strsep(&next, " ,")) { 5474 ndesc[i] = strtoul(p, NULL, 10); 5475 } 5476 5477 return(rc); 5478 } 5479 5480 #define NAME_BUFLEN 32 5481 static void 5482 iflib_add_device_sysctl_pre(if_ctx_t ctx) 5483 { 5484 device_t dev = iflib_get_dev(ctx); 5485 struct sysctl_oid_list *child, *oid_list; 5486 struct sysctl_ctx_list *ctx_list; 5487 struct sysctl_oid *node; 5488 5489 ctx_list = device_get_sysctl_ctx(dev); 5490 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 5491 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 5492 CTLFLAG_RD, NULL, "IFLIB fields"); 5493 oid_list = SYSCTL_CHILDREN(node); 5494 5495 SYSCTL_ADD_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 5496 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 0, 5497 "driver version"); 5498 5499 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 5500 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 5501 "# of txqs to use, 0 => use default #"); 5502 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 5503 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 5504 "# of rxqs to use, 0 => use default #"); 5505 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 5506 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 5507 "permit #txq != #rxq"); 5508 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 5509 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 5510 "disable MSIX (default 0)"); 5511 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 5512 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 5513 "set the rx budget"); 5514 5515 /* XXX change for per-queue sizes */ 5516 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 5517 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, 5518 mp_ndesc_handler, "A", 5519 "list of # of tx descriptors to use, 0 = use default #"); 5520 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 5521 CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, 5522 mp_ndesc_handler, "A", 5523 "list of # of rx descriptors to use, 0 = use default #"); 5524 } 5525 5526 static void 5527 iflib_add_device_sysctl_post(if_ctx_t ctx) 5528 { 5529 if_shared_ctx_t sctx = ctx->ifc_sctx; 5530 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5531 device_t dev = iflib_get_dev(ctx); 5532 struct sysctl_oid_list *child; 5533 struct sysctl_ctx_list *ctx_list; 5534 iflib_fl_t fl; 5535 iflib_txq_t txq; 5536 iflib_rxq_t rxq; 5537 int i, j; 5538 char namebuf[NAME_BUFLEN]; 5539 char *qfmt; 5540 struct sysctl_oid *queue_node, *fl_node, *node; 5541 struct sysctl_oid_list *queue_list, *fl_list; 5542 ctx_list = device_get_sysctl_ctx(dev); 5543 5544 node = ctx->ifc_sysctl_node; 5545 child = SYSCTL_CHILDREN(node); 5546 5547 if (scctx->isc_ntxqsets > 100) 5548 qfmt = "txq%03d"; 5549 else if (scctx->isc_ntxqsets > 10) 5550 qfmt = "txq%02d"; 5551 else 5552 qfmt = "txq%d"; 5553 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 5554 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5555 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5556 CTLFLAG_RD, NULL, "Queue Name"); 5557 queue_list = SYSCTL_CHILDREN(queue_node); 5558 #if MEMORY_LOGGING 5559 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 5560 CTLFLAG_RD, 5561 &txq->ift_dequeued, "total mbufs freed"); 5562 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 5563 CTLFLAG_RD, 5564 &txq->ift_enqueued, "total mbufs enqueued"); 5565 #endif 5566 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 5567 CTLFLAG_RD, 5568 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 5569 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 5570 CTLFLAG_RD, 5571 &txq->ift_pullups, "# of times m_pullup was called"); 5572 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 5573 CTLFLAG_RD, 5574 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 5575 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 5576 CTLFLAG_RD, 5577 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 5578 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 5579 CTLFLAG_RD, 5580 &txq->ift_map_failed, "# of times dma map failed"); 5581 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 5582 CTLFLAG_RD, 5583 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 5584 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 5585 CTLFLAG_RD, 5586 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 5587 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 5588 CTLFLAG_RD, 5589 &txq->ift_pidx, 1, "Producer Index"); 5590 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 5591 CTLFLAG_RD, 5592 &txq->ift_cidx, 1, "Consumer Index"); 5593 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 5594 CTLFLAG_RD, 5595 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 5596 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 5597 CTLFLAG_RD, 5598 &txq->ift_in_use, 1, "descriptors in use"); 5599 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 5600 CTLFLAG_RD, 5601 &txq->ift_processed, "descriptors procesed for clean"); 5602 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 5603 CTLFLAG_RD, 5604 &txq->ift_cleaned, "total cleaned"); 5605 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 5606 CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), 5607 0, mp_ring_state_handler, "A", "soft ring state"); 5608 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 5609 CTLFLAG_RD, &txq->ift_br->enqueues, 5610 "# of enqueues to the mp_ring for this queue"); 5611 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 5612 CTLFLAG_RD, &txq->ift_br->drops, 5613 "# of drops in the mp_ring for this queue"); 5614 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 5615 CTLFLAG_RD, &txq->ift_br->starts, 5616 "# of normal consumer starts in the mp_ring for this queue"); 5617 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 5618 CTLFLAG_RD, &txq->ift_br->stalls, 5619 "# of consumer stalls in the mp_ring for this queue"); 5620 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 5621 CTLFLAG_RD, &txq->ift_br->restarts, 5622 "# of consumer restarts in the mp_ring for this queue"); 5623 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 5624 CTLFLAG_RD, &txq->ift_br->abdications, 5625 "# of consumer abdications in the mp_ring for this queue"); 5626 } 5627 5628 if (scctx->isc_nrxqsets > 100) 5629 qfmt = "rxq%03d"; 5630 else if (scctx->isc_nrxqsets > 10) 5631 qfmt = "rxq%02d"; 5632 else 5633 qfmt = "rxq%d"; 5634 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 5635 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 5636 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 5637 CTLFLAG_RD, NULL, "Queue Name"); 5638 queue_list = SYSCTL_CHILDREN(queue_node); 5639 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5640 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", 5641 CTLFLAG_RD, 5642 &rxq->ifr_cq_pidx, 1, "Producer Index"); 5643 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 5644 CTLFLAG_RD, 5645 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 5646 } 5647 5648 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 5649 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 5650 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 5651 CTLFLAG_RD, NULL, "freelist Name"); 5652 fl_list = SYSCTL_CHILDREN(fl_node); 5653 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 5654 CTLFLAG_RD, 5655 &fl->ifl_pidx, 1, "Producer Index"); 5656 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 5657 CTLFLAG_RD, 5658 &fl->ifl_cidx, 1, "Consumer Index"); 5659 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 5660 CTLFLAG_RD, 5661 &fl->ifl_credits, 1, "credits available"); 5662 #if MEMORY_LOGGING 5663 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 5664 CTLFLAG_RD, 5665 &fl->ifl_m_enqueued, "mbufs allocated"); 5666 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 5667 CTLFLAG_RD, 5668 &fl->ifl_m_dequeued, "mbufs freed"); 5669 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 5670 CTLFLAG_RD, 5671 &fl->ifl_cl_enqueued, "clusters allocated"); 5672 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 5673 CTLFLAG_RD, 5674 &fl->ifl_cl_dequeued, "clusters freed"); 5675 #endif 5676 5677 } 5678 } 5679 5680 } 5681 5682 #ifndef __NO_STRICT_ALIGNMENT 5683 static struct mbuf * 5684 iflib_fixup_rx(struct mbuf *m) 5685 { 5686 struct mbuf *n; 5687 5688 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 5689 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 5690 m->m_data += ETHER_HDR_LEN; 5691 n = m; 5692 } else { 5693 MGETHDR(n, M_NOWAIT, MT_DATA); 5694 if (n == NULL) { 5695 m_freem(m); 5696 return (NULL); 5697 } 5698 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 5699 m->m_data += ETHER_HDR_LEN; 5700 m->m_len -= ETHER_HDR_LEN; 5701 n->m_len = ETHER_HDR_LEN; 5702 M_MOVE_PKTHDR(n, m); 5703 n->m_next = m; 5704 } 5705 return (n); 5706 } 5707 #endif 5708