1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 /* 120 * File organization: 121 * - private structures 122 * - iflib private utility functions 123 * - ifnet functions 124 * - vlan registry and other exported functions 125 * - iflib public core functions 126 * 127 * 128 */ 129 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 130 131 #define IFLIB_RXEOF_MORE (1U << 0) 132 #define IFLIB_RXEOF_EMPTY (2U << 0) 133 134 struct iflib_txq; 135 typedef struct iflib_txq *iflib_txq_t; 136 struct iflib_rxq; 137 typedef struct iflib_rxq *iflib_rxq_t; 138 struct iflib_fl; 139 typedef struct iflib_fl *iflib_fl_t; 140 141 struct iflib_ctx; 142 143 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 144 static void iflib_timer(void *arg); 145 static void iflib_tqg_detach(if_ctx_t ctx); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 uint8_t ifc_sysctl_use_logical_cores; 199 bool ifc_cpus_are_physical_cores; 200 201 qidx_t ifc_sysctl_ntxds[8]; 202 qidx_t ifc_sysctl_nrxds[8]; 203 struct if_txrx ifc_txrx; 204 #define isc_txd_encap ifc_txrx.ift_txd_encap 205 #define isc_txd_flush ifc_txrx.ift_txd_flush 206 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 207 #define isc_rxd_available ifc_txrx.ift_rxd_available 208 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 #ifdef DEV_NETMAP 353 struct callout ift_netmap_timer; 354 #endif /* DEV_NETMAP */ 355 356 if_txsd_vec_t ift_sds; 357 uint8_t ift_qstatus; 358 uint8_t ift_closed; 359 uint8_t ift_update_freq; 360 struct iflib_filter_info ift_filter_info; 361 bus_dma_tag_t ift_buf_tag; 362 bus_dma_tag_t ift_tso_buf_tag; 363 iflib_dma_info_t ift_ifdi; 364 #define MTX_NAME_LEN 32 365 char ift_mtx_name[MTX_NAME_LEN]; 366 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 367 #ifdef IFLIB_DIAGNOSTICS 368 uint64_t ift_cpu_exec_count[256]; 369 #endif 370 } __aligned(CACHE_LINE_SIZE); 371 372 struct iflib_fl { 373 qidx_t ifl_cidx; 374 qidx_t ifl_pidx; 375 qidx_t ifl_credits; 376 uint8_t ifl_gen; 377 uint8_t ifl_rxd_size; 378 #if MEMORY_LOGGING 379 uint64_t ifl_m_enqueued; 380 uint64_t ifl_m_dequeued; 381 uint64_t ifl_cl_enqueued; 382 uint64_t ifl_cl_dequeued; 383 #endif 384 /* implicit pad */ 385 bitstr_t *ifl_rx_bitmap; 386 qidx_t ifl_fragidx; 387 /* constant */ 388 qidx_t ifl_size; 389 uint16_t ifl_buf_size; 390 uint16_t ifl_cltype; 391 uma_zone_t ifl_zone; 392 iflib_rxsd_array_t ifl_sds; 393 iflib_rxq_t ifl_rxq; 394 uint8_t ifl_id; 395 bus_dma_tag_t ifl_buf_tag; 396 iflib_dma_info_t ifl_ifdi; 397 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 398 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 399 } __aligned(CACHE_LINE_SIZE); 400 401 static inline qidx_t 402 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 403 { 404 qidx_t used; 405 406 if (pidx > cidx) 407 used = pidx - cidx; 408 else if (pidx < cidx) 409 used = size - cidx + pidx; 410 else if (gen == 0 && pidx == cidx) 411 used = 0; 412 else if (gen == 1 && pidx == cidx) 413 used = size; 414 else 415 panic("bad state"); 416 417 return (used); 418 } 419 420 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 421 422 #define IDXDIFF(head, tail, wrap) \ 423 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 424 425 struct iflib_rxq { 426 if_ctx_t ifr_ctx; 427 iflib_fl_t ifr_fl; 428 uint64_t ifr_rx_irq; 429 struct pfil_head *pfil; 430 /* 431 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 432 * the completion queue consumer index. Otherwise it's unused. 433 */ 434 qidx_t ifr_cq_cidx; 435 uint16_t ifr_id; 436 uint8_t ifr_nfl; 437 uint8_t ifr_ntxqirq; 438 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 439 uint8_t ifr_fl_offset; 440 struct lro_ctrl ifr_lc; 441 struct grouptask ifr_task; 442 struct callout ifr_watchdog; 443 struct iflib_filter_info ifr_filter_info; 444 iflib_dma_info_t ifr_ifdi; 445 446 /* dynamically allocate if any drivers need a value substantially larger than this */ 447 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 448 #ifdef IFLIB_DIAGNOSTICS 449 uint64_t ifr_cpu_exec_count[256]; 450 #endif 451 } __aligned(CACHE_LINE_SIZE); 452 453 typedef struct if_rxsd { 454 caddr_t *ifsd_cl; 455 iflib_fl_t ifsd_fl; 456 } *if_rxsd_t; 457 458 /* multiple of word size */ 459 #ifdef __LP64__ 460 #define PKT_INFO_SIZE 6 461 #define RXD_INFO_SIZE 5 462 #define PKT_TYPE uint64_t 463 #else 464 #define PKT_INFO_SIZE 11 465 #define RXD_INFO_SIZE 8 466 #define PKT_TYPE uint32_t 467 #endif 468 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 469 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 470 471 typedef struct if_pkt_info_pad { 472 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 473 } *if_pkt_info_pad_t; 474 typedef struct if_rxd_info_pad { 475 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 476 } *if_rxd_info_pad_t; 477 478 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 479 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 480 481 static inline void 482 pkt_info_zero(if_pkt_info_t pi) 483 { 484 if_pkt_info_pad_t pi_pad; 485 486 pi_pad = (if_pkt_info_pad_t)pi; 487 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 488 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 489 #ifndef __LP64__ 490 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 491 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 492 #endif 493 } 494 495 static device_method_t iflib_pseudo_methods[] = { 496 DEVMETHOD(device_attach, noop_attach), 497 DEVMETHOD(device_detach, iflib_pseudo_detach), 498 DEVMETHOD_END 499 }; 500 501 driver_t iflib_pseudodriver = { 502 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 503 }; 504 505 static inline void 506 rxd_info_zero(if_rxd_info_t ri) 507 { 508 if_rxd_info_pad_t ri_pad; 509 int i; 510 511 ri_pad = (if_rxd_info_pad_t)ri; 512 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 513 ri_pad->rxd_val[i] = 0; 514 ri_pad->rxd_val[i+1] = 0; 515 ri_pad->rxd_val[i+2] = 0; 516 ri_pad->rxd_val[i+3] = 0; 517 } 518 #ifdef __LP64__ 519 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 520 #endif 521 } 522 523 /* 524 * Only allow a single packet to take up most 1/nth of the tx ring 525 */ 526 #define MAX_SINGLE_PACKET_FRACTION 12 527 #define IF_BAD_DMA (bus_addr_t)-1 528 529 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 530 531 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 532 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 534 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 535 536 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 537 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 538 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 539 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 540 541 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 542 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 543 544 void 545 iflib_set_detach(if_ctx_t ctx) 546 { 547 STATE_LOCK(ctx); 548 ctx->ifc_flags |= IFC_IN_DETACH; 549 STATE_UNLOCK(ctx); 550 } 551 552 /* Our boot-time initialization hook */ 553 static int iflib_module_event_handler(module_t, int, void *); 554 555 static moduledata_t iflib_moduledata = { 556 "iflib", 557 iflib_module_event_handler, 558 NULL 559 }; 560 561 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 562 MODULE_VERSION(iflib, 1); 563 564 MODULE_DEPEND(iflib, pci, 1, 1, 1); 565 MODULE_DEPEND(iflib, ether, 1, 1, 1); 566 567 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 568 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 569 570 #ifndef IFLIB_DEBUG_COUNTERS 571 #ifdef INVARIANTS 572 #define IFLIB_DEBUG_COUNTERS 1 573 #else 574 #define IFLIB_DEBUG_COUNTERS 0 575 #endif /* !INVARIANTS */ 576 #endif 577 578 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 579 "iflib driver parameters"); 580 581 /* 582 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 583 */ 584 static int iflib_min_tx_latency = 0; 585 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 586 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 587 static int iflib_no_tx_batch = 0; 588 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 589 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 590 static int iflib_timer_default = 1000; 591 SYSCTL_INT(_net_iflib, OID_AUTO, timer_default, CTLFLAG_RW, 592 &iflib_timer_default, 0, "number of ticks between iflib_timer calls"); 593 594 595 #if IFLIB_DEBUG_COUNTERS 596 597 static int iflib_tx_seen; 598 static int iflib_tx_sent; 599 static int iflib_tx_encap; 600 static int iflib_rx_allocs; 601 static int iflib_fl_refills; 602 static int iflib_fl_refills_large; 603 static int iflib_tx_frees; 604 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 606 &iflib_tx_seen, 0, "# TX mbufs seen"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 608 &iflib_tx_sent, 0, "# TX mbufs sent"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 610 &iflib_tx_encap, 0, "# TX mbufs encapped"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 612 &iflib_tx_frees, 0, "# TX frees"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 614 &iflib_rx_allocs, 0, "# RX allocations"); 615 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 616 &iflib_fl_refills, 0, "# refills"); 617 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 618 &iflib_fl_refills_large, 0, "# large refills"); 619 620 static int iflib_txq_drain_flushing; 621 static int iflib_txq_drain_oactive; 622 static int iflib_txq_drain_notready; 623 624 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 625 &iflib_txq_drain_flushing, 0, "# drain flushes"); 626 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 627 &iflib_txq_drain_oactive, 0, "# drain oactives"); 628 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 629 &iflib_txq_drain_notready, 0, "# drain notready"); 630 631 static int iflib_encap_load_mbuf_fail; 632 static int iflib_encap_pad_mbuf_fail; 633 static int iflib_encap_txq_avail_fail; 634 static int iflib_encap_txd_encap_fail; 635 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 639 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 641 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 642 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 643 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 644 645 static int iflib_task_fn_rxs; 646 static int iflib_rx_intr_enables; 647 static int iflib_fast_intrs; 648 static int iflib_rx_unavail; 649 static int iflib_rx_ctx_inactive; 650 static int iflib_rx_if_input; 651 static int iflib_rxd_flush; 652 653 static int iflib_verbose_debug; 654 655 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 656 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 658 &iflib_rx_intr_enables, 0, "# RX intr enables"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 660 &iflib_fast_intrs, 0, "# fast_intr calls"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 662 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 664 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 666 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 668 &iflib_rxd_flush, 0, "# times rxd_flush called"); 669 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 670 &iflib_verbose_debug, 0, "enable verbose debugging"); 671 672 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 673 static void 674 iflib_debug_reset(void) 675 { 676 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 677 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 678 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 679 iflib_txq_drain_notready = 680 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 681 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 682 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 683 iflib_rx_unavail = 684 iflib_rx_ctx_inactive = iflib_rx_if_input = 685 iflib_rxd_flush = 0; 686 } 687 688 #else 689 #define DBG_COUNTER_INC(name) 690 static void iflib_debug_reset(void) {} 691 #endif 692 693 #define IFLIB_DEBUG 0 694 695 static void iflib_tx_structures_free(if_ctx_t ctx); 696 static void iflib_rx_structures_free(if_ctx_t ctx); 697 static int iflib_queues_alloc(if_ctx_t ctx); 698 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 699 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 700 static int iflib_qset_structures_setup(if_ctx_t ctx); 701 static int iflib_msix_init(if_ctx_t ctx); 702 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 703 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 704 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 705 #ifdef ALTQ 706 static void iflib_altq_if_start(if_t ifp); 707 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 708 #endif 709 static int iflib_register(if_ctx_t); 710 static void iflib_deregister(if_ctx_t); 711 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 712 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 713 static void iflib_init_locked(if_ctx_t ctx); 714 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 715 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 716 static void iflib_ifmp_purge(iflib_txq_t txq); 717 static void _iflib_pre_assert(if_softc_ctx_t scctx); 718 static void iflib_if_init_locked(if_ctx_t ctx); 719 static void iflib_free_intr_mem(if_ctx_t ctx); 720 #ifndef __NO_STRICT_ALIGNMENT 721 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 722 #endif 723 724 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 725 SLIST_HEAD_INITIALIZER(cpu_offsets); 726 struct cpu_offset { 727 SLIST_ENTRY(cpu_offset) entries; 728 cpuset_t set; 729 unsigned int refcount; 730 uint16_t next_cpuid; 731 }; 732 static struct mtx cpu_offset_mtx; 733 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 734 MTX_DEF); 735 736 DEBUGNET_DEFINE(iflib); 737 738 static int 739 iflib_num_rx_descs(if_ctx_t ctx) 740 { 741 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 742 if_shared_ctx_t sctx = ctx->ifc_sctx; 743 uint16_t first_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 744 745 return scctx->isc_nrxd[first_rxq]; 746 } 747 748 static int 749 iflib_num_tx_descs(if_ctx_t ctx) 750 { 751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 752 if_shared_ctx_t sctx = ctx->ifc_sctx; 753 uint16_t first_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 754 755 return scctx->isc_ntxd[first_txq]; 756 } 757 758 #ifdef DEV_NETMAP 759 #include <sys/selinfo.h> 760 #include <net/netmap.h> 761 #include <dev/netmap/netmap_kern.h> 762 763 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 764 765 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init); 766 static void iflib_netmap_timer(void *arg); 767 768 /* 769 * device-specific sysctl variables: 770 * 771 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 772 * During regular operations the CRC is stripped, but on some 773 * hardware reception of frames not multiple of 64 is slower, 774 * so using crcstrip=0 helps in benchmarks. 775 * 776 * iflib_rx_miss, iflib_rx_miss_bufs: 777 * count packets that might be missed due to lost interrupts. 778 */ 779 SYSCTL_DECL(_dev_netmap); 780 /* 781 * The xl driver by default strips CRCs and we do not override it. 782 */ 783 784 int iflib_crcstrip = 1; 785 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 786 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 787 788 int iflib_rx_miss, iflib_rx_miss_bufs; 789 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 790 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 791 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 792 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 793 794 /* 795 * Register/unregister. We are already under netmap lock. 796 * Only called on the first register or the last unregister. 797 */ 798 static int 799 iflib_netmap_register(struct netmap_adapter *na, int onoff) 800 { 801 if_t ifp = na->ifp; 802 if_ctx_t ctx = ifp->if_softc; 803 int status; 804 805 CTX_LOCK(ctx); 806 if (!CTX_IS_VF(ctx)) 807 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 808 809 iflib_stop(ctx); 810 811 /* 812 * Enable (or disable) netmap flags, and intercept (or restore) 813 * ifp->if_transmit. This is done once the device has been stopped 814 * to prevent race conditions. Also, this must be done after 815 * calling netmap_disable_all_rings() and before calling 816 * netmap_enable_all_rings(), so that these two functions see the 817 * updated state of the NAF_NETMAP_ON bit. 818 */ 819 if (onoff) { 820 nm_set_native_flags(na); 821 } else { 822 nm_clear_native_flags(na); 823 } 824 825 iflib_init_locked(ctx); 826 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 827 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 828 if (status) 829 nm_clear_native_flags(na); 830 CTX_UNLOCK(ctx); 831 return (status); 832 } 833 834 static int 835 iflib_netmap_config(struct netmap_adapter *na, struct nm_config_info *info) 836 { 837 if_t ifp = na->ifp; 838 if_ctx_t ctx = ifp->if_softc; 839 iflib_rxq_t rxq = &ctx->ifc_rxqs[0]; 840 iflib_fl_t fl = &rxq->ifr_fl[0]; 841 842 info->num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 843 info->num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 844 info->num_tx_descs = iflib_num_tx_descs(ctx); 845 info->num_rx_descs = iflib_num_rx_descs(ctx); 846 info->rx_buf_maxsize = fl->ifl_buf_size; 847 nm_prinf("txr %u rxr %u txd %u rxd %u rbufsz %u", 848 info->num_tx_rings, info->num_rx_rings, info->num_tx_descs, 849 info->num_rx_descs, info->rx_buf_maxsize); 850 851 return 0; 852 } 853 854 static int 855 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, bool init) 856 { 857 struct netmap_adapter *na = kring->na; 858 u_int const lim = kring->nkr_num_slots - 1; 859 struct netmap_ring *ring = kring->ring; 860 bus_dmamap_t *map; 861 struct if_rxd_update iru; 862 if_ctx_t ctx = rxq->ifr_ctx; 863 iflib_fl_t fl = &rxq->ifr_fl[0]; 864 u_int nic_i_first, nic_i; 865 u_int nm_i; 866 int i, n; 867 #if IFLIB_DEBUG_COUNTERS 868 int rf_count = 0; 869 #endif 870 871 /* 872 * This function is used both at initialization and in rxsync. 873 * At initialization we need to prepare (with isc_rxd_refill()) 874 * all the netmap buffers currently owned by the kernel, in 875 * such a way to keep fl->ifl_pidx and kring->nr_hwcur in sync 876 * (except for kring->nkr_hwofs). These may be less than 877 * kring->nkr_num_slots if netmap_reset() was called while 878 * an application using the kring that still owned some 879 * buffers. 880 * At rxsync time, both indexes point to the next buffer to be 881 * refilled. 882 * In any case we publish (with isc_rxd_flush()) up to 883 * (fl->ifl_pidx - 1) % N (included), to avoid the NIC tail/prod 884 * pointer to overrun the head/cons pointer, although this is 885 * not necessary for some NICs (e.g. vmx). 886 */ 887 if (__predict_false(init)) { 888 n = kring->nkr_num_slots - nm_kr_rxspace(kring); 889 } else { 890 n = kring->rhead - kring->nr_hwcur; 891 if (n == 0) 892 return (0); /* Nothing to do. */ 893 if (n < 0) 894 n += kring->nkr_num_slots; 895 } 896 897 iru_init(&iru, rxq, 0 /* flid */); 898 map = fl->ifl_sds.ifsd_map; 899 nic_i = fl->ifl_pidx; 900 nm_i = netmap_idx_n2k(kring, nic_i); 901 if (__predict_false(init)) { 902 /* 903 * On init/reset, nic_i must be 0, and we must 904 * start to refill from hwtail (see netmap_reset()). 905 */ 906 MPASS(nic_i == 0); 907 MPASS(nm_i == kring->nr_hwtail); 908 } else 909 MPASS(nm_i == kring->nr_hwcur); 910 DBG_COUNTER_INC(fl_refills); 911 while (n > 0) { 912 #if IFLIB_DEBUG_COUNTERS 913 if (++rf_count == 9) 914 DBG_COUNTER_INC(fl_refills_large); 915 #endif 916 nic_i_first = nic_i; 917 for (i = 0; n > 0 && i < IFLIB_MAX_RX_REFRESH; n--, i++) { 918 struct netmap_slot *slot = &ring->slot[nm_i]; 919 uint64_t paddr; 920 void *addr = PNMB(na, slot, &paddr); 921 922 MPASS(i < IFLIB_MAX_RX_REFRESH); 923 924 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 925 return netmap_ring_reinit(kring); 926 927 fl->ifl_bus_addrs[i] = paddr + 928 nm_get_offset(kring, slot); 929 fl->ifl_rxd_idxs[i] = nic_i; 930 931 if (__predict_false(init)) { 932 netmap_load_map(na, fl->ifl_buf_tag, 933 map[nic_i], addr); 934 } else if (slot->flags & NS_BUF_CHANGED) { 935 /* buffer has changed, reload map */ 936 netmap_reload_map(na, fl->ifl_buf_tag, 937 map[nic_i], addr); 938 } 939 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i], 940 BUS_DMASYNC_PREREAD); 941 slot->flags &= ~NS_BUF_CHANGED; 942 943 nm_i = nm_next(nm_i, lim); 944 nic_i = nm_next(nic_i, lim); 945 } 946 947 iru.iru_pidx = nic_i_first; 948 iru.iru_count = i; 949 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 950 } 951 fl->ifl_pidx = nic_i; 952 /* 953 * At the end of the loop we must have refilled everything 954 * we could possibly refill. 955 */ 956 MPASS(nm_i == kring->rhead); 957 kring->nr_hwcur = nm_i; 958 959 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 961 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, 962 nm_prev(nic_i, lim)); 963 DBG_COUNTER_INC(rxd_flush); 964 965 return (0); 966 } 967 968 #define NETMAP_TX_TIMER_US 90 969 970 /* 971 * Reconcile kernel and user view of the transmit ring. 972 * 973 * All information is in the kring. 974 * Userspace wants to send packets up to the one before kring->rhead, 975 * kernel knows kring->nr_hwcur is the first unsent packet. 976 * 977 * Here we push packets out (as many as possible), and possibly 978 * reclaim buffers from previously completed transmission. 979 * 980 * The caller (netmap) guarantees that there is only one instance 981 * running at any time. Any interference with other driver 982 * methods should be handled by the individual drivers. 983 */ 984 static int 985 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 986 { 987 struct netmap_adapter *na = kring->na; 988 if_t ifp = na->ifp; 989 struct netmap_ring *ring = kring->ring; 990 u_int nm_i; /* index into the netmap kring */ 991 u_int nic_i; /* index into the NIC ring */ 992 u_int n; 993 u_int const lim = kring->nkr_num_slots - 1; 994 u_int const head = kring->rhead; 995 struct if_pkt_info pi; 996 int tx_pkts = 0, tx_bytes = 0; 997 998 /* 999 * interrupts on every tx packet are expensive so request 1000 * them every half ring, or where NS_REPORT is set 1001 */ 1002 u_int report_frequency = kring->nkr_num_slots >> 1; 1003 /* device-specific */ 1004 if_ctx_t ctx = ifp->if_softc; 1005 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 1006 1007 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1008 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1009 1010 /* 1011 * First part: process new packets to send. 1012 * nm_i is the current index in the netmap kring, 1013 * nic_i is the corresponding index in the NIC ring. 1014 * 1015 * If we have packets to send (nm_i != head) 1016 * iterate over the netmap ring, fetch length and update 1017 * the corresponding slot in the NIC ring. Some drivers also 1018 * need to update the buffer's physical address in the NIC slot 1019 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 1020 * 1021 * The netmap_reload_map() calls is especially expensive, 1022 * even when (as in this case) the tag is 0, so do only 1023 * when the buffer has actually changed. 1024 * 1025 * If possible do not set the report/intr bit on all slots, 1026 * but only a few times per ring or when NS_REPORT is set. 1027 * 1028 * Finally, on 10G and faster drivers, it might be useful 1029 * to prefetch the next slot and txr entry. 1030 */ 1031 1032 nm_i = kring->nr_hwcur; 1033 if (nm_i != head) { /* we have new packets to send */ 1034 uint32_t pkt_len = 0, seg_idx = 0; 1035 int nic_i_start = -1, flags = 0; 1036 pkt_info_zero(&pi); 1037 pi.ipi_segs = txq->ift_segs; 1038 pi.ipi_qsidx = kring->ring_id; 1039 nic_i = netmap_idx_k2n(kring, nm_i); 1040 1041 __builtin_prefetch(&ring->slot[nm_i]); 1042 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 1043 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 1044 1045 for (n = 0; nm_i != head; n++) { 1046 struct netmap_slot *slot = &ring->slot[nm_i]; 1047 uint64_t offset = nm_get_offset(kring, slot); 1048 u_int len = slot->len; 1049 uint64_t paddr; 1050 void *addr = PNMB(na, slot, &paddr); 1051 1052 flags |= (slot->flags & NS_REPORT || 1053 nic_i == 0 || nic_i == report_frequency) ? 1054 IPI_TX_INTR : 0; 1055 1056 /* 1057 * If this is the first packet fragment, save the 1058 * index of the first NIC slot for later. 1059 */ 1060 if (nic_i_start < 0) 1061 nic_i_start = nic_i; 1062 1063 pi.ipi_segs[seg_idx].ds_addr = paddr + offset; 1064 pi.ipi_segs[seg_idx].ds_len = len; 1065 if (len) { 1066 pkt_len += len; 1067 seg_idx++; 1068 } 1069 1070 if (!(slot->flags & NS_MOREFRAG)) { 1071 pi.ipi_len = pkt_len; 1072 pi.ipi_nsegs = seg_idx; 1073 pi.ipi_pidx = nic_i_start; 1074 pi.ipi_ndescs = 0; 1075 pi.ipi_flags = flags; 1076 1077 /* Prepare the NIC TX ring. */ 1078 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 1079 DBG_COUNTER_INC(tx_encap); 1080 1081 /* Update transmit counters */ 1082 tx_bytes += pi.ipi_len; 1083 tx_pkts++; 1084 1085 /* Reinit per-packet info for the next one. */ 1086 flags = seg_idx = pkt_len = 0; 1087 nic_i_start = -1; 1088 } 1089 1090 /* prefetch for next round */ 1091 __builtin_prefetch(&ring->slot[nm_i + 1]); 1092 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 1093 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 1094 1095 NM_CHECK_ADDR_LEN_OFF(na, len, offset); 1096 1097 if (slot->flags & NS_BUF_CHANGED) { 1098 /* buffer has changed, reload map */ 1099 netmap_reload_map(na, txq->ift_buf_tag, 1100 txq->ift_sds.ifsd_map[nic_i], addr); 1101 } 1102 /* make sure changes to the buffer are synced */ 1103 bus_dmamap_sync(txq->ift_buf_tag, 1104 txq->ift_sds.ifsd_map[nic_i], 1105 BUS_DMASYNC_PREWRITE); 1106 1107 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED | NS_MOREFRAG); 1108 nm_i = nm_next(nm_i, lim); 1109 nic_i = nm_next(nic_i, lim); 1110 } 1111 kring->nr_hwcur = nm_i; 1112 1113 /* synchronize the NIC ring */ 1114 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1116 1117 /* (re)start the tx unit up to slot nic_i (excluded) */ 1118 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1119 } 1120 1121 /* 1122 * Second part: reclaim buffers for completed transmissions. 1123 * 1124 * If there are unclaimed buffers, attempt to reclaim them. 1125 * If we don't manage to reclaim them all, and TX IRQs are not in use, 1126 * trigger a per-tx-queue timer to try again later. 1127 */ 1128 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1129 if (iflib_tx_credits_update(ctx, txq)) { 1130 /* some tx completed, increment avail */ 1131 nic_i = txq->ift_cidx_processed; 1132 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1133 } 1134 } 1135 1136 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1137 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1138 callout_reset_sbt_on(&txq->ift_netmap_timer, 1139 NETMAP_TX_TIMER_US * SBT_1US, SBT_1US, 1140 iflib_netmap_timer, txq, 1141 txq->ift_netmap_timer.c_cpu, 0); 1142 } 1143 1144 if_inc_counter(ifp, IFCOUNTER_OBYTES, tx_bytes); 1145 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tx_pkts); 1146 1147 return (0); 1148 } 1149 1150 /* 1151 * Reconcile kernel and user view of the receive ring. 1152 * Same as for the txsync, this routine must be efficient. 1153 * The caller guarantees a single invocations, but races against 1154 * the rest of the driver should be handled here. 1155 * 1156 * On call, kring->rhead is the first packet that userspace wants 1157 * to keep, and kring->rcur is the wakeup point. 1158 * The kernel has previously reported packets up to kring->rtail. 1159 * 1160 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1161 * of whether or not we received an interrupt. 1162 */ 1163 static int 1164 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1165 { 1166 struct netmap_adapter *na = kring->na; 1167 struct netmap_ring *ring = kring->ring; 1168 if_t ifp = na->ifp; 1169 uint32_t nm_i; /* index into the netmap ring */ 1170 uint32_t nic_i; /* index into the NIC ring */ 1171 u_int n; 1172 u_int const lim = kring->nkr_num_slots - 1; 1173 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1174 int i = 0, rx_bytes = 0, rx_pkts = 0; 1175 1176 if_ctx_t ctx = ifp->if_softc; 1177 if_shared_ctx_t sctx = ctx->ifc_sctx; 1178 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1179 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1180 iflib_fl_t fl = &rxq->ifr_fl[0]; 1181 struct if_rxd_info ri; 1182 qidx_t *cidxp; 1183 1184 /* 1185 * netmap only uses free list 0, to avoid out of order consumption 1186 * of receive buffers 1187 */ 1188 1189 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1190 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1191 1192 /* 1193 * First part: import newly received packets. 1194 * 1195 * nm_i is the index of the next free slot in the netmap ring, 1196 * nic_i is the index of the next received packet in the NIC ring 1197 * (or in the free list 0 if IFLIB_HAS_RXCQ is set), and they may 1198 * differ in case if_init() has been called while 1199 * in netmap mode. For the receive ring we have 1200 * 1201 * nic_i = fl->ifl_cidx; 1202 * nm_i = kring->nr_hwtail (previous) 1203 * and 1204 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1205 * 1206 * fl->ifl_cidx is set to 0 on a ring reinit 1207 */ 1208 if (netmap_no_pendintr || force_update) { 1209 uint32_t hwtail_lim = nm_prev(kring->nr_hwcur, lim); 1210 bool have_rxcq = sctx->isc_flags & IFLIB_HAS_RXCQ; 1211 int crclen = iflib_crcstrip ? 0 : 4; 1212 int error, avail; 1213 1214 /* 1215 * For the free list consumer index, we use the same 1216 * logic as in iflib_rxeof(). 1217 */ 1218 if (have_rxcq) 1219 cidxp = &rxq->ifr_cq_cidx; 1220 else 1221 cidxp = &fl->ifl_cidx; 1222 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1223 rxq->ifr_id, *cidxp, USHRT_MAX); 1224 1225 nic_i = fl->ifl_cidx; 1226 nm_i = netmap_idx_n2k(kring, nic_i); 1227 MPASS(nm_i == kring->nr_hwtail); 1228 for (n = 0; avail > 0 && nm_i != hwtail_lim; n++, avail--) { 1229 rxd_info_zero(&ri); 1230 ri.iri_frags = rxq->ifr_frags; 1231 ri.iri_qsidx = kring->ring_id; 1232 ri.iri_ifp = ctx->ifc_ifp; 1233 ri.iri_cidx = *cidxp; 1234 1235 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1236 for (i = 0; i < ri.iri_nfrags; i++) { 1237 if (error) { 1238 ring->slot[nm_i].len = 0; 1239 ring->slot[nm_i].flags = 0; 1240 } else { 1241 ring->slot[nm_i].len = ri.iri_frags[i].irf_len; 1242 if (i == (ri.iri_nfrags - 1)) { 1243 ring->slot[nm_i].len -= crclen; 1244 ring->slot[nm_i].flags = 0; 1245 1246 /* Update receive counters */ 1247 rx_bytes += ri.iri_len; 1248 rx_pkts++; 1249 } else 1250 ring->slot[nm_i].flags = NS_MOREFRAG; 1251 } 1252 1253 bus_dmamap_sync(fl->ifl_buf_tag, 1254 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1255 nm_i = nm_next(nm_i, lim); 1256 fl->ifl_cidx = nic_i = nm_next(nic_i, lim); 1257 } 1258 1259 if (have_rxcq) { 1260 *cidxp = ri.iri_cidx; 1261 while (*cidxp >= scctx->isc_nrxd[0]) 1262 *cidxp -= scctx->isc_nrxd[0]; 1263 } 1264 1265 } 1266 if (n) { /* update the state variables */ 1267 if (netmap_no_pendintr && !force_update) { 1268 /* diagnostics */ 1269 iflib_rx_miss ++; 1270 iflib_rx_miss_bufs += n; 1271 } 1272 kring->nr_hwtail = nm_i; 1273 } 1274 kring->nr_kflags &= ~NKR_PENDINTR; 1275 } 1276 /* 1277 * Second part: skip past packets that userspace has released. 1278 * (kring->nr_hwcur to head excluded), 1279 * and make the buffers available for reception. 1280 * As usual nm_i is the index in the netmap ring, 1281 * nic_i is the index in the NIC ring, and 1282 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1283 */ 1284 netmap_fl_refill(rxq, kring, false); 1285 1286 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 1287 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 1288 1289 return (0); 1290 } 1291 1292 static void 1293 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1294 { 1295 if_ctx_t ctx = na->ifp->if_softc; 1296 1297 CTX_LOCK(ctx); 1298 if (onoff) { 1299 IFDI_INTR_ENABLE(ctx); 1300 } else { 1301 IFDI_INTR_DISABLE(ctx); 1302 } 1303 CTX_UNLOCK(ctx); 1304 } 1305 1306 static int 1307 iflib_netmap_attach(if_ctx_t ctx) 1308 { 1309 struct netmap_adapter na; 1310 1311 bzero(&na, sizeof(na)); 1312 1313 na.ifp = ctx->ifc_ifp; 1314 na.na_flags = NAF_BDG_MAYSLEEP | NAF_MOREFRAG | NAF_OFFSETS; 1315 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1316 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1317 1318 na.num_tx_desc = iflib_num_tx_descs(ctx); 1319 na.num_rx_desc = iflib_num_rx_descs(ctx); 1320 na.nm_txsync = iflib_netmap_txsync; 1321 na.nm_rxsync = iflib_netmap_rxsync; 1322 na.nm_register = iflib_netmap_register; 1323 na.nm_intr = iflib_netmap_intr; 1324 na.nm_config = iflib_netmap_config; 1325 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1326 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1327 return (netmap_attach(&na)); 1328 } 1329 1330 static int 1331 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1332 { 1333 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1334 struct netmap_slot *slot; 1335 1336 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1337 if (slot == NULL) 1338 return (0); 1339 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1340 /* 1341 * In netmap mode, set the map for the packet buffer. 1342 * NOTE: Some drivers (not this one) also need to set 1343 * the physical buffer address in the NIC ring. 1344 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1345 * netmap slot index, si 1346 */ 1347 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1348 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1349 NMB(na, slot + si)); 1350 } 1351 return (1); 1352 } 1353 1354 static int 1355 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1356 { 1357 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1358 struct netmap_kring *kring; 1359 struct netmap_slot *slot; 1360 1361 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1362 if (slot == NULL) 1363 return (0); 1364 kring = na->rx_rings[rxq->ifr_id]; 1365 netmap_fl_refill(rxq, kring, true); 1366 return (1); 1367 } 1368 1369 static void 1370 iflib_netmap_timer(void *arg) 1371 { 1372 iflib_txq_t txq = arg; 1373 if_ctx_t ctx = txq->ift_ctx; 1374 1375 /* 1376 * Wake up the netmap application, to give it a chance to 1377 * call txsync and reclaim more completed TX buffers. 1378 */ 1379 netmap_tx_irq(ctx->ifc_ifp, txq->ift_id); 1380 } 1381 1382 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1383 1384 #else 1385 #define iflib_netmap_txq_init(ctx, txq) (0) 1386 #define iflib_netmap_rxq_init(ctx, rxq) (0) 1387 #define iflib_netmap_detach(ifp) 1388 #define netmap_enable_all_rings(ifp) 1389 #define netmap_disable_all_rings(ifp) 1390 1391 #define iflib_netmap_attach(ctx) (0) 1392 #define netmap_rx_irq(ifp, qid, budget) (0) 1393 #endif 1394 1395 #if defined(__i386__) || defined(__amd64__) 1396 static __inline void 1397 prefetch(void *x) 1398 { 1399 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1400 } 1401 static __inline void 1402 prefetch2cachelines(void *x) 1403 { 1404 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1405 #if (CACHE_LINE_SIZE < 128) 1406 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1407 #endif 1408 } 1409 #else 1410 #define prefetch(x) 1411 #define prefetch2cachelines(x) 1412 #endif 1413 1414 static void 1415 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1416 { 1417 iflib_fl_t fl; 1418 1419 fl = &rxq->ifr_fl[flid]; 1420 iru->iru_paddrs = fl->ifl_bus_addrs; 1421 iru->iru_idxs = fl->ifl_rxd_idxs; 1422 iru->iru_qsidx = rxq->ifr_id; 1423 iru->iru_buf_size = fl->ifl_buf_size; 1424 iru->iru_flidx = fl->ifl_id; 1425 } 1426 1427 static void 1428 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1429 { 1430 if (err) 1431 return; 1432 *(bus_addr_t *) arg = segs[0].ds_addr; 1433 } 1434 1435 #define DMA_WIDTH_TO_BUS_LOWADDR(width) \ 1436 (((width) == 0) || (width) == flsll(BUS_SPACE_MAXADDR) ? \ 1437 BUS_SPACE_MAXADDR : (1ULL << (width)) - 1ULL) 1438 1439 int 1440 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1441 { 1442 int err; 1443 device_t dev = ctx->ifc_dev; 1444 bus_addr_t lowaddr; 1445 1446 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(ctx->ifc_softc_ctx.isc_dma_width); 1447 1448 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1449 align, 0, /* alignment, bounds */ 1450 lowaddr, /* lowaddr */ 1451 BUS_SPACE_MAXADDR, /* highaddr */ 1452 NULL, NULL, /* filter, filterarg */ 1453 size, /* maxsize */ 1454 1, /* nsegments */ 1455 size, /* maxsegsize */ 1456 BUS_DMA_ALLOCNOW, /* flags */ 1457 NULL, /* lockfunc */ 1458 NULL, /* lockarg */ 1459 &dma->idi_tag); 1460 if (err) { 1461 device_printf(dev, 1462 "%s: bus_dma_tag_create failed: %d\n", 1463 __func__, err); 1464 goto fail_0; 1465 } 1466 1467 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1468 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1469 if (err) { 1470 device_printf(dev, 1471 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1472 __func__, (uintmax_t)size, err); 1473 goto fail_1; 1474 } 1475 1476 dma->idi_paddr = IF_BAD_DMA; 1477 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1478 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1479 if (err || dma->idi_paddr == IF_BAD_DMA) { 1480 device_printf(dev, 1481 "%s: bus_dmamap_load failed: %d\n", 1482 __func__, err); 1483 goto fail_2; 1484 } 1485 1486 dma->idi_size = size; 1487 return (0); 1488 1489 fail_2: 1490 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1491 fail_1: 1492 bus_dma_tag_destroy(dma->idi_tag); 1493 fail_0: 1494 dma->idi_tag = NULL; 1495 1496 return (err); 1497 } 1498 1499 int 1500 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1501 { 1502 if_shared_ctx_t sctx = ctx->ifc_sctx; 1503 1504 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1505 1506 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1507 } 1508 1509 int 1510 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1511 { 1512 int i, err; 1513 iflib_dma_info_t *dmaiter; 1514 1515 dmaiter = dmalist; 1516 for (i = 0; i < count; i++, dmaiter++) { 1517 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1518 break; 1519 } 1520 if (err) 1521 iflib_dma_free_multi(dmalist, i); 1522 return (err); 1523 } 1524 1525 void 1526 iflib_dma_free(iflib_dma_info_t dma) 1527 { 1528 if (dma->idi_tag == NULL) 1529 return; 1530 if (dma->idi_paddr != IF_BAD_DMA) { 1531 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1532 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1533 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1534 dma->idi_paddr = IF_BAD_DMA; 1535 } 1536 if (dma->idi_vaddr != NULL) { 1537 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1538 dma->idi_vaddr = NULL; 1539 } 1540 bus_dma_tag_destroy(dma->idi_tag); 1541 dma->idi_tag = NULL; 1542 } 1543 1544 void 1545 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1546 { 1547 int i; 1548 iflib_dma_info_t *dmaiter = dmalist; 1549 1550 for (i = 0; i < count; i++, dmaiter++) 1551 iflib_dma_free(*dmaiter); 1552 } 1553 1554 static int 1555 iflib_fast_intr(void *arg) 1556 { 1557 iflib_filter_info_t info = arg; 1558 struct grouptask *gtask = info->ifi_task; 1559 int result; 1560 1561 DBG_COUNTER_INC(fast_intrs); 1562 if (info->ifi_filter != NULL) { 1563 result = info->ifi_filter(info->ifi_filter_arg); 1564 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1565 return (result); 1566 } 1567 1568 GROUPTASK_ENQUEUE(gtask); 1569 return (FILTER_HANDLED); 1570 } 1571 1572 static int 1573 iflib_fast_intr_rxtx(void *arg) 1574 { 1575 iflib_filter_info_t info = arg; 1576 struct grouptask *gtask = info->ifi_task; 1577 if_ctx_t ctx; 1578 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1579 iflib_txq_t txq; 1580 void *sc; 1581 int i, cidx, result; 1582 qidx_t txqid; 1583 bool intr_enable, intr_legacy; 1584 1585 DBG_COUNTER_INC(fast_intrs); 1586 if (info->ifi_filter != NULL) { 1587 result = info->ifi_filter(info->ifi_filter_arg); 1588 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1589 return (result); 1590 } 1591 1592 ctx = rxq->ifr_ctx; 1593 sc = ctx->ifc_softc; 1594 intr_enable = false; 1595 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1596 MPASS(rxq->ifr_ntxqirq); 1597 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1598 txqid = rxq->ifr_txqid[i]; 1599 txq = &ctx->ifc_txqs[txqid]; 1600 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1601 BUS_DMASYNC_POSTREAD); 1602 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1603 if (intr_legacy) 1604 intr_enable = true; 1605 else 1606 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1607 continue; 1608 } 1609 GROUPTASK_ENQUEUE(&txq->ift_task); 1610 } 1611 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1612 cidx = rxq->ifr_cq_cidx; 1613 else 1614 cidx = rxq->ifr_fl[0].ifl_cidx; 1615 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1616 GROUPTASK_ENQUEUE(gtask); 1617 else { 1618 if (intr_legacy) 1619 intr_enable = true; 1620 else 1621 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1622 DBG_COUNTER_INC(rx_intr_enables); 1623 } 1624 if (intr_enable) 1625 IFDI_INTR_ENABLE(ctx); 1626 return (FILTER_HANDLED); 1627 } 1628 1629 static int 1630 iflib_fast_intr_ctx(void *arg) 1631 { 1632 iflib_filter_info_t info = arg; 1633 struct grouptask *gtask = info->ifi_task; 1634 int result; 1635 1636 DBG_COUNTER_INC(fast_intrs); 1637 if (info->ifi_filter != NULL) { 1638 result = info->ifi_filter(info->ifi_filter_arg); 1639 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1640 return (result); 1641 } 1642 1643 GROUPTASK_ENQUEUE(gtask); 1644 return (FILTER_HANDLED); 1645 } 1646 1647 static int 1648 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1649 driver_filter_t filter, driver_intr_t handler, void *arg, 1650 const char *name) 1651 { 1652 struct resource *res; 1653 void *tag = NULL; 1654 device_t dev = ctx->ifc_dev; 1655 int flags, i, rc; 1656 1657 flags = RF_ACTIVE; 1658 if (ctx->ifc_flags & IFC_LEGACY) 1659 flags |= RF_SHAREABLE; 1660 MPASS(rid < 512); 1661 i = rid; 1662 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1663 if (res == NULL) { 1664 device_printf(dev, 1665 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1666 return (ENOMEM); 1667 } 1668 irq->ii_res = res; 1669 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1670 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1671 filter, handler, arg, &tag); 1672 if (rc != 0) { 1673 device_printf(dev, 1674 "failed to setup interrupt for rid %d, name %s: %d\n", 1675 rid, name ? name : "unknown", rc); 1676 return (rc); 1677 } else if (name) 1678 bus_describe_intr(dev, res, tag, "%s", name); 1679 1680 irq->ii_tag = tag; 1681 return (0); 1682 } 1683 1684 /********************************************************************* 1685 * 1686 * Allocate DMA resources for TX buffers as well as memory for the TX 1687 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1688 * iflib_sw_tx_desc_array structure, storing all the information that 1689 * is needed to transmit a packet on the wire. This is called only 1690 * once at attach, setup is done every reset. 1691 * 1692 **********************************************************************/ 1693 static int 1694 iflib_txsd_alloc(iflib_txq_t txq) 1695 { 1696 if_ctx_t ctx = txq->ift_ctx; 1697 if_shared_ctx_t sctx = ctx->ifc_sctx; 1698 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1699 device_t dev = ctx->ifc_dev; 1700 bus_size_t tsomaxsize; 1701 bus_addr_t lowaddr; 1702 int err, nsegments, ntsosegments; 1703 bool tso; 1704 1705 nsegments = scctx->isc_tx_nsegments; 1706 ntsosegments = scctx->isc_tx_tso_segments_max; 1707 tsomaxsize = scctx->isc_tx_tso_size_max; 1708 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1709 tsomaxsize += sizeof(struct ether_vlan_header); 1710 MPASS(scctx->isc_ntxd[0] > 0); 1711 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1712 MPASS(nsegments > 0); 1713 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1714 MPASS(ntsosegments > 0); 1715 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1716 } 1717 1718 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1719 1720 /* 1721 * Set up DMA tags for TX buffers. 1722 */ 1723 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1724 1, 0, /* alignment, bounds */ 1725 lowaddr, /* lowaddr */ 1726 BUS_SPACE_MAXADDR, /* highaddr */ 1727 NULL, NULL, /* filter, filterarg */ 1728 sctx->isc_tx_maxsize, /* maxsize */ 1729 nsegments, /* nsegments */ 1730 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1731 0, /* flags */ 1732 NULL, /* lockfunc */ 1733 NULL, /* lockfuncarg */ 1734 &txq->ift_buf_tag))) { 1735 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1736 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1737 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1738 goto fail; 1739 } 1740 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1741 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1742 1, 0, /* alignment, bounds */ 1743 lowaddr, /* lowaddr */ 1744 BUS_SPACE_MAXADDR, /* highaddr */ 1745 NULL, NULL, /* filter, filterarg */ 1746 tsomaxsize, /* maxsize */ 1747 ntsosegments, /* nsegments */ 1748 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1749 0, /* flags */ 1750 NULL, /* lockfunc */ 1751 NULL, /* lockfuncarg */ 1752 &txq->ift_tso_buf_tag))) { 1753 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1754 err); 1755 goto fail; 1756 } 1757 1758 /* Allocate memory for the TX mbuf map. */ 1759 if (!(txq->ift_sds.ifsd_m = 1760 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1761 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1762 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1763 err = ENOMEM; 1764 goto fail; 1765 } 1766 1767 /* 1768 * Create the DMA maps for TX buffers. 1769 */ 1770 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1771 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1772 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1773 device_printf(dev, 1774 "Unable to allocate TX buffer DMA map memory\n"); 1775 err = ENOMEM; 1776 goto fail; 1777 } 1778 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1779 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1780 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1781 device_printf(dev, 1782 "Unable to allocate TSO TX buffer map memory\n"); 1783 err = ENOMEM; 1784 goto fail; 1785 } 1786 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1787 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1788 &txq->ift_sds.ifsd_map[i]); 1789 if (err != 0) { 1790 device_printf(dev, "Unable to create TX DMA map\n"); 1791 goto fail; 1792 } 1793 if (!tso) 1794 continue; 1795 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1796 &txq->ift_sds.ifsd_tso_map[i]); 1797 if (err != 0) { 1798 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1799 goto fail; 1800 } 1801 } 1802 return (0); 1803 fail: 1804 /* We free all, it handles case where we are in the middle */ 1805 iflib_tx_structures_free(ctx); 1806 return (err); 1807 } 1808 1809 static void 1810 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1811 { 1812 bus_dmamap_t map; 1813 1814 if (txq->ift_sds.ifsd_map != NULL) { 1815 map = txq->ift_sds.ifsd_map[i]; 1816 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1817 bus_dmamap_unload(txq->ift_buf_tag, map); 1818 bus_dmamap_destroy(txq->ift_buf_tag, map); 1819 txq->ift_sds.ifsd_map[i] = NULL; 1820 } 1821 1822 if (txq->ift_sds.ifsd_tso_map != NULL) { 1823 map = txq->ift_sds.ifsd_tso_map[i]; 1824 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1825 BUS_DMASYNC_POSTWRITE); 1826 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1827 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1828 txq->ift_sds.ifsd_tso_map[i] = NULL; 1829 } 1830 } 1831 1832 static void 1833 iflib_txq_destroy(iflib_txq_t txq) 1834 { 1835 if_ctx_t ctx = txq->ift_ctx; 1836 1837 for (int i = 0; i < txq->ift_size; i++) 1838 iflib_txsd_destroy(ctx, txq, i); 1839 1840 if (txq->ift_br != NULL) { 1841 ifmp_ring_free(txq->ift_br); 1842 txq->ift_br = NULL; 1843 } 1844 1845 mtx_destroy(&txq->ift_mtx); 1846 1847 if (txq->ift_sds.ifsd_map != NULL) { 1848 free(txq->ift_sds.ifsd_map, M_IFLIB); 1849 txq->ift_sds.ifsd_map = NULL; 1850 } 1851 if (txq->ift_sds.ifsd_tso_map != NULL) { 1852 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1853 txq->ift_sds.ifsd_tso_map = NULL; 1854 } 1855 if (txq->ift_sds.ifsd_m != NULL) { 1856 free(txq->ift_sds.ifsd_m, M_IFLIB); 1857 txq->ift_sds.ifsd_m = NULL; 1858 } 1859 if (txq->ift_buf_tag != NULL) { 1860 bus_dma_tag_destroy(txq->ift_buf_tag); 1861 txq->ift_buf_tag = NULL; 1862 } 1863 if (txq->ift_tso_buf_tag != NULL) { 1864 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1865 txq->ift_tso_buf_tag = NULL; 1866 } 1867 if (txq->ift_ifdi != NULL) { 1868 free(txq->ift_ifdi, M_IFLIB); 1869 } 1870 } 1871 1872 static void 1873 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1874 { 1875 struct mbuf **mp; 1876 1877 mp = &txq->ift_sds.ifsd_m[i]; 1878 if (*mp == NULL) 1879 return; 1880 1881 if (txq->ift_sds.ifsd_map != NULL) { 1882 bus_dmamap_sync(txq->ift_buf_tag, 1883 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1884 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1885 } 1886 if (txq->ift_sds.ifsd_tso_map != NULL) { 1887 bus_dmamap_sync(txq->ift_tso_buf_tag, 1888 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1889 bus_dmamap_unload(txq->ift_tso_buf_tag, 1890 txq->ift_sds.ifsd_tso_map[i]); 1891 } 1892 m_freem(*mp); 1893 DBG_COUNTER_INC(tx_frees); 1894 *mp = NULL; 1895 } 1896 1897 static int 1898 iflib_txq_setup(iflib_txq_t txq) 1899 { 1900 if_ctx_t ctx = txq->ift_ctx; 1901 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1902 if_shared_ctx_t sctx = ctx->ifc_sctx; 1903 iflib_dma_info_t di; 1904 int i; 1905 1906 /* Set number of descriptors available */ 1907 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1908 /* XXX make configurable */ 1909 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1910 1911 /* Reset indices */ 1912 txq->ift_cidx_processed = 0; 1913 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1914 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1915 1916 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1917 bzero((void *)di->idi_vaddr, di->idi_size); 1918 1919 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1920 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1921 bus_dmamap_sync(di->idi_tag, di->idi_map, 1922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1923 return (0); 1924 } 1925 1926 /********************************************************************* 1927 * 1928 * Allocate DMA resources for RX buffers as well as memory for the RX 1929 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1930 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1931 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1932 * Since we use use one entry in iflib_sw_rx_desc_array per received 1933 * packet, the maximum number of entries we'll need is equal to the 1934 * number of hardware receive descriptors that we've allocated. 1935 * 1936 **********************************************************************/ 1937 static int 1938 iflib_rxsd_alloc(iflib_rxq_t rxq) 1939 { 1940 if_ctx_t ctx = rxq->ifr_ctx; 1941 if_shared_ctx_t sctx = ctx->ifc_sctx; 1942 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1943 device_t dev = ctx->ifc_dev; 1944 iflib_fl_t fl; 1945 bus_addr_t lowaddr; 1946 int err; 1947 1948 MPASS(scctx->isc_nrxd[0] > 0); 1949 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1950 1951 lowaddr = DMA_WIDTH_TO_BUS_LOWADDR(scctx->isc_dma_width); 1952 1953 fl = rxq->ifr_fl; 1954 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1955 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1956 /* Set up DMA tag for RX buffers. */ 1957 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1958 1, 0, /* alignment, bounds */ 1959 lowaddr, /* lowaddr */ 1960 BUS_SPACE_MAXADDR, /* highaddr */ 1961 NULL, NULL, /* filter, filterarg */ 1962 sctx->isc_rx_maxsize, /* maxsize */ 1963 sctx->isc_rx_nsegments, /* nsegments */ 1964 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1965 0, /* flags */ 1966 NULL, /* lockfunc */ 1967 NULL, /* lockarg */ 1968 &fl->ifl_buf_tag); 1969 if (err) { 1970 device_printf(dev, 1971 "Unable to allocate RX DMA tag: %d\n", err); 1972 goto fail; 1973 } 1974 1975 /* Allocate memory for the RX mbuf map. */ 1976 if (!(fl->ifl_sds.ifsd_m = 1977 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1978 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1979 device_printf(dev, 1980 "Unable to allocate RX mbuf map memory\n"); 1981 err = ENOMEM; 1982 goto fail; 1983 } 1984 1985 /* Allocate memory for the direct RX cluster pointer map. */ 1986 if (!(fl->ifl_sds.ifsd_cl = 1987 (caddr_t *) malloc(sizeof(caddr_t) * 1988 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1989 device_printf(dev, 1990 "Unable to allocate RX cluster map memory\n"); 1991 err = ENOMEM; 1992 goto fail; 1993 } 1994 1995 /* Allocate memory for the RX cluster bus address map. */ 1996 if (!(fl->ifl_sds.ifsd_ba = 1997 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1998 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1999 device_printf(dev, 2000 "Unable to allocate RX bus address map memory\n"); 2001 err = ENOMEM; 2002 goto fail; 2003 } 2004 2005 /* 2006 * Create the DMA maps for RX buffers. 2007 */ 2008 if (!(fl->ifl_sds.ifsd_map = 2009 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 2010 device_printf(dev, 2011 "Unable to allocate RX buffer DMA map memory\n"); 2012 err = ENOMEM; 2013 goto fail; 2014 } 2015 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 2016 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 2017 &fl->ifl_sds.ifsd_map[i]); 2018 if (err != 0) { 2019 device_printf(dev, "Unable to create RX buffer DMA map\n"); 2020 goto fail; 2021 } 2022 } 2023 } 2024 return (0); 2025 2026 fail: 2027 iflib_rx_structures_free(ctx); 2028 return (err); 2029 } 2030 2031 /* 2032 * Internal service routines 2033 */ 2034 2035 struct rxq_refill_cb_arg { 2036 int error; 2037 bus_dma_segment_t seg; 2038 int nseg; 2039 }; 2040 2041 static void 2042 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2043 { 2044 struct rxq_refill_cb_arg *cb_arg = arg; 2045 2046 cb_arg->error = error; 2047 cb_arg->seg = segs[0]; 2048 cb_arg->nseg = nseg; 2049 } 2050 2051 /** 2052 * iflib_fl_refill - refill an rxq free-buffer list 2053 * @ctx: the iflib context 2054 * @fl: the free list to refill 2055 * @count: the number of new buffers to allocate 2056 * 2057 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 2058 * The caller must assure that @count does not exceed the queue's capacity 2059 * minus one (since we always leave a descriptor unavailable). 2060 */ 2061 static uint8_t 2062 iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 2063 { 2064 struct if_rxd_update iru; 2065 struct rxq_refill_cb_arg cb_arg; 2066 struct mbuf *m; 2067 caddr_t cl, *sd_cl; 2068 struct mbuf **sd_m; 2069 bus_dmamap_t *sd_map; 2070 bus_addr_t bus_addr, *sd_ba; 2071 int err, frag_idx, i, idx, n, pidx; 2072 qidx_t credits; 2073 2074 MPASS(count <= fl->ifl_size - fl->ifl_credits - 1); 2075 2076 sd_m = fl->ifl_sds.ifsd_m; 2077 sd_map = fl->ifl_sds.ifsd_map; 2078 sd_cl = fl->ifl_sds.ifsd_cl; 2079 sd_ba = fl->ifl_sds.ifsd_ba; 2080 pidx = fl->ifl_pidx; 2081 idx = pidx; 2082 frag_idx = fl->ifl_fragidx; 2083 credits = fl->ifl_credits; 2084 2085 i = 0; 2086 n = count; 2087 MPASS(n > 0); 2088 MPASS(credits + n <= fl->ifl_size); 2089 2090 if (pidx < fl->ifl_cidx) 2091 MPASS(pidx + n <= fl->ifl_cidx); 2092 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 2093 MPASS(fl->ifl_gen == 0); 2094 if (pidx > fl->ifl_cidx) 2095 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 2096 2097 DBG_COUNTER_INC(fl_refills); 2098 if (n > 8) 2099 DBG_COUNTER_INC(fl_refills_large); 2100 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 2101 while (n-- > 0) { 2102 /* 2103 * We allocate an uninitialized mbuf + cluster, mbuf is 2104 * initialized after rx. 2105 * 2106 * If the cluster is still set then we know a minimum sized 2107 * packet was received 2108 */ 2109 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 2110 &frag_idx); 2111 if (frag_idx < 0) 2112 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 2113 MPASS(frag_idx >= 0); 2114 if ((cl = sd_cl[frag_idx]) == NULL) { 2115 cl = uma_zalloc(fl->ifl_zone, M_NOWAIT); 2116 if (__predict_false(cl == NULL)) 2117 break; 2118 2119 cb_arg.error = 0; 2120 MPASS(sd_map != NULL); 2121 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 2122 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 2123 BUS_DMA_NOWAIT); 2124 if (__predict_false(err != 0 || cb_arg.error)) { 2125 uma_zfree(fl->ifl_zone, cl); 2126 break; 2127 } 2128 2129 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 2130 sd_cl[frag_idx] = cl; 2131 #if MEMORY_LOGGING 2132 fl->ifl_cl_enqueued++; 2133 #endif 2134 } else { 2135 bus_addr = sd_ba[frag_idx]; 2136 } 2137 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 2138 BUS_DMASYNC_PREREAD); 2139 2140 if (sd_m[frag_idx] == NULL) { 2141 m = m_gethdr_raw(M_NOWAIT, 0); 2142 if (__predict_false(m == NULL)) 2143 break; 2144 sd_m[frag_idx] = m; 2145 } 2146 bit_set(fl->ifl_rx_bitmap, frag_idx); 2147 #if MEMORY_LOGGING 2148 fl->ifl_m_enqueued++; 2149 #endif 2150 2151 DBG_COUNTER_INC(rx_allocs); 2152 fl->ifl_rxd_idxs[i] = frag_idx; 2153 fl->ifl_bus_addrs[i] = bus_addr; 2154 credits++; 2155 i++; 2156 MPASS(credits <= fl->ifl_size); 2157 if (++idx == fl->ifl_size) { 2158 #ifdef INVARIANTS 2159 fl->ifl_gen = 1; 2160 #endif 2161 idx = 0; 2162 } 2163 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2164 iru.iru_pidx = pidx; 2165 iru.iru_count = i; 2166 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2167 fl->ifl_pidx = idx; 2168 fl->ifl_credits = credits; 2169 pidx = idx; 2170 i = 0; 2171 } 2172 } 2173 2174 if (n < count - 1) { 2175 if (i != 0) { 2176 iru.iru_pidx = pidx; 2177 iru.iru_count = i; 2178 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2179 fl->ifl_pidx = idx; 2180 fl->ifl_credits = credits; 2181 } 2182 DBG_COUNTER_INC(rxd_flush); 2183 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2184 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2185 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, 2186 fl->ifl_id, fl->ifl_pidx); 2187 if (__predict_true(bit_test(fl->ifl_rx_bitmap, frag_idx))) { 2188 fl->ifl_fragidx = frag_idx + 1; 2189 if (fl->ifl_fragidx == fl->ifl_size) 2190 fl->ifl_fragidx = 0; 2191 } else { 2192 fl->ifl_fragidx = frag_idx; 2193 } 2194 } 2195 2196 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2197 } 2198 2199 static inline uint8_t 2200 iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2201 { 2202 /* 2203 * We leave an unused descriptor to avoid pidx to catch up with cidx. 2204 * This is important as it confuses most NICs. For instance, 2205 * Intel NICs have (per receive ring) RDH and RDT registers, where 2206 * RDH points to the next receive descriptor to be used by the NIC, 2207 * and RDT for the next receive descriptor to be published by the 2208 * driver to the NIC (RDT - 1 is thus the last valid one). 2209 * The condition RDH == RDT means no descriptors are available to 2210 * the NIC, and thus it would be ambiguous if it also meant that 2211 * all the descriptors are available to the NIC. 2212 */ 2213 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2214 #ifdef INVARIANTS 2215 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2216 #endif 2217 2218 MPASS(fl->ifl_credits <= fl->ifl_size); 2219 MPASS(reclaimable == delta); 2220 2221 if (reclaimable > 0) 2222 return (iflib_fl_refill(ctx, fl, reclaimable)); 2223 return (0); 2224 } 2225 2226 uint8_t 2227 iflib_in_detach(if_ctx_t ctx) 2228 { 2229 bool in_detach; 2230 2231 STATE_LOCK(ctx); 2232 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2233 STATE_UNLOCK(ctx); 2234 return (in_detach); 2235 } 2236 2237 static void 2238 iflib_fl_bufs_free(iflib_fl_t fl) 2239 { 2240 iflib_dma_info_t idi = fl->ifl_ifdi; 2241 bus_dmamap_t sd_map; 2242 uint32_t i; 2243 2244 for (i = 0; i < fl->ifl_size; i++) { 2245 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2246 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2247 2248 if (*sd_cl != NULL) { 2249 sd_map = fl->ifl_sds.ifsd_map[i]; 2250 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2251 BUS_DMASYNC_POSTREAD); 2252 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2253 uma_zfree(fl->ifl_zone, *sd_cl); 2254 *sd_cl = NULL; 2255 if (*sd_m != NULL) { 2256 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2257 m_free_raw(*sd_m); 2258 *sd_m = NULL; 2259 } 2260 } else { 2261 MPASS(*sd_m == NULL); 2262 } 2263 #if MEMORY_LOGGING 2264 fl->ifl_m_dequeued++; 2265 fl->ifl_cl_dequeued++; 2266 #endif 2267 } 2268 #ifdef INVARIANTS 2269 for (i = 0; i < fl->ifl_size; i++) { 2270 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2271 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2272 } 2273 #endif 2274 /* 2275 * Reset free list values 2276 */ 2277 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2278 bzero(idi->idi_vaddr, idi->idi_size); 2279 } 2280 2281 /********************************************************************* 2282 * 2283 * Initialize a free list and its buffers. 2284 * 2285 **********************************************************************/ 2286 static int 2287 iflib_fl_setup(iflib_fl_t fl) 2288 { 2289 iflib_rxq_t rxq = fl->ifl_rxq; 2290 if_ctx_t ctx = rxq->ifr_ctx; 2291 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2292 int qidx; 2293 2294 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2295 /* 2296 ** Free current RX buffer structs and their mbufs 2297 */ 2298 iflib_fl_bufs_free(fl); 2299 /* Now replenish the mbufs */ 2300 MPASS(fl->ifl_credits == 0); 2301 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2302 if (scctx->isc_rxd_buf_size[qidx] != 0) 2303 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2304 else 2305 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2306 /* 2307 * ifl_buf_size may be a driver-supplied value, so pull it up 2308 * to the selected mbuf size. 2309 */ 2310 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2311 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2312 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2313 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2314 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2315 2316 /* 2317 * Avoid pre-allocating zillions of clusters to an idle card 2318 * potentially speeding up attach. In any case make sure 2319 * to leave a descriptor unavailable. See the comment in 2320 * iflib_fl_refill_all(). 2321 */ 2322 MPASS(fl->ifl_size > 0); 2323 (void)iflib_fl_refill(ctx, fl, min(128, fl->ifl_size - 1)); 2324 if (min(128, fl->ifl_size - 1) != fl->ifl_credits) 2325 return (ENOBUFS); 2326 /* 2327 * handle failure 2328 */ 2329 MPASS(rxq != NULL); 2330 MPASS(fl->ifl_ifdi != NULL); 2331 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2332 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2333 return (0); 2334 } 2335 2336 /********************************************************************* 2337 * 2338 * Free receive ring data structures 2339 * 2340 **********************************************************************/ 2341 static void 2342 iflib_rx_sds_free(iflib_rxq_t rxq) 2343 { 2344 iflib_fl_t fl; 2345 int i, j; 2346 2347 if (rxq->ifr_fl != NULL) { 2348 for (i = 0; i < rxq->ifr_nfl; i++) { 2349 fl = &rxq->ifr_fl[i]; 2350 if (fl->ifl_buf_tag != NULL) { 2351 if (fl->ifl_sds.ifsd_map != NULL) { 2352 for (j = 0; j < fl->ifl_size; j++) { 2353 bus_dmamap_sync( 2354 fl->ifl_buf_tag, 2355 fl->ifl_sds.ifsd_map[j], 2356 BUS_DMASYNC_POSTREAD); 2357 bus_dmamap_unload( 2358 fl->ifl_buf_tag, 2359 fl->ifl_sds.ifsd_map[j]); 2360 bus_dmamap_destroy( 2361 fl->ifl_buf_tag, 2362 fl->ifl_sds.ifsd_map[j]); 2363 } 2364 } 2365 bus_dma_tag_destroy(fl->ifl_buf_tag); 2366 fl->ifl_buf_tag = NULL; 2367 } 2368 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2369 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2370 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2371 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2372 free(fl->ifl_rx_bitmap, M_IFLIB); 2373 fl->ifl_sds.ifsd_m = NULL; 2374 fl->ifl_sds.ifsd_cl = NULL; 2375 fl->ifl_sds.ifsd_ba = NULL; 2376 fl->ifl_sds.ifsd_map = NULL; 2377 fl->ifl_rx_bitmap = NULL; 2378 } 2379 free(rxq->ifr_fl, M_IFLIB); 2380 rxq->ifr_fl = NULL; 2381 free(rxq->ifr_ifdi, M_IFLIB); 2382 rxq->ifr_ifdi = NULL; 2383 rxq->ifr_cq_cidx = 0; 2384 } 2385 } 2386 2387 /* 2388 * Timer routine 2389 */ 2390 static void 2391 iflib_timer(void *arg) 2392 { 2393 iflib_txq_t txq = arg; 2394 if_ctx_t ctx = txq->ift_ctx; 2395 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2396 uint64_t this_tick = ticks; 2397 2398 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2399 return; 2400 2401 /* 2402 ** Check on the state of the TX queue(s), this 2403 ** can be done without the lock because its RO 2404 ** and the HUNG state will be static if set. 2405 */ 2406 if (this_tick - txq->ift_last_timer_tick >= iflib_timer_default) { 2407 txq->ift_last_timer_tick = this_tick; 2408 IFDI_TIMER(ctx, txq->ift_id); 2409 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2410 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2411 (sctx->isc_pause_frames == 0))) 2412 goto hung; 2413 2414 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2415 ifmp_ring_is_stalled(txq->ift_br)) { 2416 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, 2417 ("queue can't be marked as hung if interface is down")); 2418 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2419 } 2420 txq->ift_cleaned_prev = txq->ift_cleaned; 2421 } 2422 /* handle any laggards */ 2423 if (txq->ift_db_pending) 2424 GROUPTASK_ENQUEUE(&txq->ift_task); 2425 2426 sctx->isc_pause_frames = 0; 2427 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2428 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, 2429 txq, txq->ift_timer.c_cpu); 2430 return; 2431 2432 hung: 2433 device_printf(ctx->ifc_dev, 2434 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2435 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2436 STATE_LOCK(ctx); 2437 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2438 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2439 iflib_admin_intr_deferred(ctx); 2440 STATE_UNLOCK(ctx); 2441 } 2442 2443 static uint16_t 2444 iflib_get_mbuf_size_for(unsigned int size) 2445 { 2446 2447 if (size <= MCLBYTES) 2448 return (MCLBYTES); 2449 else 2450 return (MJUMPAGESIZE); 2451 } 2452 2453 static void 2454 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2455 { 2456 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2457 2458 /* 2459 * XXX don't set the max_frame_size to larger 2460 * than the hardware can handle 2461 */ 2462 ctx->ifc_rx_mbuf_sz = 2463 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2464 } 2465 2466 uint32_t 2467 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2468 { 2469 2470 return (ctx->ifc_rx_mbuf_sz); 2471 } 2472 2473 static void 2474 iflib_init_locked(if_ctx_t ctx) 2475 { 2476 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2477 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2478 if_t ifp = ctx->ifc_ifp; 2479 iflib_fl_t fl; 2480 iflib_txq_t txq; 2481 iflib_rxq_t rxq; 2482 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2483 2484 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2485 IFDI_INTR_DISABLE(ctx); 2486 2487 /* 2488 * See iflib_stop(). Useful in case iflib_init_locked() is 2489 * called without first calling iflib_stop(). 2490 */ 2491 netmap_disable_all_rings(ifp); 2492 2493 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2494 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2495 /* Set hardware offload abilities */ 2496 if_clearhwassist(ifp); 2497 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2498 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2499 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2500 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2501 if (if_getcapenable(ifp) & IFCAP_TSO4) 2502 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2503 if (if_getcapenable(ifp) & IFCAP_TSO6) 2504 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2505 2506 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2507 CALLOUT_LOCK(txq); 2508 callout_stop(&txq->ift_timer); 2509 #ifdef DEV_NETMAP 2510 callout_stop(&txq->ift_netmap_timer); 2511 #endif /* DEV_NETMAP */ 2512 CALLOUT_UNLOCK(txq); 2513 (void)iflib_netmap_txq_init(ctx, txq); 2514 } 2515 2516 /* 2517 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2518 * that drivers can use the value when setting up the hardware receive 2519 * buffers. 2520 */ 2521 iflib_calc_rx_mbuf_sz(ctx); 2522 2523 #ifdef INVARIANTS 2524 i = if_getdrvflags(ifp); 2525 #endif 2526 IFDI_INIT(ctx); 2527 MPASS(if_getdrvflags(ifp) == i); 2528 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2529 if (iflib_netmap_rxq_init(ctx, rxq) > 0) { 2530 /* This rxq is in netmap mode. Skip normal init. */ 2531 continue; 2532 } 2533 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2534 if (iflib_fl_setup(fl)) { 2535 device_printf(ctx->ifc_dev, 2536 "setting up free list %d failed - " 2537 "check cluster settings\n", j); 2538 goto done; 2539 } 2540 } 2541 } 2542 done: 2543 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2544 IFDI_INTR_ENABLE(ctx); 2545 txq = ctx->ifc_txqs; 2546 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2547 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 2548 txq->ift_timer.c_cpu); 2549 2550 /* Re-enable txsync/rxsync. */ 2551 netmap_enable_all_rings(ifp); 2552 } 2553 2554 static int 2555 iflib_media_change(if_t ifp) 2556 { 2557 if_ctx_t ctx = if_getsoftc(ifp); 2558 int err; 2559 2560 CTX_LOCK(ctx); 2561 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2562 iflib_if_init_locked(ctx); 2563 CTX_UNLOCK(ctx); 2564 return (err); 2565 } 2566 2567 static void 2568 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2569 { 2570 if_ctx_t ctx = if_getsoftc(ifp); 2571 2572 CTX_LOCK(ctx); 2573 IFDI_UPDATE_ADMIN_STATUS(ctx); 2574 IFDI_MEDIA_STATUS(ctx, ifmr); 2575 CTX_UNLOCK(ctx); 2576 } 2577 2578 void 2579 iflib_stop(if_ctx_t ctx) 2580 { 2581 iflib_txq_t txq = ctx->ifc_txqs; 2582 iflib_rxq_t rxq = ctx->ifc_rxqs; 2583 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2584 if_shared_ctx_t sctx = ctx->ifc_sctx; 2585 iflib_dma_info_t di; 2586 iflib_fl_t fl; 2587 int i, j; 2588 2589 /* Tell the stack that the interface is no longer active */ 2590 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2591 2592 IFDI_INTR_DISABLE(ctx); 2593 DELAY(1000); 2594 IFDI_STOP(ctx); 2595 DELAY(1000); 2596 2597 /* 2598 * Stop any pending txsync/rxsync and prevent new ones 2599 * form starting. Processes blocked in poll() will get 2600 * POLLERR. 2601 */ 2602 netmap_disable_all_rings(ctx->ifc_ifp); 2603 2604 iflib_debug_reset(); 2605 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2606 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2607 /* make sure all transmitters have completed before proceeding XXX */ 2608 2609 CALLOUT_LOCK(txq); 2610 callout_stop(&txq->ift_timer); 2611 #ifdef DEV_NETMAP 2612 callout_stop(&txq->ift_netmap_timer); 2613 #endif /* DEV_NETMAP */ 2614 CALLOUT_UNLOCK(txq); 2615 2616 /* clean any enqueued buffers */ 2617 iflib_ifmp_purge(txq); 2618 /* Free any existing tx buffers. */ 2619 for (j = 0; j < txq->ift_size; j++) { 2620 iflib_txsd_free(ctx, txq, j); 2621 } 2622 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2623 txq->ift_in_use = txq->ift_gen = txq->ift_no_desc_avail = 0; 2624 if (sctx->isc_flags & IFLIB_PRESERVE_TX_INDICES) 2625 txq->ift_cidx = txq->ift_pidx; 2626 else 2627 txq->ift_cidx = txq->ift_pidx = 0; 2628 2629 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2630 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2631 txq->ift_pullups = 0; 2632 ifmp_ring_reset_stats(txq->ift_br); 2633 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2634 bzero((void *)di->idi_vaddr, di->idi_size); 2635 } 2636 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2637 gtaskqueue_drain(rxq->ifr_task.gt_taskqueue, 2638 &rxq->ifr_task.gt_task); 2639 2640 rxq->ifr_cq_cidx = 0; 2641 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2642 bzero((void *)di->idi_vaddr, di->idi_size); 2643 /* also resets the free lists pidx/cidx */ 2644 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2645 iflib_fl_bufs_free(fl); 2646 } 2647 } 2648 2649 static inline caddr_t 2650 calc_next_rxd(iflib_fl_t fl, int cidx) 2651 { 2652 qidx_t size; 2653 int nrxd; 2654 caddr_t start, end, cur, next; 2655 2656 nrxd = fl->ifl_size; 2657 size = fl->ifl_rxd_size; 2658 start = fl->ifl_ifdi->idi_vaddr; 2659 2660 if (__predict_false(size == 0)) 2661 return (start); 2662 cur = start + size*cidx; 2663 end = start + size*nrxd; 2664 next = CACHE_PTR_NEXT(cur); 2665 return (next < end ? next : start); 2666 } 2667 2668 static inline void 2669 prefetch_pkts(iflib_fl_t fl, int cidx) 2670 { 2671 int nextptr; 2672 int nrxd = fl->ifl_size; 2673 caddr_t next_rxd; 2674 2675 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2676 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2677 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2678 next_rxd = calc_next_rxd(fl, cidx); 2679 prefetch(next_rxd); 2680 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2681 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2682 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2683 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2684 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2685 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2686 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2687 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2688 } 2689 2690 static struct mbuf * 2691 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2692 int *pf_rv, if_rxd_info_t ri) 2693 { 2694 bus_dmamap_t map; 2695 iflib_fl_t fl; 2696 caddr_t payload; 2697 struct mbuf *m; 2698 int flid, cidx, len, next; 2699 2700 map = NULL; 2701 flid = irf->irf_flid; 2702 cidx = irf->irf_idx; 2703 fl = &rxq->ifr_fl[flid]; 2704 sd->ifsd_fl = fl; 2705 m = fl->ifl_sds.ifsd_m[cidx]; 2706 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2707 fl->ifl_credits--; 2708 #if MEMORY_LOGGING 2709 fl->ifl_m_dequeued++; 2710 #endif 2711 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2712 prefetch_pkts(fl, cidx); 2713 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2714 prefetch(&fl->ifl_sds.ifsd_map[next]); 2715 map = fl->ifl_sds.ifsd_map[cidx]; 2716 2717 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2718 2719 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2720 irf->irf_len != 0) { 2721 payload = *sd->ifsd_cl; 2722 payload += ri->iri_pad; 2723 len = ri->iri_len - ri->iri_pad; 2724 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2725 len | PFIL_MEMPTR | PFIL_IN, NULL); 2726 switch (*pf_rv) { 2727 case PFIL_DROPPED: 2728 case PFIL_CONSUMED: 2729 /* 2730 * The filter ate it. Everything is recycled. 2731 */ 2732 m = NULL; 2733 unload = 0; 2734 break; 2735 case PFIL_REALLOCED: 2736 /* 2737 * The filter copied it. Everything is recycled. 2738 */ 2739 m = pfil_mem2mbuf(payload); 2740 unload = 0; 2741 break; 2742 case PFIL_PASS: 2743 /* 2744 * Filter said it was OK, so receive like 2745 * normal 2746 */ 2747 fl->ifl_sds.ifsd_m[cidx] = NULL; 2748 break; 2749 default: 2750 MPASS(0); 2751 } 2752 } else { 2753 fl->ifl_sds.ifsd_m[cidx] = NULL; 2754 if (pf_rv != NULL) 2755 *pf_rv = PFIL_PASS; 2756 } 2757 2758 if (unload && irf->irf_len != 0) 2759 bus_dmamap_unload(fl->ifl_buf_tag, map); 2760 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2761 if (__predict_false(fl->ifl_cidx == 0)) 2762 fl->ifl_gen = 0; 2763 bit_clear(fl->ifl_rx_bitmap, cidx); 2764 return (m); 2765 } 2766 2767 static struct mbuf * 2768 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2769 { 2770 struct mbuf *m, *mh, *mt; 2771 caddr_t cl; 2772 int *pf_rv_ptr, flags, i, padlen; 2773 bool consumed; 2774 2775 i = 0; 2776 mh = NULL; 2777 consumed = false; 2778 *pf_rv = PFIL_PASS; 2779 pf_rv_ptr = pf_rv; 2780 do { 2781 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2782 pf_rv_ptr, ri); 2783 2784 MPASS(*sd->ifsd_cl != NULL); 2785 2786 /* 2787 * Exclude zero-length frags & frags from 2788 * packets the filter has consumed or dropped 2789 */ 2790 if (ri->iri_frags[i].irf_len == 0 || consumed || 2791 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2792 if (mh == NULL) { 2793 /* everything saved here */ 2794 consumed = true; 2795 pf_rv_ptr = NULL; 2796 continue; 2797 } 2798 /* XXX we can save the cluster here, but not the mbuf */ 2799 m_init(m, M_NOWAIT, MT_DATA, 0); 2800 m_free(m); 2801 continue; 2802 } 2803 if (mh == NULL) { 2804 flags = M_PKTHDR|M_EXT; 2805 mh = mt = m; 2806 padlen = ri->iri_pad; 2807 } else { 2808 flags = M_EXT; 2809 mt->m_next = m; 2810 mt = m; 2811 /* assuming padding is only on the first fragment */ 2812 padlen = 0; 2813 } 2814 cl = *sd->ifsd_cl; 2815 *sd->ifsd_cl = NULL; 2816 2817 /* Can these two be made one ? */ 2818 m_init(m, M_NOWAIT, MT_DATA, flags); 2819 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2820 /* 2821 * These must follow m_init and m_cljset 2822 */ 2823 m->m_data += padlen; 2824 ri->iri_len -= padlen; 2825 m->m_len = ri->iri_frags[i].irf_len; 2826 } while (++i < ri->iri_nfrags); 2827 2828 return (mh); 2829 } 2830 2831 /* 2832 * Process one software descriptor 2833 */ 2834 static struct mbuf * 2835 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2836 { 2837 struct if_rxsd sd; 2838 struct mbuf *m; 2839 int pf_rv; 2840 2841 /* should I merge this back in now that the two paths are basically duplicated? */ 2842 if (ri->iri_nfrags == 1 && 2843 ri->iri_frags[0].irf_len != 0 && 2844 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2845 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2846 &pf_rv, ri); 2847 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2848 return (m); 2849 if (pf_rv == PFIL_PASS) { 2850 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2851 #ifndef __NO_STRICT_ALIGNMENT 2852 if (!IP_ALIGNED(m) && ri->iri_pad == 0) 2853 m->m_data += 2; 2854 #endif 2855 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2856 m->m_len = ri->iri_frags[0].irf_len; 2857 m->m_data += ri->iri_pad; 2858 ri->iri_len -= ri->iri_pad; 2859 } 2860 } else { 2861 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2862 if (m == NULL) 2863 return (NULL); 2864 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2865 return (m); 2866 } 2867 m->m_pkthdr.len = ri->iri_len; 2868 m->m_pkthdr.rcvif = ri->iri_ifp; 2869 m->m_flags |= ri->iri_flags; 2870 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2871 m->m_pkthdr.flowid = ri->iri_flowid; 2872 M_HASHTYPE_SET(m, ri->iri_rsstype); 2873 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2874 m->m_pkthdr.csum_data = ri->iri_csum_data; 2875 return (m); 2876 } 2877 2878 #if defined(INET6) || defined(INET) 2879 static void 2880 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2881 { 2882 CURVNET_SET(lc->ifp->if_vnet); 2883 #if defined(INET6) 2884 *v6 = V_ip6_forwarding; 2885 #endif 2886 #if defined(INET) 2887 *v4 = V_ipforwarding; 2888 #endif 2889 CURVNET_RESTORE(); 2890 } 2891 2892 /* 2893 * Returns true if it's possible this packet could be LROed. 2894 * if it returns false, it is guaranteed that tcp_lro_rx() 2895 * would not return zero. 2896 */ 2897 static bool 2898 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2899 { 2900 struct ether_header *eh; 2901 2902 eh = mtod(m, struct ether_header *); 2903 switch (eh->ether_type) { 2904 #if defined(INET6) 2905 case htons(ETHERTYPE_IPV6): 2906 return (!v6_forwarding); 2907 #endif 2908 #if defined (INET) 2909 case htons(ETHERTYPE_IP): 2910 return (!v4_forwarding); 2911 #endif 2912 } 2913 2914 return false; 2915 } 2916 #else 2917 static void 2918 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2919 { 2920 } 2921 #endif 2922 2923 static void 2924 _task_fn_rx_watchdog(void *context) 2925 { 2926 iflib_rxq_t rxq = context; 2927 2928 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2929 } 2930 2931 static uint8_t 2932 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2933 { 2934 if_t ifp; 2935 if_ctx_t ctx = rxq->ifr_ctx; 2936 if_shared_ctx_t sctx = ctx->ifc_sctx; 2937 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2938 int avail, i; 2939 qidx_t *cidxp; 2940 struct if_rxd_info ri; 2941 int err, budget_left, rx_bytes, rx_pkts; 2942 iflib_fl_t fl; 2943 int lro_enabled; 2944 bool v4_forwarding, v6_forwarding, lro_possible; 2945 uint8_t retval = 0; 2946 2947 /* 2948 * XXX early demux data packets so that if_input processing only handles 2949 * acks in interrupt context 2950 */ 2951 struct mbuf *m, *mh, *mt, *mf; 2952 2953 NET_EPOCH_ASSERT(); 2954 2955 lro_possible = v4_forwarding = v6_forwarding = false; 2956 ifp = ctx->ifc_ifp; 2957 mh = mt = NULL; 2958 MPASS(budget > 0); 2959 rx_pkts = rx_bytes = 0; 2960 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2961 cidxp = &rxq->ifr_cq_cidx; 2962 else 2963 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2964 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2965 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2966 retval |= iflib_fl_refill_all(ctx, fl); 2967 DBG_COUNTER_INC(rx_unavail); 2968 return (retval); 2969 } 2970 2971 /* pfil needs the vnet to be set */ 2972 CURVNET_SET_QUIET(ifp->if_vnet); 2973 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2974 if (__predict_false(!CTX_ACTIVE(ctx))) { 2975 DBG_COUNTER_INC(rx_ctx_inactive); 2976 break; 2977 } 2978 /* 2979 * Reset client set fields to their default values 2980 */ 2981 rxd_info_zero(&ri); 2982 ri.iri_qsidx = rxq->ifr_id; 2983 ri.iri_cidx = *cidxp; 2984 ri.iri_ifp = ifp; 2985 ri.iri_frags = rxq->ifr_frags; 2986 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2987 2988 if (err) 2989 goto err; 2990 rx_pkts += 1; 2991 rx_bytes += ri.iri_len; 2992 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2993 *cidxp = ri.iri_cidx; 2994 /* Update our consumer index */ 2995 /* XXX NB: shurd - check if this is still safe */ 2996 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2997 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2998 /* was this only a completion queue message? */ 2999 if (__predict_false(ri.iri_nfrags == 0)) 3000 continue; 3001 } 3002 MPASS(ri.iri_nfrags != 0); 3003 MPASS(ri.iri_len != 0); 3004 3005 /* will advance the cidx on the corresponding free lists */ 3006 m = iflib_rxd_pkt_get(rxq, &ri); 3007 avail--; 3008 budget_left--; 3009 if (avail == 0 && budget_left) 3010 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 3011 3012 if (__predict_false(m == NULL)) 3013 continue; 3014 3015 /* imm_pkt: -- cxgb */ 3016 if (mh == NULL) 3017 mh = mt = m; 3018 else { 3019 mt->m_nextpkt = m; 3020 mt = m; 3021 } 3022 } 3023 CURVNET_RESTORE(); 3024 /* make sure that we can refill faster than drain */ 3025 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 3026 retval |= iflib_fl_refill_all(ctx, fl); 3027 3028 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 3029 if (lro_enabled) 3030 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 3031 mt = mf = NULL; 3032 while (mh != NULL) { 3033 m = mh; 3034 mh = mh->m_nextpkt; 3035 m->m_nextpkt = NULL; 3036 #ifndef __NO_STRICT_ALIGNMENT 3037 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 3038 continue; 3039 #endif 3040 #if defined(INET6) || defined(INET) 3041 if (lro_enabled) { 3042 if (!lro_possible) { 3043 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 3044 if (lro_possible && mf != NULL) { 3045 ifp->if_input(ifp, mf); 3046 DBG_COUNTER_INC(rx_if_input); 3047 mt = mf = NULL; 3048 } 3049 } 3050 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 3051 (CSUM_L4_CALC|CSUM_L4_VALID)) { 3052 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 3053 continue; 3054 } 3055 } 3056 #endif 3057 if (lro_possible) { 3058 ifp->if_input(ifp, m); 3059 DBG_COUNTER_INC(rx_if_input); 3060 continue; 3061 } 3062 3063 if (mf == NULL) 3064 mf = m; 3065 if (mt != NULL) 3066 mt->m_nextpkt = m; 3067 mt = m; 3068 } 3069 if (mf != NULL) { 3070 ifp->if_input(ifp, mf); 3071 DBG_COUNTER_INC(rx_if_input); 3072 } 3073 3074 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 3075 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 3076 3077 /* 3078 * Flush any outstanding LRO work 3079 */ 3080 #if defined(INET6) || defined(INET) 3081 tcp_lro_flush_all(&rxq->ifr_lc); 3082 #endif 3083 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 3084 retval |= IFLIB_RXEOF_MORE; 3085 return (retval); 3086 err: 3087 STATE_LOCK(ctx); 3088 ctx->ifc_flags |= IFC_DO_RESET; 3089 iflib_admin_intr_deferred(ctx); 3090 STATE_UNLOCK(ctx); 3091 return (0); 3092 } 3093 3094 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 3095 static inline qidx_t 3096 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 3097 { 3098 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3099 qidx_t minthresh = txq->ift_size / 8; 3100 if (in_use > 4*minthresh) 3101 return (notify_count); 3102 if (in_use > 2*minthresh) 3103 return (notify_count >> 1); 3104 if (in_use > minthresh) 3105 return (notify_count >> 3); 3106 return (0); 3107 } 3108 3109 static inline qidx_t 3110 txq_max_rs_deferred(iflib_txq_t txq) 3111 { 3112 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 3113 qidx_t minthresh = txq->ift_size / 8; 3114 if (txq->ift_in_use > 4*minthresh) 3115 return (notify_count); 3116 if (txq->ift_in_use > 2*minthresh) 3117 return (notify_count >> 1); 3118 if (txq->ift_in_use > minthresh) 3119 return (notify_count >> 2); 3120 return (2); 3121 } 3122 3123 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 3124 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 3125 3126 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 3127 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 3128 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 3129 3130 /* forward compatibility for cxgb */ 3131 #define FIRST_QSET(ctx) 0 3132 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 3133 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 3134 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 3135 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 3136 3137 /* XXX we should be setting this to something other than zero */ 3138 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 3139 #define MAX_TX_DESC(ctx) MAX((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 3140 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 3141 3142 static inline bool 3143 iflib_txd_db_check(iflib_txq_t txq, int ring) 3144 { 3145 if_ctx_t ctx = txq->ift_ctx; 3146 qidx_t dbval, max; 3147 3148 max = TXQ_MAX_DB_DEFERRED(txq, txq->ift_in_use); 3149 3150 /* force || threshold exceeded || at the edge of the ring */ 3151 if (ring || (txq->ift_db_pending >= max) || (TXQ_AVAIL(txq) <= MAX_TX_DESC(ctx) + 2)) { 3152 3153 /* 3154 * 'npending' is used if the card's doorbell is in terms of the number of descriptors 3155 * pending flush (BRCM). 'pidx' is used in cases where the card's doorbeel uses the 3156 * producer index explicitly (INTC). 3157 */ 3158 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 3159 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3160 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3161 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 3162 3163 /* 3164 * Absent bugs there are zero packets pending so reset pending counts to zero. 3165 */ 3166 txq->ift_db_pending = txq->ift_npending = 0; 3167 return (true); 3168 } 3169 return (false); 3170 } 3171 3172 #ifdef PKT_DEBUG 3173 static void 3174 print_pkt(if_pkt_info_t pi) 3175 { 3176 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 3177 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 3178 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 3179 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 3180 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 3181 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 3182 } 3183 #endif 3184 3185 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 3186 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 3187 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 3188 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 3189 3190 static int 3191 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 3192 { 3193 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 3194 struct ether_vlan_header *eh; 3195 struct mbuf *m; 3196 3197 m = *mp; 3198 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3199 M_WRITABLE(m) == 0) { 3200 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3201 return (ENOMEM); 3202 } else { 3203 m_freem(*mp); 3204 DBG_COUNTER_INC(tx_frees); 3205 *mp = m; 3206 } 3207 } 3208 3209 /* 3210 * Determine where frame payload starts. 3211 * Jump over vlan headers if already present, 3212 * helpful for QinQ too. 3213 */ 3214 if (__predict_false(m->m_len < sizeof(*eh))) { 3215 txq->ift_pullups++; 3216 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3217 return (ENOMEM); 3218 } 3219 eh = mtod(m, struct ether_vlan_header *); 3220 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3221 pi->ipi_etype = ntohs(eh->evl_proto); 3222 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3223 } else { 3224 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3225 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3226 } 3227 3228 switch (pi->ipi_etype) { 3229 #ifdef INET 3230 case ETHERTYPE_IP: 3231 { 3232 struct mbuf *n; 3233 struct ip *ip = NULL; 3234 struct tcphdr *th = NULL; 3235 int minthlen; 3236 3237 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3238 if (__predict_false(m->m_len < minthlen)) { 3239 /* 3240 * if this code bloat is causing too much of a hit 3241 * move it to a separate function and mark it noinline 3242 */ 3243 if (m->m_len == pi->ipi_ehdrlen) { 3244 n = m->m_next; 3245 MPASS(n); 3246 if (n->m_len >= sizeof(*ip)) { 3247 ip = (struct ip *)n->m_data; 3248 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3249 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3250 } else { 3251 txq->ift_pullups++; 3252 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3253 return (ENOMEM); 3254 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3255 } 3256 } else { 3257 txq->ift_pullups++; 3258 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3259 return (ENOMEM); 3260 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3261 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3262 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3263 } 3264 } else { 3265 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3266 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3267 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3268 } 3269 pi->ipi_ip_hlen = ip->ip_hl << 2; 3270 pi->ipi_ipproto = ip->ip_p; 3271 pi->ipi_flags |= IPI_TX_IPV4; 3272 3273 /* TCP checksum offload may require TCP header length */ 3274 if (IS_TX_OFFLOAD4(pi)) { 3275 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3276 if (__predict_false(th == NULL)) { 3277 txq->ift_pullups++; 3278 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3279 return (ENOMEM); 3280 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3281 } 3282 pi->ipi_tcp_hflags = th->th_flags; 3283 pi->ipi_tcp_hlen = th->th_off << 2; 3284 pi->ipi_tcp_seq = th->th_seq; 3285 } 3286 if (IS_TSO4(pi)) { 3287 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3288 return (ENXIO); 3289 /* 3290 * TSO always requires hardware checksum offload. 3291 */ 3292 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3293 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3294 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3295 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3296 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3297 ip->ip_sum = 0; 3298 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3299 } 3300 } 3301 } 3302 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3303 ip->ip_sum = 0; 3304 3305 break; 3306 } 3307 #endif 3308 #ifdef INET6 3309 case ETHERTYPE_IPV6: 3310 { 3311 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3312 struct tcphdr *th; 3313 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3314 3315 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3316 txq->ift_pullups++; 3317 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3318 return (ENOMEM); 3319 } 3320 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3321 3322 /* XXX-BZ this will go badly in case of ext hdrs. */ 3323 pi->ipi_ipproto = ip6->ip6_nxt; 3324 pi->ipi_flags |= IPI_TX_IPV6; 3325 3326 /* TCP checksum offload may require TCP header length */ 3327 if (IS_TX_OFFLOAD6(pi)) { 3328 if (pi->ipi_ipproto == IPPROTO_TCP) { 3329 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3330 txq->ift_pullups++; 3331 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3332 return (ENOMEM); 3333 } 3334 pi->ipi_tcp_hflags = th->th_flags; 3335 pi->ipi_tcp_hlen = th->th_off << 2; 3336 pi->ipi_tcp_seq = th->th_seq; 3337 } 3338 if (IS_TSO6(pi)) { 3339 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3340 return (ENXIO); 3341 /* 3342 * TSO always requires hardware checksum offload. 3343 */ 3344 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3345 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3346 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3347 } 3348 } 3349 break; 3350 } 3351 #endif 3352 default: 3353 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3354 pi->ipi_ip_hlen = 0; 3355 break; 3356 } 3357 *mp = m; 3358 3359 return (0); 3360 } 3361 3362 /* 3363 * If dodgy hardware rejects the scatter gather chain we've handed it 3364 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3365 * m_defrag'd mbufs 3366 */ 3367 static __noinline struct mbuf * 3368 iflib_remove_mbuf(iflib_txq_t txq) 3369 { 3370 int ntxd, pidx; 3371 struct mbuf *m, **ifsd_m; 3372 3373 ifsd_m = txq->ift_sds.ifsd_m; 3374 ntxd = txq->ift_size; 3375 pidx = txq->ift_pidx & (ntxd - 1); 3376 ifsd_m = txq->ift_sds.ifsd_m; 3377 m = ifsd_m[pidx]; 3378 ifsd_m[pidx] = NULL; 3379 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3380 if (txq->ift_sds.ifsd_tso_map != NULL) 3381 bus_dmamap_unload(txq->ift_tso_buf_tag, 3382 txq->ift_sds.ifsd_tso_map[pidx]); 3383 #if MEMORY_LOGGING 3384 txq->ift_dequeued++; 3385 #endif 3386 return (m); 3387 } 3388 3389 static inline caddr_t 3390 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3391 { 3392 qidx_t size; 3393 int ntxd; 3394 caddr_t start, end, cur, next; 3395 3396 ntxd = txq->ift_size; 3397 size = txq->ift_txd_size[qid]; 3398 start = txq->ift_ifdi[qid].idi_vaddr; 3399 3400 if (__predict_false(size == 0)) 3401 return (start); 3402 cur = start + size*cidx; 3403 end = start + size*ntxd; 3404 next = CACHE_PTR_NEXT(cur); 3405 return (next < end ? next : start); 3406 } 3407 3408 /* 3409 * Pad an mbuf to ensure a minimum ethernet frame size. 3410 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3411 */ 3412 static __noinline int 3413 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3414 { 3415 /* 3416 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3417 * and ARP message is the smallest common payload I can think of 3418 */ 3419 static char pad[18]; /* just zeros */ 3420 int n; 3421 struct mbuf *new_head; 3422 3423 if (!M_WRITABLE(*m_head)) { 3424 new_head = m_dup(*m_head, M_NOWAIT); 3425 if (new_head == NULL) { 3426 m_freem(*m_head); 3427 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3428 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3429 DBG_COUNTER_INC(tx_frees); 3430 return ENOMEM; 3431 } 3432 m_freem(*m_head); 3433 *m_head = new_head; 3434 } 3435 3436 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3437 n > 0; n -= sizeof(pad)) 3438 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3439 break; 3440 3441 if (n > 0) { 3442 m_freem(*m_head); 3443 device_printf(dev, "cannot pad short frame\n"); 3444 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3445 DBG_COUNTER_INC(tx_frees); 3446 return (ENOBUFS); 3447 } 3448 3449 return 0; 3450 } 3451 3452 static int 3453 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3454 { 3455 if_ctx_t ctx; 3456 if_shared_ctx_t sctx; 3457 if_softc_ctx_t scctx; 3458 bus_dma_tag_t buf_tag; 3459 bus_dma_segment_t *segs; 3460 struct mbuf *m_head, **ifsd_m; 3461 void *next_txd; 3462 bus_dmamap_t map; 3463 struct if_pkt_info pi; 3464 int remap = 0; 3465 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3466 3467 ctx = txq->ift_ctx; 3468 sctx = ctx->ifc_sctx; 3469 scctx = &ctx->ifc_softc_ctx; 3470 segs = txq->ift_segs; 3471 ntxd = txq->ift_size; 3472 m_head = *m_headp; 3473 map = NULL; 3474 3475 /* 3476 * If we're doing TSO the next descriptor to clean may be quite far ahead 3477 */ 3478 cidx = txq->ift_cidx; 3479 pidx = txq->ift_pidx; 3480 if (ctx->ifc_flags & IFC_PREFETCH) { 3481 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3482 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3483 next_txd = calc_next_txd(txq, cidx, 0); 3484 prefetch(next_txd); 3485 } 3486 3487 /* prefetch the next cache line of mbuf pointers and flags */ 3488 prefetch(&txq->ift_sds.ifsd_m[next]); 3489 prefetch(&txq->ift_sds.ifsd_map[next]); 3490 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3491 } 3492 map = txq->ift_sds.ifsd_map[pidx]; 3493 ifsd_m = txq->ift_sds.ifsd_m; 3494 3495 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3496 buf_tag = txq->ift_tso_buf_tag; 3497 max_segs = scctx->isc_tx_tso_segments_max; 3498 map = txq->ift_sds.ifsd_tso_map[pidx]; 3499 MPASS(buf_tag != NULL); 3500 MPASS(max_segs > 0); 3501 } else { 3502 buf_tag = txq->ift_buf_tag; 3503 max_segs = scctx->isc_tx_nsegments; 3504 map = txq->ift_sds.ifsd_map[pidx]; 3505 } 3506 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3507 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3508 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3509 if (err) { 3510 DBG_COUNTER_INC(encap_txd_encap_fail); 3511 return err; 3512 } 3513 } 3514 m_head = *m_headp; 3515 3516 pkt_info_zero(&pi); 3517 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3518 pi.ipi_pidx = pidx; 3519 pi.ipi_qsidx = txq->ift_id; 3520 pi.ipi_len = m_head->m_pkthdr.len; 3521 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3522 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3523 3524 /* deliberate bitwise OR to make one condition */ 3525 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3526 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3527 DBG_COUNTER_INC(encap_txd_encap_fail); 3528 return (err); 3529 } 3530 m_head = *m_headp; 3531 } 3532 3533 retry: 3534 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3535 BUS_DMA_NOWAIT); 3536 defrag: 3537 if (__predict_false(err)) { 3538 switch (err) { 3539 case EFBIG: 3540 /* try collapse once and defrag once */ 3541 if (remap == 0) { 3542 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3543 /* try defrag if collapsing fails */ 3544 if (m_head == NULL) 3545 remap++; 3546 } 3547 if (remap == 1) { 3548 txq->ift_mbuf_defrag++; 3549 m_head = m_defrag(*m_headp, M_NOWAIT); 3550 } 3551 /* 3552 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3553 * failed to map an mbuf that was run through m_defrag 3554 */ 3555 MPASS(remap <= 1); 3556 if (__predict_false(m_head == NULL || remap > 1)) 3557 goto defrag_failed; 3558 remap++; 3559 *m_headp = m_head; 3560 goto retry; 3561 break; 3562 case ENOMEM: 3563 txq->ift_no_tx_dma_setup++; 3564 break; 3565 default: 3566 txq->ift_no_tx_dma_setup++; 3567 m_freem(*m_headp); 3568 DBG_COUNTER_INC(tx_frees); 3569 *m_headp = NULL; 3570 break; 3571 } 3572 txq->ift_map_failed++; 3573 DBG_COUNTER_INC(encap_load_mbuf_fail); 3574 DBG_COUNTER_INC(encap_txd_encap_fail); 3575 return (err); 3576 } 3577 ifsd_m[pidx] = m_head; 3578 /* 3579 * XXX assumes a 1 to 1 relationship between segments and 3580 * descriptors - this does not hold true on all drivers, e.g. 3581 * cxgb 3582 */ 3583 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3584 txq->ift_no_desc_avail++; 3585 bus_dmamap_unload(buf_tag, map); 3586 DBG_COUNTER_INC(encap_txq_avail_fail); 3587 DBG_COUNTER_INC(encap_txd_encap_fail); 3588 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3589 GROUPTASK_ENQUEUE(&txq->ift_task); 3590 return (ENOBUFS); 3591 } 3592 /* 3593 * On Intel cards we can greatly reduce the number of TX interrupts 3594 * we see by only setting report status on every Nth descriptor. 3595 * However, this also means that the driver will need to keep track 3596 * of the descriptors that RS was set on to check them for the DD bit. 3597 */ 3598 txq->ift_rs_pending += nsegs + 1; 3599 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3600 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3601 pi.ipi_flags |= IPI_TX_INTR; 3602 txq->ift_rs_pending = 0; 3603 } 3604 3605 pi.ipi_segs = segs; 3606 pi.ipi_nsegs = nsegs; 3607 3608 MPASS(pidx >= 0 && pidx < txq->ift_size); 3609 #ifdef PKT_DEBUG 3610 print_pkt(&pi); 3611 #endif 3612 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3613 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3614 DBG_COUNTER_INC(tx_encap); 3615 MPASS(pi.ipi_new_pidx < txq->ift_size); 3616 3617 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3618 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3619 ndesc += txq->ift_size; 3620 txq->ift_gen = 1; 3621 } 3622 /* 3623 * drivers can need as many as 3624 * two sentinels 3625 */ 3626 MPASS(ndesc <= pi.ipi_nsegs + 2); 3627 MPASS(pi.ipi_new_pidx != pidx); 3628 MPASS(ndesc > 0); 3629 txq->ift_in_use += ndesc; 3630 txq->ift_db_pending += ndesc; 3631 3632 /* 3633 * We update the last software descriptor again here because there may 3634 * be a sentinel and/or there may be more mbufs than segments 3635 */ 3636 txq->ift_pidx = pi.ipi_new_pidx; 3637 txq->ift_npending += pi.ipi_ndescs; 3638 } else { 3639 *m_headp = m_head = iflib_remove_mbuf(txq); 3640 if (err == EFBIG) { 3641 txq->ift_txd_encap_efbig++; 3642 if (remap < 2) { 3643 remap = 1; 3644 goto defrag; 3645 } 3646 } 3647 goto defrag_failed; 3648 } 3649 /* 3650 * err can't possibly be non-zero here, so we don't neet to test it 3651 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3652 */ 3653 return (err); 3654 3655 defrag_failed: 3656 txq->ift_mbuf_defrag_failed++; 3657 txq->ift_map_failed++; 3658 m_freem(*m_headp); 3659 DBG_COUNTER_INC(tx_frees); 3660 *m_headp = NULL; 3661 DBG_COUNTER_INC(encap_txd_encap_fail); 3662 return (ENOMEM); 3663 } 3664 3665 static void 3666 iflib_tx_desc_free(iflib_txq_t txq, int n) 3667 { 3668 uint32_t qsize, cidx, mask, gen; 3669 struct mbuf *m, **ifsd_m; 3670 bool do_prefetch; 3671 3672 cidx = txq->ift_cidx; 3673 gen = txq->ift_gen; 3674 qsize = txq->ift_size; 3675 mask = qsize-1; 3676 ifsd_m = txq->ift_sds.ifsd_m; 3677 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3678 3679 while (n-- > 0) { 3680 if (do_prefetch) { 3681 prefetch(ifsd_m[(cidx + 3) & mask]); 3682 prefetch(ifsd_m[(cidx + 4) & mask]); 3683 } 3684 if ((m = ifsd_m[cidx]) != NULL) { 3685 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3686 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3687 bus_dmamap_sync(txq->ift_tso_buf_tag, 3688 txq->ift_sds.ifsd_tso_map[cidx], 3689 BUS_DMASYNC_POSTWRITE); 3690 bus_dmamap_unload(txq->ift_tso_buf_tag, 3691 txq->ift_sds.ifsd_tso_map[cidx]); 3692 } else { 3693 bus_dmamap_sync(txq->ift_buf_tag, 3694 txq->ift_sds.ifsd_map[cidx], 3695 BUS_DMASYNC_POSTWRITE); 3696 bus_dmamap_unload(txq->ift_buf_tag, 3697 txq->ift_sds.ifsd_map[cidx]); 3698 } 3699 /* XXX we don't support any drivers that batch packets yet */ 3700 MPASS(m->m_nextpkt == NULL); 3701 m_freem(m); 3702 ifsd_m[cidx] = NULL; 3703 #if MEMORY_LOGGING 3704 txq->ift_dequeued++; 3705 #endif 3706 DBG_COUNTER_INC(tx_frees); 3707 } 3708 if (__predict_false(++cidx == qsize)) { 3709 cidx = 0; 3710 gen = 0; 3711 } 3712 } 3713 txq->ift_cidx = cidx; 3714 txq->ift_gen = gen; 3715 } 3716 3717 static __inline int 3718 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3719 { 3720 int reclaim; 3721 if_ctx_t ctx = txq->ift_ctx; 3722 3723 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3724 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3725 3726 /* 3727 * Need a rate-limiting check so that this isn't called every time 3728 */ 3729 iflib_tx_credits_update(ctx, txq); 3730 reclaim = DESC_RECLAIMABLE(txq); 3731 3732 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3733 #ifdef INVARIANTS 3734 if (iflib_verbose_debug) { 3735 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3736 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3737 reclaim, thresh); 3738 } 3739 #endif 3740 return (0); 3741 } 3742 iflib_tx_desc_free(txq, reclaim); 3743 txq->ift_cleaned += reclaim; 3744 txq->ift_in_use -= reclaim; 3745 3746 return (reclaim); 3747 } 3748 3749 static struct mbuf ** 3750 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3751 { 3752 int next, size; 3753 struct mbuf **items; 3754 3755 size = r->size; 3756 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3757 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3758 3759 prefetch(items[(cidx + offset) & (size-1)]); 3760 if (remaining > 1) { 3761 prefetch2cachelines(&items[next]); 3762 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3763 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3764 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3765 } 3766 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3767 } 3768 3769 static void 3770 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3771 { 3772 3773 ifmp_ring_check_drainage(txq->ift_br, budget); 3774 } 3775 3776 static uint32_t 3777 iflib_txq_can_drain(struct ifmp_ring *r) 3778 { 3779 iflib_txq_t txq = r->cookie; 3780 if_ctx_t ctx = txq->ift_ctx; 3781 3782 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3783 return (1); 3784 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3785 BUS_DMASYNC_POSTREAD); 3786 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3787 false)); 3788 } 3789 3790 static uint32_t 3791 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3792 { 3793 iflib_txq_t txq = r->cookie; 3794 if_ctx_t ctx = txq->ift_ctx; 3795 if_t ifp = ctx->ifc_ifp; 3796 struct mbuf *m, **mp; 3797 int avail, bytes_sent, skipped, count, err, i; 3798 int mcast_sent, pkt_sent, reclaimed; 3799 bool do_prefetch, rang, ring; 3800 3801 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3802 !LINK_ACTIVE(ctx))) { 3803 DBG_COUNTER_INC(txq_drain_notready); 3804 return (0); 3805 } 3806 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3807 rang = iflib_txd_db_check(txq, reclaimed && txq->ift_db_pending); 3808 avail = IDXDIFF(pidx, cidx, r->size); 3809 3810 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3811 /* 3812 * The driver is unloading so we need to free all pending packets. 3813 */ 3814 DBG_COUNTER_INC(txq_drain_flushing); 3815 for (i = 0; i < avail; i++) { 3816 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3817 m_freem(r->items[(cidx + i) & (r->size-1)]); 3818 r->items[(cidx + i) & (r->size-1)] = NULL; 3819 } 3820 return (avail); 3821 } 3822 3823 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3824 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3825 CALLOUT_LOCK(txq); 3826 callout_stop(&txq->ift_timer); 3827 CALLOUT_UNLOCK(txq); 3828 DBG_COUNTER_INC(txq_drain_oactive); 3829 return (0); 3830 } 3831 3832 /* 3833 * If we've reclaimed any packets this queue cannot be hung. 3834 */ 3835 if (reclaimed) 3836 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3837 skipped = mcast_sent = bytes_sent = pkt_sent = 0; 3838 count = MIN(avail, TX_BATCH_SIZE); 3839 #ifdef INVARIANTS 3840 if (iflib_verbose_debug) 3841 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3842 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3843 #endif 3844 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3845 err = 0; 3846 for (i = 0; i < count && TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx) + 2; i++) { 3847 int rem = do_prefetch ? count - i : 0; 3848 3849 mp = _ring_peek_one(r, cidx, i, rem); 3850 MPASS(mp != NULL && *mp != NULL); 3851 3852 /* 3853 * Completion interrupts will use the address of the txq 3854 * as a sentinel to enqueue _something_ in order to acquire 3855 * the lock on the mp_ring (there's no direct lock call). 3856 * We obviously whave to check for these sentinel cases 3857 * and skip them. 3858 */ 3859 if (__predict_false(*mp == (struct mbuf *)txq)) { 3860 skipped++; 3861 continue; 3862 } 3863 err = iflib_encap(txq, mp); 3864 if (__predict_false(err)) { 3865 /* no room - bail out */ 3866 if (err == ENOBUFS) 3867 break; 3868 skipped++; 3869 /* we can't send this packet - skip it */ 3870 continue; 3871 } 3872 pkt_sent++; 3873 m = *mp; 3874 DBG_COUNTER_INC(tx_sent); 3875 bytes_sent += m->m_pkthdr.len; 3876 mcast_sent += !!(m->m_flags & M_MCAST); 3877 3878 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3879 break; 3880 ETHER_BPF_MTAP(ifp, m); 3881 rang = iflib_txd_db_check(txq, false); 3882 } 3883 3884 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3885 ring = rang ? false : (iflib_min_tx_latency | err); 3886 iflib_txd_db_check(txq, ring); 3887 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3888 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3889 if (mcast_sent) 3890 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3891 #ifdef INVARIANTS 3892 if (iflib_verbose_debug) 3893 printf("consumed=%d\n", skipped + pkt_sent); 3894 #endif 3895 return (skipped + pkt_sent); 3896 } 3897 3898 static uint32_t 3899 iflib_txq_drain_always(struct ifmp_ring *r) 3900 { 3901 return (1); 3902 } 3903 3904 static uint32_t 3905 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3906 { 3907 int i, avail; 3908 struct mbuf **mp; 3909 iflib_txq_t txq; 3910 3911 txq = r->cookie; 3912 3913 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3914 CALLOUT_LOCK(txq); 3915 callout_stop(&txq->ift_timer); 3916 CALLOUT_UNLOCK(txq); 3917 3918 avail = IDXDIFF(pidx, cidx, r->size); 3919 for (i = 0; i < avail; i++) { 3920 mp = _ring_peek_one(r, cidx, i, avail - i); 3921 if (__predict_false(*mp == (struct mbuf *)txq)) 3922 continue; 3923 m_freem(*mp); 3924 DBG_COUNTER_INC(tx_frees); 3925 } 3926 MPASS(ifmp_ring_is_stalled(r) == 0); 3927 return (avail); 3928 } 3929 3930 static void 3931 iflib_ifmp_purge(iflib_txq_t txq) 3932 { 3933 struct ifmp_ring *r; 3934 3935 r = txq->ift_br; 3936 r->drain = iflib_txq_drain_free; 3937 r->can_drain = iflib_txq_drain_always; 3938 3939 ifmp_ring_check_drainage(r, r->size); 3940 3941 r->drain = iflib_txq_drain; 3942 r->can_drain = iflib_txq_can_drain; 3943 } 3944 3945 static void 3946 _task_fn_tx(void *context) 3947 { 3948 iflib_txq_t txq = context; 3949 if_ctx_t ctx = txq->ift_ctx; 3950 if_t ifp = ctx->ifc_ifp; 3951 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3952 3953 #ifdef IFLIB_DIAGNOSTICS 3954 txq->ift_cpu_exec_count[curcpu]++; 3955 #endif 3956 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 3957 return; 3958 #ifdef DEV_NETMAP 3959 if ((if_getcapenable(ifp) & IFCAP_NETMAP) && 3960 netmap_tx_irq(ifp, txq->ift_id)) 3961 goto skip_ifmp; 3962 #endif 3963 #ifdef ALTQ 3964 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3965 iflib_altq_if_start(ifp); 3966 #endif 3967 if (txq->ift_db_pending) 3968 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3969 else if (!abdicate) 3970 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3971 /* 3972 * When abdicating, we always need to check drainage, not just when we don't enqueue 3973 */ 3974 if (abdicate) 3975 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3976 #ifdef DEV_NETMAP 3977 skip_ifmp: 3978 #endif 3979 if (ctx->ifc_flags & IFC_LEGACY) 3980 IFDI_INTR_ENABLE(ctx); 3981 else 3982 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3983 } 3984 3985 static void 3986 _task_fn_rx(void *context) 3987 { 3988 iflib_rxq_t rxq = context; 3989 if_ctx_t ctx = rxq->ifr_ctx; 3990 uint8_t more; 3991 uint16_t budget; 3992 #ifdef DEV_NETMAP 3993 u_int work = 0; 3994 int nmirq; 3995 #endif 3996 3997 #ifdef IFLIB_DIAGNOSTICS 3998 rxq->ifr_cpu_exec_count[curcpu]++; 3999 #endif 4000 DBG_COUNTER_INC(task_fn_rxs); 4001 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4002 return; 4003 #ifdef DEV_NETMAP 4004 nmirq = netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work); 4005 if (nmirq != NM_IRQ_PASS) { 4006 more = (nmirq == NM_IRQ_RESCHED) ? IFLIB_RXEOF_MORE : 0; 4007 goto skip_rxeof; 4008 } 4009 #endif 4010 budget = ctx->ifc_sysctl_rx_budget; 4011 if (budget == 0) 4012 budget = 16; /* XXX */ 4013 more = iflib_rxeof(rxq, budget); 4014 #ifdef DEV_NETMAP 4015 skip_rxeof: 4016 #endif 4017 if ((more & IFLIB_RXEOF_MORE) == 0) { 4018 if (ctx->ifc_flags & IFC_LEGACY) 4019 IFDI_INTR_ENABLE(ctx); 4020 else 4021 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 4022 DBG_COUNTER_INC(rx_intr_enables); 4023 } 4024 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 4025 return; 4026 4027 if (more & IFLIB_RXEOF_MORE) 4028 GROUPTASK_ENQUEUE(&rxq->ifr_task); 4029 else if (more & IFLIB_RXEOF_EMPTY) 4030 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 4031 } 4032 4033 static void 4034 _task_fn_admin(void *context) 4035 { 4036 if_ctx_t ctx = context; 4037 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 4038 iflib_txq_t txq; 4039 int i; 4040 bool oactive, running, do_reset, do_watchdog, in_detach; 4041 4042 STATE_LOCK(ctx); 4043 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 4044 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 4045 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 4046 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 4047 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 4048 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 4049 STATE_UNLOCK(ctx); 4050 4051 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4052 return; 4053 if (in_detach) 4054 return; 4055 4056 CTX_LOCK(ctx); 4057 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4058 CALLOUT_LOCK(txq); 4059 callout_stop(&txq->ift_timer); 4060 CALLOUT_UNLOCK(txq); 4061 } 4062 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_ADMINCQ) 4063 IFDI_ADMIN_COMPLETION_HANDLE(ctx); 4064 if (do_watchdog) { 4065 ctx->ifc_watchdog_events++; 4066 IFDI_WATCHDOG_RESET(ctx); 4067 } 4068 IFDI_UPDATE_ADMIN_STATUS(ctx); 4069 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 4070 callout_reset_on(&txq->ift_timer, iflib_timer_default, iflib_timer, txq, 4071 txq->ift_timer.c_cpu); 4072 } 4073 IFDI_LINK_INTR_ENABLE(ctx); 4074 if (do_reset) 4075 iflib_if_init_locked(ctx); 4076 CTX_UNLOCK(ctx); 4077 4078 if (LINK_ACTIVE(ctx) == 0) 4079 return; 4080 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 4081 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 4082 } 4083 4084 static void 4085 _task_fn_iov(void *context) 4086 { 4087 if_ctx_t ctx = context; 4088 4089 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 4090 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 4091 return; 4092 4093 CTX_LOCK(ctx); 4094 IFDI_VFLR_HANDLE(ctx); 4095 CTX_UNLOCK(ctx); 4096 } 4097 4098 static int 4099 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4100 { 4101 int err; 4102 if_int_delay_info_t info; 4103 if_ctx_t ctx; 4104 4105 info = (if_int_delay_info_t)arg1; 4106 ctx = info->iidi_ctx; 4107 info->iidi_req = req; 4108 info->iidi_oidp = oidp; 4109 CTX_LOCK(ctx); 4110 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 4111 CTX_UNLOCK(ctx); 4112 return (err); 4113 } 4114 4115 /********************************************************************* 4116 * 4117 * IFNET FUNCTIONS 4118 * 4119 **********************************************************************/ 4120 4121 static void 4122 iflib_if_init_locked(if_ctx_t ctx) 4123 { 4124 iflib_stop(ctx); 4125 iflib_init_locked(ctx); 4126 } 4127 4128 static void 4129 iflib_if_init(void *arg) 4130 { 4131 if_ctx_t ctx = arg; 4132 4133 CTX_LOCK(ctx); 4134 iflib_if_init_locked(ctx); 4135 CTX_UNLOCK(ctx); 4136 } 4137 4138 static int 4139 iflib_if_transmit(if_t ifp, struct mbuf *m) 4140 { 4141 if_ctx_t ctx = if_getsoftc(ifp); 4142 4143 iflib_txq_t txq; 4144 int err, qidx; 4145 int abdicate = ctx->ifc_sysctl_tx_abdicate; 4146 4147 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 4148 DBG_COUNTER_INC(tx_frees); 4149 m_freem(m); 4150 return (ENETDOWN); 4151 } 4152 4153 MPASS(m->m_nextpkt == NULL); 4154 /* ALTQ-enabled interfaces always use queue 0. */ 4155 qidx = 0; 4156 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 4157 qidx = QIDX(ctx, m); 4158 /* 4159 * XXX calculate buf_ring based on flowid (divvy up bits?) 4160 */ 4161 txq = &ctx->ifc_txqs[qidx]; 4162 4163 #ifdef DRIVER_BACKPRESSURE 4164 if (txq->ift_closed) { 4165 while (m != NULL) { 4166 next = m->m_nextpkt; 4167 m->m_nextpkt = NULL; 4168 m_freem(m); 4169 DBG_COUNTER_INC(tx_frees); 4170 m = next; 4171 } 4172 return (ENOBUFS); 4173 } 4174 #endif 4175 #ifdef notyet 4176 qidx = count = 0; 4177 mp = marr; 4178 next = m; 4179 do { 4180 count++; 4181 next = next->m_nextpkt; 4182 } while (next != NULL); 4183 4184 if (count > nitems(marr)) 4185 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 4186 /* XXX check nextpkt */ 4187 m_freem(m); 4188 /* XXX simplify for now */ 4189 DBG_COUNTER_INC(tx_frees); 4190 return (ENOBUFS); 4191 } 4192 for (next = m, i = 0; next != NULL; i++) { 4193 mp[i] = next; 4194 next = next->m_nextpkt; 4195 mp[i]->m_nextpkt = NULL; 4196 } 4197 #endif 4198 DBG_COUNTER_INC(tx_seen); 4199 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4200 4201 if (abdicate) 4202 GROUPTASK_ENQUEUE(&txq->ift_task); 4203 if (err) { 4204 if (!abdicate) 4205 GROUPTASK_ENQUEUE(&txq->ift_task); 4206 /* support forthcoming later */ 4207 #ifdef DRIVER_BACKPRESSURE 4208 txq->ift_closed = TRUE; 4209 #endif 4210 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4211 m_freem(m); 4212 DBG_COUNTER_INC(tx_frees); 4213 } 4214 4215 return (err); 4216 } 4217 4218 #ifdef ALTQ 4219 /* 4220 * The overall approach to integrating iflib with ALTQ is to continue to use 4221 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4222 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4223 * is redundant/unnecessary, but doing so minimizes the amount of 4224 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4225 * redundantly queueing to an intermediate mp_ring is swamped by the 4226 * performance limitations inherent in using ALTQ. 4227 * 4228 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4229 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4230 * given interface. If ALTQ is enabled for an interface, then all 4231 * transmitted packets for that interface will be submitted to the ALTQ 4232 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4233 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4234 * update stats that the iflib machinery handles, and which is sensitve to 4235 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4236 * will be installed as the start routine for use by ALTQ facilities that 4237 * need to trigger queue drains on a scheduled basis. 4238 * 4239 */ 4240 static void 4241 iflib_altq_if_start(if_t ifp) 4242 { 4243 struct ifaltq *ifq = &ifp->if_snd; 4244 struct mbuf *m; 4245 4246 IFQ_LOCK(ifq); 4247 IFQ_DEQUEUE_NOLOCK(ifq, m); 4248 while (m != NULL) { 4249 iflib_if_transmit(ifp, m); 4250 IFQ_DEQUEUE_NOLOCK(ifq, m); 4251 } 4252 IFQ_UNLOCK(ifq); 4253 } 4254 4255 static int 4256 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4257 { 4258 int err; 4259 4260 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4261 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4262 if (err == 0) 4263 iflib_altq_if_start(ifp); 4264 } else 4265 err = iflib_if_transmit(ifp, m); 4266 4267 return (err); 4268 } 4269 #endif /* ALTQ */ 4270 4271 static void 4272 iflib_if_qflush(if_t ifp) 4273 { 4274 if_ctx_t ctx = if_getsoftc(ifp); 4275 iflib_txq_t txq = ctx->ifc_txqs; 4276 int i; 4277 4278 STATE_LOCK(ctx); 4279 ctx->ifc_flags |= IFC_QFLUSH; 4280 STATE_UNLOCK(ctx); 4281 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4282 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4283 iflib_txq_check_drain(txq, 0); 4284 STATE_LOCK(ctx); 4285 ctx->ifc_flags &= ~IFC_QFLUSH; 4286 STATE_UNLOCK(ctx); 4287 4288 /* 4289 * When ALTQ is enabled, this will also take care of purging the 4290 * ALTQ queue(s). 4291 */ 4292 if_qflush(ifp); 4293 } 4294 4295 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4296 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4297 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4298 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_MEXTPG) 4299 4300 static int 4301 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4302 { 4303 if_ctx_t ctx = if_getsoftc(ifp); 4304 struct ifreq *ifr = (struct ifreq *)data; 4305 #if defined(INET) || defined(INET6) 4306 struct ifaddr *ifa = (struct ifaddr *)data; 4307 #endif 4308 bool avoid_reset = false; 4309 int err = 0, reinit = 0, bits; 4310 4311 switch (command) { 4312 case SIOCSIFADDR: 4313 #ifdef INET 4314 if (ifa->ifa_addr->sa_family == AF_INET) 4315 avoid_reset = true; 4316 #endif 4317 #ifdef INET6 4318 if (ifa->ifa_addr->sa_family == AF_INET6) 4319 avoid_reset = true; 4320 #endif 4321 /* 4322 ** Calling init results in link renegotiation, 4323 ** so we avoid doing it when possible. 4324 */ 4325 if (avoid_reset) { 4326 if_setflagbits(ifp, IFF_UP,0); 4327 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4328 reinit = 1; 4329 #ifdef INET 4330 if (!(if_getflags(ifp) & IFF_NOARP)) 4331 arp_ifinit(ifp, ifa); 4332 #endif 4333 } else 4334 err = ether_ioctl(ifp, command, data); 4335 break; 4336 case SIOCSIFMTU: 4337 CTX_LOCK(ctx); 4338 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4339 CTX_UNLOCK(ctx); 4340 break; 4341 } 4342 bits = if_getdrvflags(ifp); 4343 /* stop the driver and free any clusters before proceeding */ 4344 iflib_stop(ctx); 4345 4346 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4347 STATE_LOCK(ctx); 4348 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4349 ctx->ifc_flags |= IFC_MULTISEG; 4350 else 4351 ctx->ifc_flags &= ~IFC_MULTISEG; 4352 STATE_UNLOCK(ctx); 4353 err = if_setmtu(ifp, ifr->ifr_mtu); 4354 } 4355 iflib_init_locked(ctx); 4356 STATE_LOCK(ctx); 4357 if_setdrvflags(ifp, bits); 4358 STATE_UNLOCK(ctx); 4359 CTX_UNLOCK(ctx); 4360 break; 4361 case SIOCSIFFLAGS: 4362 CTX_LOCK(ctx); 4363 if (if_getflags(ifp) & IFF_UP) { 4364 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4365 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4366 (IFF_PROMISC | IFF_ALLMULTI)) { 4367 CTX_UNLOCK(ctx); 4368 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4369 CTX_LOCK(ctx); 4370 } 4371 } else 4372 reinit = 1; 4373 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4374 iflib_stop(ctx); 4375 } 4376 ctx->ifc_if_flags = if_getflags(ifp); 4377 CTX_UNLOCK(ctx); 4378 break; 4379 case SIOCADDMULTI: 4380 case SIOCDELMULTI: 4381 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4382 CTX_LOCK(ctx); 4383 IFDI_INTR_DISABLE(ctx); 4384 IFDI_MULTI_SET(ctx); 4385 IFDI_INTR_ENABLE(ctx); 4386 CTX_UNLOCK(ctx); 4387 } 4388 break; 4389 case SIOCSIFMEDIA: 4390 CTX_LOCK(ctx); 4391 IFDI_MEDIA_SET(ctx); 4392 CTX_UNLOCK(ctx); 4393 /* FALLTHROUGH */ 4394 case SIOCGIFMEDIA: 4395 case SIOCGIFXMEDIA: 4396 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4397 break; 4398 case SIOCGI2C: 4399 { 4400 struct ifi2creq i2c; 4401 4402 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4403 if (err != 0) 4404 break; 4405 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4406 err = EINVAL; 4407 break; 4408 } 4409 if (i2c.len > sizeof(i2c.data)) { 4410 err = EINVAL; 4411 break; 4412 } 4413 4414 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4415 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4416 sizeof(i2c)); 4417 break; 4418 } 4419 case SIOCSIFCAP: 4420 { 4421 int mask, setmask, oldmask; 4422 4423 oldmask = if_getcapenable(ifp); 4424 mask = ifr->ifr_reqcap ^ oldmask; 4425 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_MEXTPG; 4426 setmask = 0; 4427 #ifdef TCP_OFFLOAD 4428 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4429 #endif 4430 setmask |= (mask & IFCAP_FLAGS); 4431 setmask |= (mask & IFCAP_WOL); 4432 4433 /* 4434 * If any RX csum has changed, change all the ones that 4435 * are supported by the driver. 4436 */ 4437 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4438 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4439 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4440 } 4441 4442 /* 4443 * want to ensure that traffic has stopped before we change any of the flags 4444 */ 4445 if (setmask) { 4446 CTX_LOCK(ctx); 4447 bits = if_getdrvflags(ifp); 4448 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4449 iflib_stop(ctx); 4450 STATE_LOCK(ctx); 4451 if_togglecapenable(ifp, setmask); 4452 STATE_UNLOCK(ctx); 4453 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4454 iflib_init_locked(ctx); 4455 STATE_LOCK(ctx); 4456 if_setdrvflags(ifp, bits); 4457 STATE_UNLOCK(ctx); 4458 CTX_UNLOCK(ctx); 4459 } 4460 if_vlancap(ifp); 4461 break; 4462 } 4463 case SIOCGPRIVATE_0: 4464 case SIOCSDRVSPEC: 4465 case SIOCGDRVSPEC: 4466 CTX_LOCK(ctx); 4467 err = IFDI_PRIV_IOCTL(ctx, command, data); 4468 CTX_UNLOCK(ctx); 4469 break; 4470 default: 4471 err = ether_ioctl(ifp, command, data); 4472 break; 4473 } 4474 if (reinit) 4475 iflib_if_init(ctx); 4476 return (err); 4477 } 4478 4479 static uint64_t 4480 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4481 { 4482 if_ctx_t ctx = if_getsoftc(ifp); 4483 4484 return (IFDI_GET_COUNTER(ctx, cnt)); 4485 } 4486 4487 /********************************************************************* 4488 * 4489 * OTHER FUNCTIONS EXPORTED TO THE STACK 4490 * 4491 **********************************************************************/ 4492 4493 static void 4494 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4495 { 4496 if_ctx_t ctx = if_getsoftc(ifp); 4497 4498 if ((void *)ctx != arg) 4499 return; 4500 4501 if ((vtag == 0) || (vtag > 4095)) 4502 return; 4503 4504 if (iflib_in_detach(ctx)) 4505 return; 4506 4507 CTX_LOCK(ctx); 4508 /* Driver may need all untagged packets to be flushed */ 4509 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4510 iflib_stop(ctx); 4511 IFDI_VLAN_REGISTER(ctx, vtag); 4512 /* Re-init to load the changes, if required */ 4513 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4514 iflib_init_locked(ctx); 4515 CTX_UNLOCK(ctx); 4516 } 4517 4518 static void 4519 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4520 { 4521 if_ctx_t ctx = if_getsoftc(ifp); 4522 4523 if ((void *)ctx != arg) 4524 return; 4525 4526 if ((vtag == 0) || (vtag > 4095)) 4527 return; 4528 4529 CTX_LOCK(ctx); 4530 /* Driver may need all tagged packets to be flushed */ 4531 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4532 iflib_stop(ctx); 4533 IFDI_VLAN_UNREGISTER(ctx, vtag); 4534 /* Re-init to load the changes, if required */ 4535 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4536 iflib_init_locked(ctx); 4537 CTX_UNLOCK(ctx); 4538 } 4539 4540 static void 4541 iflib_led_func(void *arg, int onoff) 4542 { 4543 if_ctx_t ctx = arg; 4544 4545 CTX_LOCK(ctx); 4546 IFDI_LED_FUNC(ctx, onoff); 4547 CTX_UNLOCK(ctx); 4548 } 4549 4550 /********************************************************************* 4551 * 4552 * BUS FUNCTION DEFINITIONS 4553 * 4554 **********************************************************************/ 4555 4556 int 4557 iflib_device_probe(device_t dev) 4558 { 4559 const pci_vendor_info_t *ent; 4560 if_shared_ctx_t sctx; 4561 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4562 uint16_t pci_vendor_id; 4563 4564 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4565 return (ENOTSUP); 4566 4567 pci_vendor_id = pci_get_vendor(dev); 4568 pci_device_id = pci_get_device(dev); 4569 pci_subvendor_id = pci_get_subvendor(dev); 4570 pci_subdevice_id = pci_get_subdevice(dev); 4571 pci_rev_id = pci_get_revid(dev); 4572 if (sctx->isc_parse_devinfo != NULL) 4573 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4574 4575 ent = sctx->isc_vendor_info; 4576 while (ent->pvi_vendor_id != 0) { 4577 if (pci_vendor_id != ent->pvi_vendor_id) { 4578 ent++; 4579 continue; 4580 } 4581 if ((pci_device_id == ent->pvi_device_id) && 4582 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4583 (ent->pvi_subvendor_id == 0)) && 4584 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4585 (ent->pvi_subdevice_id == 0)) && 4586 ((pci_rev_id == ent->pvi_rev_id) || 4587 (ent->pvi_rev_id == 0))) { 4588 device_set_desc_copy(dev, ent->pvi_name); 4589 /* this needs to be changed to zero if the bus probing code 4590 * ever stops re-probing on best match because the sctx 4591 * may have its values over written by register calls 4592 * in subsequent probes 4593 */ 4594 return (BUS_PROBE_DEFAULT); 4595 } 4596 ent++; 4597 } 4598 return (ENXIO); 4599 } 4600 4601 int 4602 iflib_device_probe_vendor(device_t dev) 4603 { 4604 int probe; 4605 4606 probe = iflib_device_probe(dev); 4607 if (probe == BUS_PROBE_DEFAULT) 4608 return (BUS_PROBE_VENDOR); 4609 else 4610 return (probe); 4611 } 4612 4613 static void 4614 iflib_reset_qvalues(if_ctx_t ctx) 4615 { 4616 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4617 if_shared_ctx_t sctx = ctx->ifc_sctx; 4618 device_t dev = ctx->ifc_dev; 4619 int i; 4620 4621 if (ctx->ifc_sysctl_ntxqs != 0) 4622 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4623 if (ctx->ifc_sysctl_nrxqs != 0) 4624 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4625 4626 for (i = 0; i < sctx->isc_ntxqs; i++) { 4627 if (ctx->ifc_sysctl_ntxds[i] != 0) 4628 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4629 else 4630 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4631 } 4632 4633 for (i = 0; i < sctx->isc_nrxqs; i++) { 4634 if (ctx->ifc_sysctl_nrxds[i] != 0) 4635 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4636 else 4637 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4638 } 4639 4640 for (i = 0; i < sctx->isc_nrxqs; i++) { 4641 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4642 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4643 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4644 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4645 } 4646 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4647 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4648 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4649 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4650 } 4651 if (!powerof2(scctx->isc_nrxd[i])) { 4652 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4653 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4654 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4655 } 4656 } 4657 4658 for (i = 0; i < sctx->isc_ntxqs; i++) { 4659 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4660 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4661 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4662 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4663 } 4664 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4665 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4666 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4667 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4668 } 4669 if (!powerof2(scctx->isc_ntxd[i])) { 4670 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4671 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4672 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4673 } 4674 } 4675 } 4676 4677 static void 4678 iflib_add_pfil(if_ctx_t ctx) 4679 { 4680 struct pfil_head *pfil; 4681 struct pfil_head_args pa; 4682 iflib_rxq_t rxq; 4683 int i; 4684 4685 pa.pa_version = PFIL_VERSION; 4686 pa.pa_flags = PFIL_IN; 4687 pa.pa_type = PFIL_TYPE_ETHERNET; 4688 pa.pa_headname = ctx->ifc_ifp->if_xname; 4689 pfil = pfil_head_register(&pa); 4690 4691 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4692 rxq->pfil = pfil; 4693 } 4694 } 4695 4696 static void 4697 iflib_rem_pfil(if_ctx_t ctx) 4698 { 4699 struct pfil_head *pfil; 4700 iflib_rxq_t rxq; 4701 int i; 4702 4703 rxq = ctx->ifc_rxqs; 4704 pfil = rxq->pfil; 4705 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4706 rxq->pfil = NULL; 4707 } 4708 pfil_head_unregister(pfil); 4709 } 4710 4711 4712 /* 4713 * Advance forward by n members of the cpuset ctx->ifc_cpus starting from 4714 * cpuid and wrapping as necessary. 4715 */ 4716 static unsigned int 4717 cpuid_advance(if_ctx_t ctx, unsigned int cpuid, unsigned int n) 4718 { 4719 unsigned int first_valid; 4720 unsigned int last_valid; 4721 4722 /* cpuid should always be in the valid set */ 4723 MPASS(CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4724 4725 /* valid set should never be empty */ 4726 MPASS(!CPU_EMPTY(&ctx->ifc_cpus)); 4727 4728 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4729 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4730 n = n % CPU_COUNT(&ctx->ifc_cpus); 4731 while (n > 0) { 4732 do { 4733 cpuid++; 4734 if (cpuid > last_valid) 4735 cpuid = first_valid; 4736 } while (!CPU_ISSET(cpuid, &ctx->ifc_cpus)); 4737 n--; 4738 } 4739 4740 return (cpuid); 4741 } 4742 4743 #if defined(SMP) && defined(SCHED_ULE) 4744 extern struct cpu_group *cpu_top; /* CPU topology */ 4745 4746 static int 4747 find_child_with_core(int cpu, struct cpu_group *grp) 4748 { 4749 int i; 4750 4751 if (grp->cg_children == 0) 4752 return -1; 4753 4754 MPASS(grp->cg_child); 4755 for (i = 0; i < grp->cg_children; i++) { 4756 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 4757 return i; 4758 } 4759 4760 return -1; 4761 } 4762 4763 4764 /* 4765 * Find an L2 neighbor of the given CPU or return -1 if none found. This 4766 * does not distinguish among multiple L2 neighbors if the given CPU has 4767 * more than one (it will always return the same result in that case). 4768 */ 4769 static int 4770 find_l2_neighbor(int cpu) 4771 { 4772 struct cpu_group *grp; 4773 int i; 4774 4775 grp = cpu_top; 4776 if (grp == NULL) 4777 return -1; 4778 4779 /* 4780 * Find the smallest CPU group that contains the given core. 4781 */ 4782 i = 0; 4783 while ((i = find_child_with_core(cpu, grp)) != -1) { 4784 /* 4785 * If the smallest group containing the given CPU has less 4786 * than two members, we conclude the given CPU has no 4787 * L2 neighbor. 4788 */ 4789 if (grp->cg_child[i].cg_count <= 1) 4790 return (-1); 4791 grp = &grp->cg_child[i]; 4792 } 4793 4794 /* Must share L2. */ 4795 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 4796 return -1; 4797 4798 /* 4799 * Select the first member of the set that isn't the reference 4800 * CPU, which at this point is guaranteed to exist. 4801 */ 4802 for (i = 0; i < CPU_SETSIZE; i++) { 4803 if (CPU_ISSET(i, &grp->cg_mask) && i != cpu) 4804 return (i); 4805 } 4806 4807 /* Should never be reached */ 4808 return (-1); 4809 } 4810 4811 #else 4812 static int 4813 find_l2_neighbor(int cpu) 4814 { 4815 4816 return (-1); 4817 } 4818 #endif 4819 4820 /* 4821 * CPU mapping behaviors 4822 * --------------------- 4823 * 'separate txrx' refers to the separate_txrx sysctl 4824 * 'use logical' refers to the use_logical_cores sysctl 4825 * 'INTR CPUS' indicates whether bus_get_cpus(INTR_CPUS) succeeded 4826 * 4827 * separate use INTR 4828 * txrx logical CPUS result 4829 * ---------- --------- ------ ------------------------------------------------ 4830 * - - X RX and TX queues mapped to consecutive physical 4831 * cores with RX/TX pairs on same core and excess 4832 * of either following 4833 * - X X RX and TX queues mapped to consecutive cores 4834 * of any type with RX/TX pairs on same core and 4835 * excess of either following 4836 * X - X RX and TX queues mapped to consecutive physical 4837 * cores; all RX then all TX 4838 * X X X RX queues mapped to consecutive physical cores 4839 * first, then TX queues mapped to L2 neighbor of 4840 * the corresponding RX queue if one exists, 4841 * otherwise to consecutive physical cores 4842 * - n/a - RX and TX queues mapped to consecutive cores of 4843 * any type with RX/TX pairs on same core and excess 4844 * of either following 4845 * X n/a - RX and TX queues mapped to consecutive cores of 4846 * any type; all RX then all TX 4847 */ 4848 static unsigned int 4849 get_cpuid_for_queue(if_ctx_t ctx, unsigned int base_cpuid, unsigned int qid, 4850 bool is_tx) 4851 { 4852 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4853 unsigned int core_index; 4854 4855 if (ctx->ifc_sysctl_separate_txrx) { 4856 /* 4857 * When using separate CPUs for TX and RX, the assignment 4858 * will always be of a consecutive CPU out of the set of 4859 * context CPUs, except for the specific case where the 4860 * context CPUs are phsyical cores, the use of logical cores 4861 * has been enabled, the assignment is for TX, the TX qid 4862 * corresponds to an RX qid, and the CPU assigned to the 4863 * corresponding RX queue has an L2 neighbor. 4864 */ 4865 if (ctx->ifc_sysctl_use_logical_cores && 4866 ctx->ifc_cpus_are_physical_cores && 4867 is_tx && qid < scctx->isc_nrxqsets) { 4868 int l2_neighbor; 4869 unsigned int rx_cpuid; 4870 4871 rx_cpuid = cpuid_advance(ctx, base_cpuid, qid); 4872 l2_neighbor = find_l2_neighbor(rx_cpuid); 4873 if (l2_neighbor != -1) { 4874 return (l2_neighbor); 4875 } 4876 /* 4877 * ... else fall through to the normal 4878 * consecutive-after-RX assignment scheme. 4879 * 4880 * Note that we are assuming that all RX queue CPUs 4881 * have an L2 neighbor, or all do not. If a mixed 4882 * scenario is possible, we will have to keep track 4883 * separately of how many queues prior to this one 4884 * were not able to be assigned to an L2 neighbor. 4885 */ 4886 } 4887 if (is_tx) 4888 core_index = scctx->isc_nrxqsets + qid; 4889 else 4890 core_index = qid; 4891 } else { 4892 core_index = qid; 4893 } 4894 4895 return (cpuid_advance(ctx, base_cpuid, core_index)); 4896 } 4897 4898 static uint16_t 4899 get_ctx_core_offset(if_ctx_t ctx) 4900 { 4901 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4902 struct cpu_offset *op; 4903 cpuset_t assigned_cpus; 4904 unsigned int cores_consumed; 4905 unsigned int base_cpuid = ctx->ifc_sysctl_core_offset; 4906 unsigned int first_valid; 4907 unsigned int last_valid; 4908 unsigned int i; 4909 4910 first_valid = CPU_FFS(&ctx->ifc_cpus) - 1; 4911 last_valid = CPU_FLS(&ctx->ifc_cpus) - 1; 4912 4913 if (base_cpuid != CORE_OFFSET_UNSPECIFIED) { 4914 /* 4915 * Align the user-chosen base CPU ID to the next valid CPU 4916 * for this device. If the chosen base CPU ID is smaller 4917 * than the first valid CPU or larger than the last valid 4918 * CPU, we assume the user does not know what the valid 4919 * range is for this device and is thinking in terms of a 4920 * zero-based reference frame, and so we shift the given 4921 * value into the valid range (and wrap accordingly) so the 4922 * intent is translated to the proper frame of reference. 4923 * If the base CPU ID is within the valid first/last, but 4924 * does not correspond to a valid CPU, it is advanced to the 4925 * next valid CPU (wrapping if necessary). 4926 */ 4927 if (base_cpuid < first_valid || base_cpuid > last_valid) { 4928 /* shift from zero-based to first_valid-based */ 4929 base_cpuid += first_valid; 4930 /* wrap to range [first_valid, last_valid] */ 4931 base_cpuid = (base_cpuid - first_valid) % 4932 (last_valid - first_valid + 1); 4933 } 4934 if (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) { 4935 /* 4936 * base_cpuid is in [first_valid, last_valid], but 4937 * not a member of the valid set. In this case, 4938 * there will always be a member of the valid set 4939 * with a CPU ID that is greater than base_cpuid, 4940 * and we simply advance to it. 4941 */ 4942 while (!CPU_ISSET(base_cpuid, &ctx->ifc_cpus)) 4943 base_cpuid++; 4944 } 4945 return (base_cpuid); 4946 } 4947 4948 /* 4949 * Determine how many cores will be consumed by performing the CPU 4950 * assignments and counting how many of the assigned CPUs correspond 4951 * to CPUs in the set of context CPUs. This is done using the CPU 4952 * ID first_valid as the base CPU ID, as the base CPU must be within 4953 * the set of context CPUs. 4954 * 4955 * Note not all assigned CPUs will be in the set of context CPUs 4956 * when separate CPUs are being allocated to TX and RX queues, 4957 * assignment to logical cores has been enabled, the set of context 4958 * CPUs contains only physical CPUs, and TX queues are mapped to L2 4959 * neighbors of CPUs that RX queues have been mapped to - in this 4960 * case we do only want to count how many CPUs in the set of context 4961 * CPUs have been consumed, as that determines the next CPU in that 4962 * set to start allocating at for the next device for which 4963 * core_offset is not set. 4964 */ 4965 CPU_ZERO(&assigned_cpus); 4966 for (i = 0; i < scctx->isc_ntxqsets; i++) 4967 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, true), 4968 &assigned_cpus); 4969 for (i = 0; i < scctx->isc_nrxqsets; i++) 4970 CPU_SET(get_cpuid_for_queue(ctx, first_valid, i, false), 4971 &assigned_cpus); 4972 CPU_AND(&assigned_cpus, &ctx->ifc_cpus); 4973 cores_consumed = CPU_COUNT(&assigned_cpus); 4974 4975 mtx_lock(&cpu_offset_mtx); 4976 SLIST_FOREACH(op, &cpu_offsets, entries) { 4977 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4978 base_cpuid = op->next_cpuid; 4979 op->next_cpuid = cpuid_advance(ctx, op->next_cpuid, 4980 cores_consumed); 4981 MPASS(op->refcount < UINT_MAX); 4982 op->refcount++; 4983 break; 4984 } 4985 } 4986 if (base_cpuid == CORE_OFFSET_UNSPECIFIED) { 4987 base_cpuid = first_valid; 4988 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4989 M_NOWAIT | M_ZERO); 4990 if (op == NULL) { 4991 device_printf(ctx->ifc_dev, 4992 "allocation for cpu offset failed.\n"); 4993 } else { 4994 op->next_cpuid = cpuid_advance(ctx, base_cpuid, 4995 cores_consumed); 4996 op->refcount = 1; 4997 CPU_COPY(&ctx->ifc_cpus, &op->set); 4998 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4999 } 5000 } 5001 mtx_unlock(&cpu_offset_mtx); 5002 5003 return (base_cpuid); 5004 } 5005 5006 static void 5007 unref_ctx_core_offset(if_ctx_t ctx) 5008 { 5009 struct cpu_offset *op, *top; 5010 5011 mtx_lock(&cpu_offset_mtx); 5012 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 5013 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 5014 MPASS(op->refcount > 0); 5015 op->refcount--; 5016 if (op->refcount == 0) { 5017 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 5018 free(op, M_IFLIB); 5019 } 5020 break; 5021 } 5022 } 5023 mtx_unlock(&cpu_offset_mtx); 5024 } 5025 5026 int 5027 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 5028 { 5029 if_ctx_t ctx; 5030 if_t ifp; 5031 if_softc_ctx_t scctx; 5032 kobjop_desc_t kobj_desc; 5033 kobj_method_t *kobj_method; 5034 int err, msix, rid; 5035 int num_txd, num_rxd; 5036 5037 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 5038 5039 if (sc == NULL) { 5040 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5041 device_set_softc(dev, ctx); 5042 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5043 } 5044 5045 ctx->ifc_sctx = sctx; 5046 ctx->ifc_dev = dev; 5047 ctx->ifc_softc = sc; 5048 5049 if ((err = iflib_register(ctx)) != 0) { 5050 device_printf(dev, "iflib_register failed %d\n", err); 5051 goto fail_ctx_free; 5052 } 5053 iflib_add_device_sysctl_pre(ctx); 5054 5055 scctx = &ctx->ifc_softc_ctx; 5056 ifp = ctx->ifc_ifp; 5057 5058 iflib_reset_qvalues(ctx); 5059 CTX_LOCK(ctx); 5060 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5061 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5062 goto fail_unlock; 5063 } 5064 _iflib_pre_assert(scctx); 5065 ctx->ifc_txrx = *scctx->isc_txrx; 5066 5067 MPASS(scctx->isc_dma_width <= flsll(BUS_SPACE_MAXADDR)); 5068 5069 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 5070 ctx->ifc_mediap = scctx->isc_media; 5071 5072 #ifdef INVARIANTS 5073 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5074 MPASS(scctx->isc_tx_csum_flags); 5075 #endif 5076 5077 if_setcapabilities(ifp, 5078 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_MEXTPG); 5079 if_setcapenable(ifp, 5080 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_MEXTPG); 5081 5082 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5083 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5084 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5085 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5086 5087 num_txd = iflib_num_tx_descs(ctx); 5088 num_rxd = iflib_num_rx_descs(ctx); 5089 5090 /* XXX change for per-queue sizes */ 5091 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5092 num_txd, num_rxd); 5093 5094 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5095 scctx->isc_tx_nsegments = max(1, num_txd / 5096 MAX_SINGLE_PACKET_FRACTION); 5097 if (scctx->isc_tx_tso_segments_max > num_txd / 5098 MAX_SINGLE_PACKET_FRACTION) 5099 scctx->isc_tx_tso_segments_max = max(1, 5100 num_txd / MAX_SINGLE_PACKET_FRACTION); 5101 5102 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5103 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5104 /* 5105 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5106 * but some MACs do. 5107 */ 5108 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5109 IP_MAXPACKET)); 5110 /* 5111 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5112 * into account. In the worst case, each of these calls will 5113 * add another mbuf and, thus, the requirement for another DMA 5114 * segment. So for best performance, it doesn't make sense to 5115 * advertize a maximum of TSO segments that typically will 5116 * require defragmentation in iflib_encap(). 5117 */ 5118 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5119 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5120 } 5121 if (scctx->isc_rss_table_size == 0) 5122 scctx->isc_rss_table_size = 64; 5123 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5124 5125 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5126 /* XXX format name */ 5127 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5128 NULL, NULL, "admin"); 5129 5130 /* Set up cpu set. If it fails, use the set of all CPUs. */ 5131 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 5132 device_printf(dev, "Unable to fetch CPU list\n"); 5133 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 5134 ctx->ifc_cpus_are_physical_cores = false; 5135 } else 5136 ctx->ifc_cpus_are_physical_cores = true; 5137 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 5138 5139 /* 5140 ** Now set up MSI or MSI-X, should return us the number of supported 5141 ** vectors (will be 1 for a legacy interrupt and MSI). 5142 */ 5143 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 5144 msix = scctx->isc_vectors; 5145 } else if (scctx->isc_msix_bar != 0) 5146 /* 5147 * The simple fact that isc_msix_bar is not 0 does not mean we 5148 * we have a good value there that is known to work. 5149 */ 5150 msix = iflib_msix_init(ctx); 5151 else { 5152 scctx->isc_vectors = 1; 5153 scctx->isc_ntxqsets = 1; 5154 scctx->isc_nrxqsets = 1; 5155 scctx->isc_intr = IFLIB_INTR_LEGACY; 5156 msix = 0; 5157 } 5158 /* Get memory for the station queues */ 5159 if ((err = iflib_queues_alloc(ctx))) { 5160 device_printf(dev, "Unable to allocate queue memory\n"); 5161 goto fail_intr_free; 5162 } 5163 5164 if ((err = iflib_qset_structures_setup(ctx))) 5165 goto fail_queues; 5166 5167 /* 5168 * Now that we know how many queues there are, get the core offset. 5169 */ 5170 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 5171 5172 if (msix > 1) { 5173 /* 5174 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 5175 * aren't the default NULL implementation. 5176 */ 5177 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 5178 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5179 kobj_desc); 5180 if (kobj_method == &kobj_desc->deflt) { 5181 device_printf(dev, 5182 "MSI-X requires ifdi_rx_queue_intr_enable method"); 5183 err = EOPNOTSUPP; 5184 goto fail_queues; 5185 } 5186 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 5187 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 5188 kobj_desc); 5189 if (kobj_method == &kobj_desc->deflt) { 5190 device_printf(dev, 5191 "MSI-X requires ifdi_tx_queue_intr_enable method"); 5192 err = EOPNOTSUPP; 5193 goto fail_queues; 5194 } 5195 5196 /* 5197 * Assign the MSI-X vectors. 5198 * Note that the default NULL ifdi_msix_intr_assign method will 5199 * fail here, too. 5200 */ 5201 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 5202 if (err != 0) { 5203 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 5204 err); 5205 goto fail_queues; 5206 } 5207 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 5208 rid = 0; 5209 if (scctx->isc_intr == IFLIB_INTR_MSI) { 5210 MPASS(msix == 1); 5211 rid = 1; 5212 } 5213 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 5214 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 5215 goto fail_queues; 5216 } 5217 } else { 5218 device_printf(dev, 5219 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 5220 err = ENODEV; 5221 goto fail_queues; 5222 } 5223 5224 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5225 5226 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5227 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5228 goto fail_detach; 5229 } 5230 5231 /* 5232 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5233 * This must appear after the call to ether_ifattach() because 5234 * ether_ifattach() sets if_hdrlen to the default value. 5235 */ 5236 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5237 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5238 5239 if ((err = iflib_netmap_attach(ctx))) { 5240 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 5241 goto fail_detach; 5242 } 5243 *ctxp = ctx; 5244 5245 DEBUGNET_SET(ctx->ifc_ifp, iflib); 5246 5247 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5248 iflib_add_device_sysctl_post(ctx); 5249 iflib_add_pfil(ctx); 5250 ctx->ifc_flags |= IFC_INIT_DONE; 5251 CTX_UNLOCK(ctx); 5252 5253 return (0); 5254 5255 fail_detach: 5256 ether_ifdetach(ctx->ifc_ifp); 5257 fail_queues: 5258 iflib_tqg_detach(ctx); 5259 iflib_tx_structures_free(ctx); 5260 iflib_rx_structures_free(ctx); 5261 IFDI_DETACH(ctx); 5262 IFDI_QUEUES_FREE(ctx); 5263 fail_intr_free: 5264 iflib_free_intr_mem(ctx); 5265 fail_unlock: 5266 CTX_UNLOCK(ctx); 5267 iflib_deregister(ctx); 5268 fail_ctx_free: 5269 device_set_softc(ctx->ifc_dev, NULL); 5270 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5271 free(ctx->ifc_softc, M_IFLIB); 5272 free(ctx, M_IFLIB); 5273 return (err); 5274 } 5275 5276 int 5277 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 5278 struct iflib_cloneattach_ctx *clctx) 5279 { 5280 int num_txd, num_rxd; 5281 int err; 5282 if_ctx_t ctx; 5283 if_t ifp; 5284 if_softc_ctx_t scctx; 5285 int i; 5286 void *sc; 5287 5288 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 5289 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 5290 ctx->ifc_flags |= IFC_SC_ALLOCATED; 5291 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 5292 ctx->ifc_flags |= IFC_PSEUDO; 5293 5294 ctx->ifc_sctx = sctx; 5295 ctx->ifc_softc = sc; 5296 ctx->ifc_dev = dev; 5297 5298 if ((err = iflib_register(ctx)) != 0) { 5299 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 5300 goto fail_ctx_free; 5301 } 5302 iflib_add_device_sysctl_pre(ctx); 5303 5304 scctx = &ctx->ifc_softc_ctx; 5305 ifp = ctx->ifc_ifp; 5306 5307 iflib_reset_qvalues(ctx); 5308 CTX_LOCK(ctx); 5309 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 5310 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 5311 goto fail_unlock; 5312 } 5313 if (sctx->isc_flags & IFLIB_GEN_MAC) 5314 ether_gen_addr(ifp, &ctx->ifc_mac); 5315 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 5316 clctx->cc_params)) != 0) { 5317 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 5318 goto fail_unlock; 5319 } 5320 #ifdef INVARIANTS 5321 if (scctx->isc_capabilities & IFCAP_TXCSUM) 5322 MPASS(scctx->isc_tx_csum_flags); 5323 #endif 5324 5325 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5326 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 5327 5328 ifp->if_flags |= IFF_NOGROUP; 5329 if (sctx->isc_flags & IFLIB_PSEUDO) { 5330 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5331 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5332 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) { 5333 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5334 } else { 5335 if_attach(ctx->ifc_ifp); 5336 bpfattach(ctx->ifc_ifp, DLT_NULL, sizeof(u_int32_t)); 5337 } 5338 5339 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5340 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5341 goto fail_detach; 5342 } 5343 *ctxp = ctx; 5344 5345 /* 5346 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5347 * This must appear after the call to ether_ifattach() because 5348 * ether_ifattach() sets if_hdrlen to the default value. 5349 */ 5350 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5351 if_setifheaderlen(ifp, 5352 sizeof(struct ether_vlan_header)); 5353 5354 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5355 iflib_add_device_sysctl_post(ctx); 5356 ctx->ifc_flags |= IFC_INIT_DONE; 5357 CTX_UNLOCK(ctx); 5358 return (0); 5359 } 5360 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 5361 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 5362 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 5363 5364 _iflib_pre_assert(scctx); 5365 ctx->ifc_txrx = *scctx->isc_txrx; 5366 5367 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 5368 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 5369 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 5370 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 5371 5372 num_txd = iflib_num_tx_descs(ctx); 5373 num_rxd = iflib_num_rx_descs(ctx); 5374 5375 /* XXX change for per-queue sizes */ 5376 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 5377 num_txd, num_rxd); 5378 5379 if (scctx->isc_tx_nsegments > num_txd / MAX_SINGLE_PACKET_FRACTION) 5380 scctx->isc_tx_nsegments = max(1, num_txd / 5381 MAX_SINGLE_PACKET_FRACTION); 5382 if (scctx->isc_tx_tso_segments_max > num_txd / 5383 MAX_SINGLE_PACKET_FRACTION) 5384 scctx->isc_tx_tso_segments_max = max(1, 5385 num_txd / MAX_SINGLE_PACKET_FRACTION); 5386 5387 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 5388 if (if_getcapabilities(ifp) & IFCAP_TSO) { 5389 /* 5390 * The stack can't handle a TSO size larger than IP_MAXPACKET, 5391 * but some MACs do. 5392 */ 5393 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 5394 IP_MAXPACKET)); 5395 /* 5396 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 5397 * into account. In the worst case, each of these calls will 5398 * add another mbuf and, thus, the requirement for another DMA 5399 * segment. So for best performance, it doesn't make sense to 5400 * advertize a maximum of TSO segments that typically will 5401 * require defragmentation in iflib_encap(). 5402 */ 5403 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 5404 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 5405 } 5406 if (scctx->isc_rss_table_size == 0) 5407 scctx->isc_rss_table_size = 64; 5408 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 5409 5410 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 5411 /* XXX format name */ 5412 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 5413 NULL, NULL, "admin"); 5414 5415 /* XXX --- can support > 1 -- but keep it simple for now */ 5416 scctx->isc_intr = IFLIB_INTR_LEGACY; 5417 5418 /* Get memory for the station queues */ 5419 if ((err = iflib_queues_alloc(ctx))) { 5420 device_printf(dev, "Unable to allocate queue memory\n"); 5421 goto fail_iflib_detach; 5422 } 5423 5424 if ((err = iflib_qset_structures_setup(ctx))) { 5425 device_printf(dev, "qset structure setup failed %d\n", err); 5426 goto fail_queues; 5427 } 5428 5429 /* 5430 * XXX What if anything do we want to do about interrupts? 5431 */ 5432 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 5433 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 5434 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 5435 goto fail_detach; 5436 } 5437 5438 /* 5439 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 5440 * This must appear after the call to ether_ifattach() because 5441 * ether_ifattach() sets if_hdrlen to the default value. 5442 */ 5443 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 5444 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 5445 5446 /* XXX handle more than one queue */ 5447 for (i = 0; i < scctx->isc_nrxqsets; i++) 5448 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 5449 5450 *ctxp = ctx; 5451 5452 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 5453 iflib_add_device_sysctl_post(ctx); 5454 ctx->ifc_flags |= IFC_INIT_DONE; 5455 CTX_UNLOCK(ctx); 5456 5457 return (0); 5458 fail_detach: 5459 ether_ifdetach(ctx->ifc_ifp); 5460 fail_queues: 5461 iflib_tqg_detach(ctx); 5462 iflib_tx_structures_free(ctx); 5463 iflib_rx_structures_free(ctx); 5464 fail_iflib_detach: 5465 IFDI_DETACH(ctx); 5466 IFDI_QUEUES_FREE(ctx); 5467 fail_unlock: 5468 CTX_UNLOCK(ctx); 5469 iflib_deregister(ctx); 5470 fail_ctx_free: 5471 free(ctx->ifc_softc, M_IFLIB); 5472 free(ctx, M_IFLIB); 5473 return (err); 5474 } 5475 5476 int 5477 iflib_pseudo_deregister(if_ctx_t ctx) 5478 { 5479 if_t ifp = ctx->ifc_ifp; 5480 if_shared_ctx_t sctx = ctx->ifc_sctx; 5481 5482 /* Unregister VLAN event handlers early */ 5483 iflib_unregister_vlan_handlers(ctx); 5484 5485 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5486 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) { 5487 bpfdetach(ifp); 5488 if_detach(ifp); 5489 } else { 5490 ether_ifdetach(ifp); 5491 } 5492 5493 iflib_tqg_detach(ctx); 5494 iflib_tx_structures_free(ctx); 5495 iflib_rx_structures_free(ctx); 5496 IFDI_DETACH(ctx); 5497 IFDI_QUEUES_FREE(ctx); 5498 5499 iflib_deregister(ctx); 5500 5501 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5502 free(ctx->ifc_softc, M_IFLIB); 5503 free(ctx, M_IFLIB); 5504 return (0); 5505 } 5506 5507 int 5508 iflib_device_attach(device_t dev) 5509 { 5510 if_ctx_t ctx; 5511 if_shared_ctx_t sctx; 5512 5513 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5514 return (ENOTSUP); 5515 5516 pci_enable_busmaster(dev); 5517 5518 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5519 } 5520 5521 int 5522 iflib_device_deregister(if_ctx_t ctx) 5523 { 5524 if_t ifp = ctx->ifc_ifp; 5525 device_t dev = ctx->ifc_dev; 5526 5527 /* Make sure VLANS are not using driver */ 5528 if (if_vlantrunkinuse(ifp)) { 5529 device_printf(dev, "Vlan in use, detach first\n"); 5530 return (EBUSY); 5531 } 5532 #ifdef PCI_IOV 5533 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5534 device_printf(dev, "SR-IOV in use; detach first.\n"); 5535 return (EBUSY); 5536 } 5537 #endif 5538 5539 STATE_LOCK(ctx); 5540 ctx->ifc_flags |= IFC_IN_DETACH; 5541 STATE_UNLOCK(ctx); 5542 5543 /* Unregister VLAN handlers before calling iflib_stop() */ 5544 iflib_unregister_vlan_handlers(ctx); 5545 5546 iflib_netmap_detach(ifp); 5547 ether_ifdetach(ifp); 5548 5549 CTX_LOCK(ctx); 5550 iflib_stop(ctx); 5551 CTX_UNLOCK(ctx); 5552 5553 iflib_rem_pfil(ctx); 5554 if (ctx->ifc_led_dev != NULL) 5555 led_destroy(ctx->ifc_led_dev); 5556 5557 iflib_tqg_detach(ctx); 5558 iflib_tx_structures_free(ctx); 5559 iflib_rx_structures_free(ctx); 5560 5561 CTX_LOCK(ctx); 5562 IFDI_DETACH(ctx); 5563 IFDI_QUEUES_FREE(ctx); 5564 CTX_UNLOCK(ctx); 5565 5566 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5567 iflib_free_intr_mem(ctx); 5568 5569 bus_generic_detach(dev); 5570 5571 iflib_deregister(ctx); 5572 5573 device_set_softc(ctx->ifc_dev, NULL); 5574 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5575 free(ctx->ifc_softc, M_IFLIB); 5576 unref_ctx_core_offset(ctx); 5577 free(ctx, M_IFLIB); 5578 return (0); 5579 } 5580 5581 static void 5582 iflib_tqg_detach(if_ctx_t ctx) 5583 { 5584 iflib_txq_t txq; 5585 iflib_rxq_t rxq; 5586 int i; 5587 struct taskqgroup *tqg; 5588 5589 /* XXX drain any dependent tasks */ 5590 tqg = qgroup_if_io_tqg; 5591 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5592 callout_drain(&txq->ift_timer); 5593 #ifdef DEV_NETMAP 5594 callout_drain(&txq->ift_netmap_timer); 5595 #endif /* DEV_NETMAP */ 5596 if (txq->ift_task.gt_uniq != NULL) 5597 taskqgroup_detach(tqg, &txq->ift_task); 5598 } 5599 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5600 if (rxq->ifr_task.gt_uniq != NULL) 5601 taskqgroup_detach(tqg, &rxq->ifr_task); 5602 } 5603 tqg = qgroup_if_config_tqg; 5604 if (ctx->ifc_admin_task.gt_uniq != NULL) 5605 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5606 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5607 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5608 } 5609 5610 static void 5611 iflib_free_intr_mem(if_ctx_t ctx) 5612 { 5613 5614 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5615 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5616 } 5617 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5618 pci_release_msi(ctx->ifc_dev); 5619 } 5620 if (ctx->ifc_msix_mem != NULL) { 5621 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5622 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5623 ctx->ifc_msix_mem = NULL; 5624 } 5625 } 5626 5627 int 5628 iflib_device_detach(device_t dev) 5629 { 5630 if_ctx_t ctx = device_get_softc(dev); 5631 5632 return (iflib_device_deregister(ctx)); 5633 } 5634 5635 int 5636 iflib_device_suspend(device_t dev) 5637 { 5638 if_ctx_t ctx = device_get_softc(dev); 5639 5640 CTX_LOCK(ctx); 5641 IFDI_SUSPEND(ctx); 5642 CTX_UNLOCK(ctx); 5643 5644 return bus_generic_suspend(dev); 5645 } 5646 int 5647 iflib_device_shutdown(device_t dev) 5648 { 5649 if_ctx_t ctx = device_get_softc(dev); 5650 5651 CTX_LOCK(ctx); 5652 IFDI_SHUTDOWN(ctx); 5653 CTX_UNLOCK(ctx); 5654 5655 return bus_generic_suspend(dev); 5656 } 5657 5658 int 5659 iflib_device_resume(device_t dev) 5660 { 5661 if_ctx_t ctx = device_get_softc(dev); 5662 iflib_txq_t txq = ctx->ifc_txqs; 5663 5664 CTX_LOCK(ctx); 5665 IFDI_RESUME(ctx); 5666 iflib_if_init_locked(ctx); 5667 CTX_UNLOCK(ctx); 5668 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5669 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5670 5671 return (bus_generic_resume(dev)); 5672 } 5673 5674 int 5675 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5676 { 5677 int error; 5678 if_ctx_t ctx = device_get_softc(dev); 5679 5680 CTX_LOCK(ctx); 5681 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5682 CTX_UNLOCK(ctx); 5683 5684 return (error); 5685 } 5686 5687 void 5688 iflib_device_iov_uninit(device_t dev) 5689 { 5690 if_ctx_t ctx = device_get_softc(dev); 5691 5692 CTX_LOCK(ctx); 5693 IFDI_IOV_UNINIT(ctx); 5694 CTX_UNLOCK(ctx); 5695 } 5696 5697 int 5698 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5699 { 5700 int error; 5701 if_ctx_t ctx = device_get_softc(dev); 5702 5703 CTX_LOCK(ctx); 5704 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5705 CTX_UNLOCK(ctx); 5706 5707 return (error); 5708 } 5709 5710 /********************************************************************* 5711 * 5712 * MODULE FUNCTION DEFINITIONS 5713 * 5714 **********************************************************************/ 5715 5716 /* 5717 * - Start a fast taskqueue thread for each core 5718 * - Start a taskqueue for control operations 5719 */ 5720 static int 5721 iflib_module_init(void) 5722 { 5723 iflib_timer_default = hz / 2; 5724 return (0); 5725 } 5726 5727 static int 5728 iflib_module_event_handler(module_t mod, int what, void *arg) 5729 { 5730 int err; 5731 5732 switch (what) { 5733 case MOD_LOAD: 5734 if ((err = iflib_module_init()) != 0) 5735 return (err); 5736 break; 5737 case MOD_UNLOAD: 5738 return (EBUSY); 5739 default: 5740 return (EOPNOTSUPP); 5741 } 5742 5743 return (0); 5744 } 5745 5746 /********************************************************************* 5747 * 5748 * PUBLIC FUNCTION DEFINITIONS 5749 * ordered as in iflib.h 5750 * 5751 **********************************************************************/ 5752 5753 static void 5754 _iflib_assert(if_shared_ctx_t sctx) 5755 { 5756 int i; 5757 5758 MPASS(sctx->isc_tx_maxsize); 5759 MPASS(sctx->isc_tx_maxsegsize); 5760 5761 MPASS(sctx->isc_rx_maxsize); 5762 MPASS(sctx->isc_rx_nsegments); 5763 MPASS(sctx->isc_rx_maxsegsize); 5764 5765 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5766 for (i = 0; i < sctx->isc_nrxqs; i++) { 5767 MPASS(sctx->isc_nrxd_min[i]); 5768 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5769 MPASS(sctx->isc_nrxd_max[i]); 5770 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5771 MPASS(sctx->isc_nrxd_default[i]); 5772 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5773 } 5774 5775 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5776 for (i = 0; i < sctx->isc_ntxqs; i++) { 5777 MPASS(sctx->isc_ntxd_min[i]); 5778 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5779 MPASS(sctx->isc_ntxd_max[i]); 5780 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5781 MPASS(sctx->isc_ntxd_default[i]); 5782 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5783 } 5784 } 5785 5786 static void 5787 _iflib_pre_assert(if_softc_ctx_t scctx) 5788 { 5789 5790 MPASS(scctx->isc_txrx->ift_txd_encap); 5791 MPASS(scctx->isc_txrx->ift_txd_flush); 5792 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5793 MPASS(scctx->isc_txrx->ift_rxd_available); 5794 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5795 MPASS(scctx->isc_txrx->ift_rxd_refill); 5796 MPASS(scctx->isc_txrx->ift_rxd_flush); 5797 } 5798 5799 static int 5800 iflib_register(if_ctx_t ctx) 5801 { 5802 if_shared_ctx_t sctx = ctx->ifc_sctx; 5803 driver_t *driver = sctx->isc_driver; 5804 device_t dev = ctx->ifc_dev; 5805 if_t ifp; 5806 u_char type; 5807 int iflags; 5808 5809 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5810 _iflib_assert(sctx); 5811 5812 CTX_LOCK_INIT(ctx); 5813 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5814 if (sctx->isc_flags & IFLIB_PSEUDO) { 5815 if (sctx->isc_flags & IFLIB_PSEUDO_ETHER) 5816 type = IFT_ETHER; 5817 else 5818 type = IFT_PPP; 5819 } else 5820 type = IFT_ETHER; 5821 ifp = ctx->ifc_ifp = if_alloc(type); 5822 if (ifp == NULL) { 5823 device_printf(dev, "can not allocate ifnet structure\n"); 5824 return (ENOMEM); 5825 } 5826 5827 /* 5828 * Initialize our context's device specific methods 5829 */ 5830 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5831 kobj_class_compile((kobj_class_t) driver); 5832 5833 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5834 if_setsoftc(ifp, ctx); 5835 if_setdev(ifp, dev); 5836 if_setinitfn(ifp, iflib_if_init); 5837 if_setioctlfn(ifp, iflib_if_ioctl); 5838 #ifdef ALTQ 5839 if_setstartfn(ifp, iflib_altq_if_start); 5840 if_settransmitfn(ifp, iflib_altq_if_transmit); 5841 if_setsendqready(ifp); 5842 #else 5843 if_settransmitfn(ifp, iflib_if_transmit); 5844 #endif 5845 if_setqflushfn(ifp, iflib_if_qflush); 5846 iflags = IFF_MULTICAST | IFF_KNOWSEPOCH; 5847 5848 if ((sctx->isc_flags & IFLIB_PSEUDO) && 5849 (sctx->isc_flags & IFLIB_PSEUDO_ETHER) == 0) 5850 iflags |= IFF_POINTOPOINT; 5851 else 5852 iflags |= IFF_BROADCAST | IFF_SIMPLEX; 5853 if_setflags(ifp, iflags); 5854 ctx->ifc_vlan_attach_event = 5855 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5856 EVENTHANDLER_PRI_FIRST); 5857 ctx->ifc_vlan_detach_event = 5858 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5859 EVENTHANDLER_PRI_FIRST); 5860 5861 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5862 ctx->ifc_mediap = &ctx->ifc_media; 5863 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5864 iflib_media_change, iflib_media_status); 5865 } 5866 return (0); 5867 } 5868 5869 static void 5870 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5871 { 5872 /* Unregister VLAN events */ 5873 if (ctx->ifc_vlan_attach_event != NULL) { 5874 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5875 ctx->ifc_vlan_attach_event = NULL; 5876 } 5877 if (ctx->ifc_vlan_detach_event != NULL) { 5878 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5879 ctx->ifc_vlan_detach_event = NULL; 5880 } 5881 5882 } 5883 5884 static void 5885 iflib_deregister(if_ctx_t ctx) 5886 { 5887 if_t ifp = ctx->ifc_ifp; 5888 5889 /* Remove all media */ 5890 ifmedia_removeall(&ctx->ifc_media); 5891 5892 /* Ensure that VLAN event handlers are unregistered */ 5893 iflib_unregister_vlan_handlers(ctx); 5894 5895 /* Release kobject reference */ 5896 kobj_delete((kobj_t) ctx, NULL); 5897 5898 /* Free the ifnet structure */ 5899 if_free(ifp); 5900 5901 STATE_LOCK_DESTROY(ctx); 5902 5903 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5904 CTX_LOCK_DESTROY(ctx); 5905 } 5906 5907 static int 5908 iflib_queues_alloc(if_ctx_t ctx) 5909 { 5910 if_shared_ctx_t sctx = ctx->ifc_sctx; 5911 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5912 device_t dev = ctx->ifc_dev; 5913 int nrxqsets = scctx->isc_nrxqsets; 5914 int ntxqsets = scctx->isc_ntxqsets; 5915 iflib_txq_t txq; 5916 iflib_rxq_t rxq; 5917 iflib_fl_t fl = NULL; 5918 int i, j, cpu, err, txconf, rxconf; 5919 iflib_dma_info_t ifdip; 5920 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5921 uint32_t *txqsizes = scctx->isc_txqsizes; 5922 uint8_t nrxqs = sctx->isc_nrxqs; 5923 uint8_t ntxqs = sctx->isc_ntxqs; 5924 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5925 int fl_offset = (sctx->isc_flags & IFLIB_HAS_RXCQ ? 1 : 0); 5926 caddr_t *vaddrs; 5927 uint64_t *paddrs; 5928 5929 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5930 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5931 KASSERT(nrxqs >= fl_offset + nfree_lists, 5932 ("there must be at least a rxq for each free list")); 5933 5934 /* Allocate the TX ring struct memory */ 5935 if (!(ctx->ifc_txqs = 5936 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5937 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5938 device_printf(dev, "Unable to allocate TX ring memory\n"); 5939 err = ENOMEM; 5940 goto fail; 5941 } 5942 5943 /* Now allocate the RX */ 5944 if (!(ctx->ifc_rxqs = 5945 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5946 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5947 device_printf(dev, "Unable to allocate RX ring memory\n"); 5948 err = ENOMEM; 5949 goto rx_fail; 5950 } 5951 5952 txq = ctx->ifc_txqs; 5953 rxq = ctx->ifc_rxqs; 5954 5955 /* 5956 * XXX handle allocation failure 5957 */ 5958 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5959 /* Set up some basics */ 5960 5961 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5962 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5963 device_printf(dev, 5964 "Unable to allocate TX DMA info memory\n"); 5965 err = ENOMEM; 5966 goto err_tx_desc; 5967 } 5968 txq->ift_ifdi = ifdip; 5969 for (j = 0; j < ntxqs; j++, ifdip++) { 5970 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5971 device_printf(dev, 5972 "Unable to allocate TX descriptors\n"); 5973 err = ENOMEM; 5974 goto err_tx_desc; 5975 } 5976 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5977 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5978 } 5979 txq->ift_ctx = ctx; 5980 txq->ift_id = i; 5981 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5982 txq->ift_br_offset = 1; 5983 } else { 5984 txq->ift_br_offset = 0; 5985 } 5986 5987 if (iflib_txsd_alloc(txq)) { 5988 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5989 err = ENOMEM; 5990 goto err_tx_desc; 5991 } 5992 5993 /* Initialize the TX lock */ 5994 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5995 device_get_nameunit(dev), txq->ift_id); 5996 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5997 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5998 txq->ift_timer.c_cpu = cpu; 5999 #ifdef DEV_NETMAP 6000 callout_init_mtx(&txq->ift_netmap_timer, &txq->ift_mtx, 0); 6001 txq->ift_netmap_timer.c_cpu = cpu; 6002 #endif /* DEV_NETMAP */ 6003 6004 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 6005 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 6006 if (err) { 6007 /* XXX free any allocated rings */ 6008 device_printf(dev, "Unable to allocate buf_ring\n"); 6009 goto err_tx_desc; 6010 } 6011 } 6012 6013 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 6014 /* Set up some basics */ 6015 callout_init(&rxq->ifr_watchdog, 1); 6016 6017 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 6018 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 6019 device_printf(dev, 6020 "Unable to allocate RX DMA info memory\n"); 6021 err = ENOMEM; 6022 goto err_tx_desc; 6023 } 6024 6025 rxq->ifr_ifdi = ifdip; 6026 /* XXX this needs to be changed if #rx queues != #tx queues */ 6027 rxq->ifr_ntxqirq = 1; 6028 rxq->ifr_txqid[0] = i; 6029 for (j = 0; j < nrxqs; j++, ifdip++) { 6030 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 6031 device_printf(dev, 6032 "Unable to allocate RX descriptors\n"); 6033 err = ENOMEM; 6034 goto err_tx_desc; 6035 } 6036 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 6037 } 6038 rxq->ifr_ctx = ctx; 6039 rxq->ifr_id = i; 6040 rxq->ifr_fl_offset = fl_offset; 6041 rxq->ifr_nfl = nfree_lists; 6042 if (!(fl = 6043 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 6044 device_printf(dev, "Unable to allocate free list memory\n"); 6045 err = ENOMEM; 6046 goto err_tx_desc; 6047 } 6048 rxq->ifr_fl = fl; 6049 for (j = 0; j < nfree_lists; j++) { 6050 fl[j].ifl_rxq = rxq; 6051 fl[j].ifl_id = j; 6052 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 6053 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 6054 } 6055 /* Allocate receive buffers for the ring */ 6056 if (iflib_rxsd_alloc(rxq)) { 6057 device_printf(dev, 6058 "Critical Failure setting up receive buffers\n"); 6059 err = ENOMEM; 6060 goto err_rx_desc; 6061 } 6062 6063 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 6064 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 6065 M_WAITOK); 6066 } 6067 6068 /* TXQs */ 6069 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6070 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 6071 for (i = 0; i < ntxqsets; i++) { 6072 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 6073 6074 for (j = 0; j < ntxqs; j++, di++) { 6075 vaddrs[i*ntxqs + j] = di->idi_vaddr; 6076 paddrs[i*ntxqs + j] = di->idi_paddr; 6077 } 6078 } 6079 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 6080 device_printf(ctx->ifc_dev, 6081 "Unable to allocate device TX queue\n"); 6082 iflib_tx_structures_free(ctx); 6083 free(vaddrs, M_IFLIB); 6084 free(paddrs, M_IFLIB); 6085 goto err_rx_desc; 6086 } 6087 free(vaddrs, M_IFLIB); 6088 free(paddrs, M_IFLIB); 6089 6090 /* RXQs */ 6091 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6092 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 6093 for (i = 0; i < nrxqsets; i++) { 6094 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 6095 6096 for (j = 0; j < nrxqs; j++, di++) { 6097 vaddrs[i*nrxqs + j] = di->idi_vaddr; 6098 paddrs[i*nrxqs + j] = di->idi_paddr; 6099 } 6100 } 6101 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 6102 device_printf(ctx->ifc_dev, 6103 "Unable to allocate device RX queue\n"); 6104 iflib_tx_structures_free(ctx); 6105 free(vaddrs, M_IFLIB); 6106 free(paddrs, M_IFLIB); 6107 goto err_rx_desc; 6108 } 6109 free(vaddrs, M_IFLIB); 6110 free(paddrs, M_IFLIB); 6111 6112 return (0); 6113 6114 /* XXX handle allocation failure changes */ 6115 err_rx_desc: 6116 err_tx_desc: 6117 rx_fail: 6118 if (ctx->ifc_rxqs != NULL) 6119 free(ctx->ifc_rxqs, M_IFLIB); 6120 ctx->ifc_rxqs = NULL; 6121 if (ctx->ifc_txqs != NULL) 6122 free(ctx->ifc_txqs, M_IFLIB); 6123 ctx->ifc_txqs = NULL; 6124 fail: 6125 return (err); 6126 } 6127 6128 static int 6129 iflib_tx_structures_setup(if_ctx_t ctx) 6130 { 6131 iflib_txq_t txq = ctx->ifc_txqs; 6132 int i; 6133 6134 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 6135 iflib_txq_setup(txq); 6136 6137 return (0); 6138 } 6139 6140 static void 6141 iflib_tx_structures_free(if_ctx_t ctx) 6142 { 6143 iflib_txq_t txq = ctx->ifc_txqs; 6144 if_shared_ctx_t sctx = ctx->ifc_sctx; 6145 int i, j; 6146 6147 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 6148 for (j = 0; j < sctx->isc_ntxqs; j++) 6149 iflib_dma_free(&txq->ift_ifdi[j]); 6150 iflib_txq_destroy(txq); 6151 } 6152 free(ctx->ifc_txqs, M_IFLIB); 6153 ctx->ifc_txqs = NULL; 6154 } 6155 6156 /********************************************************************* 6157 * 6158 * Initialize all receive rings. 6159 * 6160 **********************************************************************/ 6161 static int 6162 iflib_rx_structures_setup(if_ctx_t ctx) 6163 { 6164 iflib_rxq_t rxq = ctx->ifc_rxqs; 6165 int q; 6166 #if defined(INET6) || defined(INET) 6167 int err, i; 6168 #endif 6169 6170 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 6171 #if defined(INET6) || defined(INET) 6172 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 6173 TCP_LRO_ENTRIES, min(1024, 6174 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 6175 if (err != 0) { 6176 device_printf(ctx->ifc_dev, 6177 "LRO Initialization failed!\n"); 6178 goto fail; 6179 } 6180 #endif 6181 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 6182 } 6183 return (0); 6184 #if defined(INET6) || defined(INET) 6185 fail: 6186 /* 6187 * Free LRO resources allocated so far, we will only handle 6188 * the rings that completed, the failing case will have 6189 * cleaned up for itself. 'q' failed, so its the terminus. 6190 */ 6191 rxq = ctx->ifc_rxqs; 6192 for (i = 0; i < q; ++i, rxq++) { 6193 tcp_lro_free(&rxq->ifr_lc); 6194 } 6195 return (err); 6196 #endif 6197 } 6198 6199 /********************************************************************* 6200 * 6201 * Free all receive rings. 6202 * 6203 **********************************************************************/ 6204 static void 6205 iflib_rx_structures_free(if_ctx_t ctx) 6206 { 6207 iflib_rxq_t rxq = ctx->ifc_rxqs; 6208 if_shared_ctx_t sctx = ctx->ifc_sctx; 6209 int i, j; 6210 6211 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 6212 for (j = 0; j < sctx->isc_nrxqs; j++) 6213 iflib_dma_free(&rxq->ifr_ifdi[j]); 6214 iflib_rx_sds_free(rxq); 6215 #if defined(INET6) || defined(INET) 6216 tcp_lro_free(&rxq->ifr_lc); 6217 #endif 6218 } 6219 free(ctx->ifc_rxqs, M_IFLIB); 6220 ctx->ifc_rxqs = NULL; 6221 } 6222 6223 static int 6224 iflib_qset_structures_setup(if_ctx_t ctx) 6225 { 6226 int err; 6227 6228 /* 6229 * It is expected that the caller takes care of freeing queues if this 6230 * fails. 6231 */ 6232 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 6233 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 6234 return (err); 6235 } 6236 6237 if ((err = iflib_rx_structures_setup(ctx)) != 0) 6238 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 6239 6240 return (err); 6241 } 6242 6243 int 6244 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 6245 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 6246 { 6247 6248 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 6249 } 6250 6251 /* Just to avoid copy/paste */ 6252 static inline int 6253 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 6254 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 6255 const char *name) 6256 { 6257 device_t dev; 6258 unsigned int base_cpuid, cpuid; 6259 int err; 6260 6261 dev = ctx->ifc_dev; 6262 base_cpuid = ctx->ifc_sysctl_core_offset; 6263 cpuid = get_cpuid_for_queue(ctx, base_cpuid, qid, type == IFLIB_INTR_TX); 6264 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, 6265 irq ? irq->ii_res : NULL, name); 6266 if (err) { 6267 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 6268 return (err); 6269 } 6270 #ifdef notyet 6271 if (cpuid > ctx->ifc_cpuid_highest) 6272 ctx->ifc_cpuid_highest = cpuid; 6273 #endif 6274 return (0); 6275 } 6276 6277 int 6278 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 6279 iflib_intr_type_t type, driver_filter_t *filter, 6280 void *filter_arg, int qid, const char *name) 6281 { 6282 device_t dev; 6283 struct grouptask *gtask; 6284 struct taskqgroup *tqg; 6285 iflib_filter_info_t info; 6286 gtask_fn_t *fn; 6287 int tqrid, err; 6288 driver_filter_t *intr_fast; 6289 void *q; 6290 6291 info = &ctx->ifc_filter_info; 6292 tqrid = rid; 6293 6294 switch (type) { 6295 /* XXX merge tx/rx for netmap? */ 6296 case IFLIB_INTR_TX: 6297 q = &ctx->ifc_txqs[qid]; 6298 info = &ctx->ifc_txqs[qid].ift_filter_info; 6299 gtask = &ctx->ifc_txqs[qid].ift_task; 6300 tqg = qgroup_if_io_tqg; 6301 fn = _task_fn_tx; 6302 intr_fast = iflib_fast_intr; 6303 GROUPTASK_INIT(gtask, 0, fn, q); 6304 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 6305 break; 6306 case IFLIB_INTR_RX: 6307 q = &ctx->ifc_rxqs[qid]; 6308 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6309 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6310 tqg = qgroup_if_io_tqg; 6311 fn = _task_fn_rx; 6312 intr_fast = iflib_fast_intr; 6313 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6314 break; 6315 case IFLIB_INTR_RXTX: 6316 q = &ctx->ifc_rxqs[qid]; 6317 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 6318 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6319 tqg = qgroup_if_io_tqg; 6320 fn = _task_fn_rx; 6321 intr_fast = iflib_fast_intr_rxtx; 6322 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6323 break; 6324 case IFLIB_INTR_ADMIN: 6325 q = ctx; 6326 tqrid = -1; 6327 info = &ctx->ifc_filter_info; 6328 gtask = &ctx->ifc_admin_task; 6329 tqg = qgroup_if_config_tqg; 6330 fn = _task_fn_admin; 6331 intr_fast = iflib_fast_intr_ctx; 6332 break; 6333 default: 6334 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6335 __func__); 6336 return (EINVAL); 6337 } 6338 6339 info->ifi_filter = filter; 6340 info->ifi_filter_arg = filter_arg; 6341 info->ifi_task = gtask; 6342 info->ifi_ctx = q; 6343 6344 dev = ctx->ifc_dev; 6345 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6346 if (err != 0) { 6347 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6348 return (err); 6349 } 6350 if (type == IFLIB_INTR_ADMIN) 6351 return (0); 6352 6353 if (tqrid != -1) { 6354 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, 6355 name); 6356 if (err) 6357 return (err); 6358 } else { 6359 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6360 } 6361 6362 return (0); 6363 } 6364 6365 void 6366 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6367 { 6368 device_t dev; 6369 struct grouptask *gtask; 6370 struct taskqgroup *tqg; 6371 gtask_fn_t *fn; 6372 void *q; 6373 int err; 6374 6375 switch (type) { 6376 case IFLIB_INTR_TX: 6377 q = &ctx->ifc_txqs[qid]; 6378 gtask = &ctx->ifc_txqs[qid].ift_task; 6379 tqg = qgroup_if_io_tqg; 6380 fn = _task_fn_tx; 6381 GROUPTASK_INIT(gtask, 0, fn, q); 6382 break; 6383 case IFLIB_INTR_RX: 6384 q = &ctx->ifc_rxqs[qid]; 6385 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6386 tqg = qgroup_if_io_tqg; 6387 fn = _task_fn_rx; 6388 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6389 break; 6390 case IFLIB_INTR_IOV: 6391 q = ctx; 6392 gtask = &ctx->ifc_vflr_task; 6393 tqg = qgroup_if_config_tqg; 6394 fn = _task_fn_iov; 6395 GROUPTASK_INIT(gtask, 0, fn, q); 6396 break; 6397 default: 6398 panic("unknown net intr type"); 6399 } 6400 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, q, name); 6401 if (err) { 6402 dev = ctx->ifc_dev; 6403 taskqgroup_attach(tqg, gtask, q, dev, irq ? irq->ii_res : NULL, 6404 name); 6405 } 6406 } 6407 6408 void 6409 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6410 { 6411 6412 if (irq->ii_tag) 6413 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6414 6415 if (irq->ii_res) 6416 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6417 rman_get_rid(irq->ii_res), irq->ii_res); 6418 } 6419 6420 static int 6421 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6422 { 6423 iflib_txq_t txq = ctx->ifc_txqs; 6424 iflib_rxq_t rxq = ctx->ifc_rxqs; 6425 if_irq_t irq = &ctx->ifc_legacy_irq; 6426 iflib_filter_info_t info; 6427 device_t dev; 6428 struct grouptask *gtask; 6429 struct resource *res; 6430 struct taskqgroup *tqg; 6431 void *q; 6432 int err, tqrid; 6433 bool rx_only; 6434 6435 q = &ctx->ifc_rxqs[0]; 6436 info = &rxq[0].ifr_filter_info; 6437 gtask = &rxq[0].ifr_task; 6438 tqg = qgroup_if_io_tqg; 6439 tqrid = *rid; 6440 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6441 6442 ctx->ifc_flags |= IFC_LEGACY; 6443 info->ifi_filter = filter; 6444 info->ifi_filter_arg = filter_arg; 6445 info->ifi_task = gtask; 6446 info->ifi_ctx = rx_only ? ctx : q; 6447 6448 dev = ctx->ifc_dev; 6449 /* We allocate a single interrupt resource */ 6450 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6451 iflib_fast_intr_rxtx, NULL, info, name); 6452 if (err != 0) 6453 return (err); 6454 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6455 res = irq->ii_res; 6456 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6457 6458 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6459 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6460 "tx"); 6461 return (0); 6462 } 6463 6464 void 6465 iflib_led_create(if_ctx_t ctx) 6466 { 6467 6468 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6469 device_get_nameunit(ctx->ifc_dev)); 6470 } 6471 6472 void 6473 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6474 { 6475 6476 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6477 } 6478 6479 void 6480 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6481 { 6482 6483 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6484 } 6485 6486 void 6487 iflib_admin_intr_deferred(if_ctx_t ctx) 6488 { 6489 6490 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6491 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6492 } 6493 6494 void 6495 iflib_iov_intr_deferred(if_ctx_t ctx) 6496 { 6497 6498 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6499 } 6500 6501 void 6502 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6503 { 6504 6505 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6506 name); 6507 } 6508 6509 void 6510 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6511 const char *name) 6512 { 6513 6514 GROUPTASK_INIT(gtask, 0, fn, ctx); 6515 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6516 name); 6517 } 6518 6519 void 6520 iflib_config_gtask_deinit(struct grouptask *gtask) 6521 { 6522 6523 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6524 } 6525 6526 void 6527 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6528 { 6529 if_t ifp = ctx->ifc_ifp; 6530 iflib_txq_t txq = ctx->ifc_txqs; 6531 6532 if_setbaudrate(ifp, baudrate); 6533 if (baudrate >= IF_Gbps(10)) { 6534 STATE_LOCK(ctx); 6535 ctx->ifc_flags |= IFC_PREFETCH; 6536 STATE_UNLOCK(ctx); 6537 } 6538 /* If link down, disable watchdog */ 6539 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6540 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6541 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6542 } 6543 ctx->ifc_link_state = link_state; 6544 if_link_state_change(ifp, link_state); 6545 } 6546 6547 static int 6548 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6549 { 6550 int credits; 6551 #ifdef INVARIANTS 6552 int credits_pre = txq->ift_cidx_processed; 6553 #endif 6554 6555 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6556 BUS_DMASYNC_POSTREAD); 6557 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6558 return (0); 6559 6560 txq->ift_processed += credits; 6561 txq->ift_cidx_processed += credits; 6562 6563 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6564 if (txq->ift_cidx_processed >= txq->ift_size) 6565 txq->ift_cidx_processed -= txq->ift_size; 6566 return (credits); 6567 } 6568 6569 static int 6570 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6571 { 6572 iflib_fl_t fl; 6573 u_int i; 6574 6575 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6576 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6577 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6578 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6579 budget)); 6580 } 6581 6582 void 6583 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6584 const char *description, if_int_delay_info_t info, 6585 int offset, int value) 6586 { 6587 info->iidi_ctx = ctx; 6588 info->iidi_offset = offset; 6589 info->iidi_value = value; 6590 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6591 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6592 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6593 info, 0, iflib_sysctl_int_delay, "I", description); 6594 } 6595 6596 struct sx * 6597 iflib_ctx_lock_get(if_ctx_t ctx) 6598 { 6599 6600 return (&ctx->ifc_ctx_sx); 6601 } 6602 6603 static int 6604 iflib_msix_init(if_ctx_t ctx) 6605 { 6606 device_t dev = ctx->ifc_dev; 6607 if_shared_ctx_t sctx = ctx->ifc_sctx; 6608 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6609 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6610 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6611 6612 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6613 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6614 6615 if (bootverbose) 6616 device_printf(dev, "msix_init qsets capped at %d\n", 6617 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6618 6619 /* Override by tuneable */ 6620 if (scctx->isc_disable_msix) 6621 goto msi; 6622 6623 /* First try MSI-X */ 6624 if ((msgs = pci_msix_count(dev)) == 0) { 6625 if (bootverbose) 6626 device_printf(dev, "MSI-X not supported or disabled\n"); 6627 goto msi; 6628 } 6629 6630 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6631 /* 6632 * bar == -1 => "trust me I know what I'm doing" 6633 * Some drivers are for hardware that is so shoddily 6634 * documented that no one knows which bars are which 6635 * so the developer has to map all bars. This hack 6636 * allows shoddy garbage to use MSI-X in this framework. 6637 */ 6638 if (bar != -1) { 6639 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6640 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6641 if (ctx->ifc_msix_mem == NULL) { 6642 device_printf(dev, "Unable to map MSI-X table\n"); 6643 goto msi; 6644 } 6645 } 6646 6647 admincnt = sctx->isc_admin_intrcnt; 6648 #if IFLIB_DEBUG 6649 /* use only 1 qset in debug mode */ 6650 queuemsgs = min(msgs - admincnt, 1); 6651 #else 6652 queuemsgs = msgs - admincnt; 6653 #endif 6654 #ifdef RSS 6655 queues = imin(queuemsgs, rss_getnumbuckets()); 6656 #else 6657 queues = queuemsgs; 6658 #endif 6659 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6660 if (bootverbose) 6661 device_printf(dev, 6662 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6663 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6664 #ifdef RSS 6665 /* If we're doing RSS, clamp at the number of RSS buckets */ 6666 if (queues > rss_getnumbuckets()) 6667 queues = rss_getnumbuckets(); 6668 #endif 6669 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6670 rx_queues = iflib_num_rx_queues; 6671 else 6672 rx_queues = queues; 6673 6674 if (rx_queues > scctx->isc_nrxqsets) 6675 rx_queues = scctx->isc_nrxqsets; 6676 6677 /* 6678 * We want this to be all logical CPUs by default 6679 */ 6680 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6681 tx_queues = iflib_num_tx_queues; 6682 else 6683 tx_queues = mp_ncpus; 6684 6685 if (tx_queues > scctx->isc_ntxqsets) 6686 tx_queues = scctx->isc_ntxqsets; 6687 6688 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6689 #ifdef INVARIANTS 6690 if (tx_queues != rx_queues) 6691 device_printf(dev, 6692 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6693 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6694 #endif 6695 tx_queues = min(rx_queues, tx_queues); 6696 rx_queues = min(rx_queues, tx_queues); 6697 } 6698 6699 vectors = rx_queues + admincnt; 6700 if (msgs < vectors) { 6701 device_printf(dev, 6702 "insufficient number of MSI-X vectors " 6703 "(supported %d, need %d)\n", msgs, vectors); 6704 goto msi; 6705 } 6706 6707 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6708 tx_queues); 6709 msgs = vectors; 6710 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6711 if (vectors != msgs) { 6712 device_printf(dev, 6713 "Unable to allocate sufficient MSI-X vectors " 6714 "(got %d, need %d)\n", vectors, msgs); 6715 pci_release_msi(dev); 6716 if (bar != -1) { 6717 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6718 ctx->ifc_msix_mem); 6719 ctx->ifc_msix_mem = NULL; 6720 } 6721 goto msi; 6722 } 6723 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6724 vectors); 6725 scctx->isc_vectors = vectors; 6726 scctx->isc_nrxqsets = rx_queues; 6727 scctx->isc_ntxqsets = tx_queues; 6728 scctx->isc_intr = IFLIB_INTR_MSIX; 6729 6730 return (vectors); 6731 } else { 6732 device_printf(dev, 6733 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6734 err); 6735 if (bar != -1) { 6736 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6737 ctx->ifc_msix_mem); 6738 ctx->ifc_msix_mem = NULL; 6739 } 6740 } 6741 6742 msi: 6743 vectors = pci_msi_count(dev); 6744 scctx->isc_nrxqsets = 1; 6745 scctx->isc_ntxqsets = 1; 6746 scctx->isc_vectors = vectors; 6747 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6748 device_printf(dev,"Using an MSI interrupt\n"); 6749 scctx->isc_intr = IFLIB_INTR_MSI; 6750 } else { 6751 scctx->isc_vectors = 1; 6752 device_printf(dev,"Using a Legacy interrupt\n"); 6753 scctx->isc_intr = IFLIB_INTR_LEGACY; 6754 } 6755 6756 return (vectors); 6757 } 6758 6759 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6760 6761 static int 6762 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6763 { 6764 int rc; 6765 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6766 struct sbuf *sb; 6767 const char *ring_state = "UNKNOWN"; 6768 6769 /* XXX needed ? */ 6770 rc = sysctl_wire_old_buffer(req, 0); 6771 MPASS(rc == 0); 6772 if (rc != 0) 6773 return (rc); 6774 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6775 MPASS(sb != NULL); 6776 if (sb == NULL) 6777 return (ENOMEM); 6778 if (state[3] <= 3) 6779 ring_state = ring_states[state[3]]; 6780 6781 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6782 state[0], state[1], state[2], ring_state); 6783 rc = sbuf_finish(sb); 6784 sbuf_delete(sb); 6785 return(rc); 6786 } 6787 6788 enum iflib_ndesc_handler { 6789 IFLIB_NTXD_HANDLER, 6790 IFLIB_NRXD_HANDLER, 6791 }; 6792 6793 static int 6794 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6795 { 6796 if_ctx_t ctx = (void *)arg1; 6797 enum iflib_ndesc_handler type = arg2; 6798 char buf[256] = {0}; 6799 qidx_t *ndesc; 6800 char *p, *next; 6801 int nqs, rc, i; 6802 6803 nqs = 8; 6804 switch(type) { 6805 case IFLIB_NTXD_HANDLER: 6806 ndesc = ctx->ifc_sysctl_ntxds; 6807 if (ctx->ifc_sctx) 6808 nqs = ctx->ifc_sctx->isc_ntxqs; 6809 break; 6810 case IFLIB_NRXD_HANDLER: 6811 ndesc = ctx->ifc_sysctl_nrxds; 6812 if (ctx->ifc_sctx) 6813 nqs = ctx->ifc_sctx->isc_nrxqs; 6814 break; 6815 default: 6816 printf("%s: unhandled type\n", __func__); 6817 return (EINVAL); 6818 } 6819 if (nqs == 0) 6820 nqs = 8; 6821 6822 for (i=0; i<8; i++) { 6823 if (i >= nqs) 6824 break; 6825 if (i) 6826 strcat(buf, ","); 6827 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6828 } 6829 6830 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6831 if (rc || req->newptr == NULL) 6832 return rc; 6833 6834 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6835 i++, p = strsep(&next, " ,")) { 6836 ndesc[i] = strtoul(p, NULL, 10); 6837 } 6838 6839 return(rc); 6840 } 6841 6842 #define NAME_BUFLEN 32 6843 static void 6844 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6845 { 6846 device_t dev = iflib_get_dev(ctx); 6847 struct sysctl_oid_list *child, *oid_list; 6848 struct sysctl_ctx_list *ctx_list; 6849 struct sysctl_oid *node; 6850 6851 ctx_list = device_get_sysctl_ctx(dev); 6852 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6853 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6854 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6855 oid_list = SYSCTL_CHILDREN(node); 6856 6857 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6858 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6859 "driver version"); 6860 6861 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6862 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6863 "# of txqs to use, 0 => use default #"); 6864 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6865 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6866 "# of rxqs to use, 0 => use default #"); 6867 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6868 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6869 "permit #txq != #rxq"); 6870 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6871 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6872 "disable MSI-X (default 0)"); 6873 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6874 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6875 "set the RX budget"); 6876 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6877 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6878 "cause TX to abdicate instead of running to completion"); 6879 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6880 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6881 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6882 "offset to start using cores at"); 6883 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6884 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6885 "use separate cores for TX and RX"); 6886 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "use_logical_cores", 6887 CTLFLAG_RDTUN, &ctx->ifc_sysctl_use_logical_cores, 0, 6888 "try to make use of logical cores for TX and RX"); 6889 6890 /* XXX change for per-queue sizes */ 6891 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6892 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6893 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6894 "list of # of TX descriptors to use, 0 = use default #"); 6895 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6896 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6897 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6898 "list of # of RX descriptors to use, 0 = use default #"); 6899 } 6900 6901 static void 6902 iflib_add_device_sysctl_post(if_ctx_t ctx) 6903 { 6904 if_shared_ctx_t sctx = ctx->ifc_sctx; 6905 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6906 device_t dev = iflib_get_dev(ctx); 6907 struct sysctl_oid_list *child; 6908 struct sysctl_ctx_list *ctx_list; 6909 iflib_fl_t fl; 6910 iflib_txq_t txq; 6911 iflib_rxq_t rxq; 6912 int i, j; 6913 char namebuf[NAME_BUFLEN]; 6914 char *qfmt; 6915 struct sysctl_oid *queue_node, *fl_node, *node; 6916 struct sysctl_oid_list *queue_list, *fl_list; 6917 ctx_list = device_get_sysctl_ctx(dev); 6918 6919 node = ctx->ifc_sysctl_node; 6920 child = SYSCTL_CHILDREN(node); 6921 6922 if (scctx->isc_ntxqsets > 100) 6923 qfmt = "txq%03d"; 6924 else if (scctx->isc_ntxqsets > 10) 6925 qfmt = "txq%02d"; 6926 else 6927 qfmt = "txq%d"; 6928 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6929 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6930 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6931 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6932 queue_list = SYSCTL_CHILDREN(queue_node); 6933 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 6934 CTLFLAG_RD, 6935 &txq->ift_task.gt_cpu, 0, "cpu this queue is bound to"); 6936 #if MEMORY_LOGGING 6937 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6938 CTLFLAG_RD, 6939 &txq->ift_dequeued, "total mbufs freed"); 6940 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6941 CTLFLAG_RD, 6942 &txq->ift_enqueued, "total mbufs enqueued"); 6943 #endif 6944 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6945 CTLFLAG_RD, 6946 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6947 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6948 CTLFLAG_RD, 6949 &txq->ift_pullups, "# of times m_pullup was called"); 6950 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6951 CTLFLAG_RD, 6952 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6953 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6954 CTLFLAG_RD, 6955 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6956 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6957 CTLFLAG_RD, 6958 &txq->ift_map_failed, "# of times DMA map failed"); 6959 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6960 CTLFLAG_RD, 6961 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6962 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6963 CTLFLAG_RD, 6964 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6965 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6966 CTLFLAG_RD, 6967 &txq->ift_pidx, 1, "Producer Index"); 6968 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6969 CTLFLAG_RD, 6970 &txq->ift_cidx, 1, "Consumer Index"); 6971 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6972 CTLFLAG_RD, 6973 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6974 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6975 CTLFLAG_RD, 6976 &txq->ift_in_use, 1, "descriptors in use"); 6977 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6978 CTLFLAG_RD, 6979 &txq->ift_processed, "descriptors procesed for clean"); 6980 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6981 CTLFLAG_RD, 6982 &txq->ift_cleaned, "total cleaned"); 6983 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6984 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6985 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6986 mp_ring_state_handler, "A", "soft ring state"); 6987 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6988 CTLFLAG_RD, &txq->ift_br->enqueues, 6989 "# of enqueues to the mp_ring for this queue"); 6990 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6991 CTLFLAG_RD, &txq->ift_br->drops, 6992 "# of drops in the mp_ring for this queue"); 6993 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6994 CTLFLAG_RD, &txq->ift_br->starts, 6995 "# of normal consumer starts in the mp_ring for this queue"); 6996 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6997 CTLFLAG_RD, &txq->ift_br->stalls, 6998 "# of consumer stalls in the mp_ring for this queue"); 6999 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 7000 CTLFLAG_RD, &txq->ift_br->restarts, 7001 "# of consumer restarts in the mp_ring for this queue"); 7002 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 7003 CTLFLAG_RD, &txq->ift_br->abdications, 7004 "# of consumer abdications in the mp_ring for this queue"); 7005 } 7006 7007 if (scctx->isc_nrxqsets > 100) 7008 qfmt = "rxq%03d"; 7009 else if (scctx->isc_nrxqsets > 10) 7010 qfmt = "rxq%02d"; 7011 else 7012 qfmt = "rxq%d"; 7013 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 7014 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 7015 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 7016 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 7017 queue_list = SYSCTL_CHILDREN(queue_node); 7018 SYSCTL_ADD_INT(ctx_list, queue_list, OID_AUTO, "cpu", 7019 CTLFLAG_RD, 7020 &rxq->ifr_task.gt_cpu, 0, "cpu this queue is bound to"); 7021 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 7022 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 7023 CTLFLAG_RD, 7024 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 7025 } 7026 7027 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 7028 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 7029 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 7030 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 7031 fl_list = SYSCTL_CHILDREN(fl_node); 7032 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 7033 CTLFLAG_RD, 7034 &fl->ifl_pidx, 1, "Producer Index"); 7035 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 7036 CTLFLAG_RD, 7037 &fl->ifl_cidx, 1, "Consumer Index"); 7038 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 7039 CTLFLAG_RD, 7040 &fl->ifl_credits, 1, "credits available"); 7041 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 7042 CTLFLAG_RD, 7043 &fl->ifl_buf_size, 1, "buffer size"); 7044 #if MEMORY_LOGGING 7045 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 7046 CTLFLAG_RD, 7047 &fl->ifl_m_enqueued, "mbufs allocated"); 7048 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 7049 CTLFLAG_RD, 7050 &fl->ifl_m_dequeued, "mbufs freed"); 7051 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 7052 CTLFLAG_RD, 7053 &fl->ifl_cl_enqueued, "clusters allocated"); 7054 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 7055 CTLFLAG_RD, 7056 &fl->ifl_cl_dequeued, "clusters freed"); 7057 #endif 7058 } 7059 } 7060 7061 } 7062 7063 void 7064 iflib_request_reset(if_ctx_t ctx) 7065 { 7066 7067 STATE_LOCK(ctx); 7068 ctx->ifc_flags |= IFC_DO_RESET; 7069 STATE_UNLOCK(ctx); 7070 } 7071 7072 #ifndef __NO_STRICT_ALIGNMENT 7073 static struct mbuf * 7074 iflib_fixup_rx(struct mbuf *m) 7075 { 7076 struct mbuf *n; 7077 7078 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 7079 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 7080 m->m_data += ETHER_HDR_LEN; 7081 n = m; 7082 } else { 7083 MGETHDR(n, M_NOWAIT, MT_DATA); 7084 if (n == NULL) { 7085 m_freem(m); 7086 return (NULL); 7087 } 7088 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 7089 m->m_data += ETHER_HDR_LEN; 7090 m->m_len -= ETHER_HDR_LEN; 7091 n->m_len = ETHER_HDR_LEN; 7092 M_MOVE_PKTHDR(n, m); 7093 n->m_next = m; 7094 } 7095 return (n); 7096 } 7097 #endif 7098 7099 #ifdef DEBUGNET 7100 static void 7101 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 7102 { 7103 if_ctx_t ctx; 7104 7105 ctx = if_getsoftc(ifp); 7106 CTX_LOCK(ctx); 7107 *nrxr = NRXQSETS(ctx); 7108 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 7109 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 7110 CTX_UNLOCK(ctx); 7111 } 7112 7113 static void 7114 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 7115 { 7116 if_ctx_t ctx; 7117 if_softc_ctx_t scctx; 7118 iflib_fl_t fl; 7119 iflib_rxq_t rxq; 7120 int i, j; 7121 7122 ctx = if_getsoftc(ifp); 7123 scctx = &ctx->ifc_softc_ctx; 7124 7125 switch (event) { 7126 case DEBUGNET_START: 7127 for (i = 0; i < scctx->isc_nrxqsets; i++) { 7128 rxq = &ctx->ifc_rxqs[i]; 7129 for (j = 0; j < rxq->ifr_nfl; j++) { 7130 fl = rxq->ifr_fl; 7131 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 7132 } 7133 } 7134 iflib_no_tx_batch = 1; 7135 break; 7136 default: 7137 break; 7138 } 7139 } 7140 7141 static int 7142 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 7143 { 7144 if_ctx_t ctx; 7145 iflib_txq_t txq; 7146 int error; 7147 7148 ctx = if_getsoftc(ifp); 7149 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7150 IFF_DRV_RUNNING) 7151 return (EBUSY); 7152 7153 txq = &ctx->ifc_txqs[0]; 7154 error = iflib_encap(txq, &m); 7155 if (error == 0) 7156 (void)iflib_txd_db_check(txq, true); 7157 return (error); 7158 } 7159 7160 static int 7161 iflib_debugnet_poll(if_t ifp, int count) 7162 { 7163 struct epoch_tracker et; 7164 if_ctx_t ctx; 7165 if_softc_ctx_t scctx; 7166 iflib_txq_t txq; 7167 int i; 7168 7169 ctx = if_getsoftc(ifp); 7170 scctx = &ctx->ifc_softc_ctx; 7171 7172 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 7173 IFF_DRV_RUNNING) 7174 return (EBUSY); 7175 7176 txq = &ctx->ifc_txqs[0]; 7177 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 7178 7179 NET_EPOCH_ENTER(et); 7180 for (i = 0; i < scctx->isc_nrxqsets; i++) 7181 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 7182 NET_EPOCH_EXIT(et); 7183 return (0); 7184 } 7185 #endif /* DEBUGNET */ 7186