1 /*- 2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Neither the name of Matthew Macy nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_inet.h" 32 #include "opt_inet6.h" 33 #include "opt_acpi.h" 34 #include "opt_sched.h" 35 36 #include <sys/param.h> 37 #include <sys/types.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/mutex.h> 43 #include <sys/module.h> 44 #include <sys/kobj.h> 45 #include <sys/rman.h> 46 #include <sys/sbuf.h> 47 #include <sys/smp.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/syslog.h> 52 #include <sys/taskqueue.h> 53 #include <sys/limits.h> 54 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_types.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 #include <net/ethernet.h> 61 #include <net/mp_ring.h> 62 #include <net/debugnet.h> 63 #include <net/pfil.h> 64 #include <net/vnet.h> 65 66 #include <netinet/in.h> 67 #include <netinet/in_pcb.h> 68 #include <netinet/tcp_lro.h> 69 #include <netinet/in_systm.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/ip_var.h> 75 #include <netinet6/ip6_var.h> 76 77 #include <machine/bus.h> 78 #include <machine/in_cksum.h> 79 80 #include <vm/vm.h> 81 #include <vm/pmap.h> 82 83 #include <dev/led/led.h> 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pci_private.h> 87 88 #include <net/iflib.h> 89 #include <net/iflib_private.h> 90 91 #include "ifdi_if.h" 92 93 #ifdef PCI_IOV 94 #include <dev/pci/pci_iov.h> 95 #endif 96 97 #include <sys/bitstring.h> 98 /* 99 * enable accounting of every mbuf as it comes in to and goes out of 100 * iflib's software descriptor references 101 */ 102 #define MEMORY_LOGGING 0 103 /* 104 * Enable mbuf vectors for compressing long mbuf chains 105 */ 106 107 /* 108 * NB: 109 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead 110 * we prefetch needs to be determined by the time spent in m_free vis a vis 111 * the cost of a prefetch. This will of course vary based on the workload: 112 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which 113 * is quite expensive, thus suggesting very little prefetch. 114 * - small packet forwarding which is just returning a single mbuf to 115 * UMA will typically be very fast vis a vis the cost of a memory 116 * access. 117 */ 118 119 120 /* 121 * File organization: 122 * - private structures 123 * - iflib private utility functions 124 * - ifnet functions 125 * - vlan registry and other exported functions 126 * - iflib public core functions 127 * 128 * 129 */ 130 MALLOC_DEFINE(M_IFLIB, "iflib", "ifnet library"); 131 132 #define IFLIB_RXEOF_MORE (1U << 0) 133 #define IFLIB_RXEOF_EMPTY (2U << 0) 134 135 struct iflib_txq; 136 typedef struct iflib_txq *iflib_txq_t; 137 struct iflib_rxq; 138 typedef struct iflib_rxq *iflib_rxq_t; 139 struct iflib_fl; 140 typedef struct iflib_fl *iflib_fl_t; 141 142 struct iflib_ctx; 143 144 static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); 145 static void iflib_timer(void *arg); 146 147 typedef struct iflib_filter_info { 148 driver_filter_t *ifi_filter; 149 void *ifi_filter_arg; 150 struct grouptask *ifi_task; 151 void *ifi_ctx; 152 } *iflib_filter_info_t; 153 154 struct iflib_ctx { 155 KOBJ_FIELDS; 156 /* 157 * Pointer to hardware driver's softc 158 */ 159 void *ifc_softc; 160 device_t ifc_dev; 161 if_t ifc_ifp; 162 163 cpuset_t ifc_cpus; 164 if_shared_ctx_t ifc_sctx; 165 struct if_softc_ctx ifc_softc_ctx; 166 167 struct sx ifc_ctx_sx; 168 struct mtx ifc_state_mtx; 169 170 iflib_txq_t ifc_txqs; 171 iflib_rxq_t ifc_rxqs; 172 uint32_t ifc_if_flags; 173 uint32_t ifc_flags; 174 uint32_t ifc_max_fl_buf_size; 175 uint32_t ifc_rx_mbuf_sz; 176 177 int ifc_link_state; 178 int ifc_watchdog_events; 179 struct cdev *ifc_led_dev; 180 struct resource *ifc_msix_mem; 181 182 struct if_irq ifc_legacy_irq; 183 struct grouptask ifc_admin_task; 184 struct grouptask ifc_vflr_task; 185 struct iflib_filter_info ifc_filter_info; 186 struct ifmedia ifc_media; 187 struct ifmedia *ifc_mediap; 188 189 struct sysctl_oid *ifc_sysctl_node; 190 uint16_t ifc_sysctl_ntxqs; 191 uint16_t ifc_sysctl_nrxqs; 192 uint16_t ifc_sysctl_qs_eq_override; 193 uint16_t ifc_sysctl_rx_budget; 194 uint16_t ifc_sysctl_tx_abdicate; 195 uint16_t ifc_sysctl_core_offset; 196 #define CORE_OFFSET_UNSPECIFIED 0xffff 197 uint8_t ifc_sysctl_separate_txrx; 198 199 qidx_t ifc_sysctl_ntxds[8]; 200 qidx_t ifc_sysctl_nrxds[8]; 201 struct if_txrx ifc_txrx; 202 #define isc_txd_encap ifc_txrx.ift_txd_encap 203 #define isc_txd_flush ifc_txrx.ift_txd_flush 204 #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update 205 #define isc_rxd_available ifc_txrx.ift_rxd_available 206 #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get 207 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 208 #define isc_rxd_flush ifc_txrx.ift_rxd_flush 209 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 210 #define isc_rxd_refill ifc_txrx.ift_rxd_refill 211 #define isc_legacy_intr ifc_txrx.ift_legacy_intr 212 eventhandler_tag ifc_vlan_attach_event; 213 eventhandler_tag ifc_vlan_detach_event; 214 struct ether_addr ifc_mac; 215 }; 216 217 void * 218 iflib_get_softc(if_ctx_t ctx) 219 { 220 221 return (ctx->ifc_softc); 222 } 223 224 device_t 225 iflib_get_dev(if_ctx_t ctx) 226 { 227 228 return (ctx->ifc_dev); 229 } 230 231 if_t 232 iflib_get_ifp(if_ctx_t ctx) 233 { 234 235 return (ctx->ifc_ifp); 236 } 237 238 struct ifmedia * 239 iflib_get_media(if_ctx_t ctx) 240 { 241 242 return (ctx->ifc_mediap); 243 } 244 245 uint32_t 246 iflib_get_flags(if_ctx_t ctx) 247 { 248 return (ctx->ifc_flags); 249 } 250 251 void 252 iflib_set_mac(if_ctx_t ctx, uint8_t mac[ETHER_ADDR_LEN]) 253 { 254 255 bcopy(mac, ctx->ifc_mac.octet, ETHER_ADDR_LEN); 256 } 257 258 if_softc_ctx_t 259 iflib_get_softc_ctx(if_ctx_t ctx) 260 { 261 262 return (&ctx->ifc_softc_ctx); 263 } 264 265 if_shared_ctx_t 266 iflib_get_sctx(if_ctx_t ctx) 267 { 268 269 return (ctx->ifc_sctx); 270 } 271 272 #define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) 273 #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) 274 #define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) 275 276 #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) 277 #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) 278 279 typedef struct iflib_sw_rx_desc_array { 280 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 281 struct mbuf **ifsd_m; /* pkthdr mbufs */ 282 caddr_t *ifsd_cl; /* direct cluster pointer for rx */ 283 bus_addr_t *ifsd_ba; /* bus addr of cluster for rx */ 284 } iflib_rxsd_array_t; 285 286 typedef struct iflib_sw_tx_desc_array { 287 bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ 288 bus_dmamap_t *ifsd_tso_map; /* bus_dma maps for TSO packet */ 289 struct mbuf **ifsd_m; /* pkthdr mbufs */ 290 } if_txsd_vec_t; 291 292 /* magic number that should be high enough for any hardware */ 293 #define IFLIB_MAX_TX_SEGS 128 294 #define IFLIB_RX_COPY_THRESH 128 295 #define IFLIB_MAX_RX_REFRESH 32 296 /* The minimum descriptors per second before we start coalescing */ 297 #define IFLIB_MIN_DESC_SEC 16384 298 #define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 299 #define IFLIB_QUEUE_IDLE 0 300 #define IFLIB_QUEUE_HUNG 1 301 #define IFLIB_QUEUE_WORKING 2 302 /* maximum number of txqs that can share an rx interrupt */ 303 #define IFLIB_MAX_TX_SHARED_INTR 4 304 305 /* this should really scale with ring size - this is a fairly arbitrary value */ 306 #define TX_BATCH_SIZE 32 307 308 #define IFLIB_RESTART_BUDGET 8 309 310 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 311 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 312 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 313 314 struct iflib_txq { 315 qidx_t ift_in_use; 316 qidx_t ift_cidx; 317 qidx_t ift_cidx_processed; 318 qidx_t ift_pidx; 319 uint8_t ift_gen; 320 uint8_t ift_br_offset; 321 uint16_t ift_npending; 322 uint16_t ift_db_pending; 323 uint16_t ift_rs_pending; 324 /* implicit pad */ 325 uint8_t ift_txd_size[8]; 326 uint64_t ift_processed; 327 uint64_t ift_cleaned; 328 uint64_t ift_cleaned_prev; 329 #if MEMORY_LOGGING 330 uint64_t ift_enqueued; 331 uint64_t ift_dequeued; 332 #endif 333 uint64_t ift_no_tx_dma_setup; 334 uint64_t ift_no_desc_avail; 335 uint64_t ift_mbuf_defrag_failed; 336 uint64_t ift_mbuf_defrag; 337 uint64_t ift_map_failed; 338 uint64_t ift_txd_encap_efbig; 339 uint64_t ift_pullups; 340 uint64_t ift_last_timer_tick; 341 342 struct mtx ift_mtx; 343 struct mtx ift_db_mtx; 344 345 /* constant values */ 346 if_ctx_t ift_ctx; 347 struct ifmp_ring *ift_br; 348 struct grouptask ift_task; 349 qidx_t ift_size; 350 uint16_t ift_id; 351 struct callout ift_timer; 352 353 if_txsd_vec_t ift_sds; 354 uint8_t ift_qstatus; 355 uint8_t ift_closed; 356 uint8_t ift_update_freq; 357 struct iflib_filter_info ift_filter_info; 358 bus_dma_tag_t ift_buf_tag; 359 bus_dma_tag_t ift_tso_buf_tag; 360 iflib_dma_info_t ift_ifdi; 361 #define MTX_NAME_LEN 32 362 char ift_mtx_name[MTX_NAME_LEN]; 363 bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); 364 #ifdef IFLIB_DIAGNOSTICS 365 uint64_t ift_cpu_exec_count[256]; 366 #endif 367 } __aligned(CACHE_LINE_SIZE); 368 369 struct iflib_fl { 370 qidx_t ifl_cidx; 371 qidx_t ifl_pidx; 372 qidx_t ifl_credits; 373 uint8_t ifl_gen; 374 uint8_t ifl_rxd_size; 375 #if MEMORY_LOGGING 376 uint64_t ifl_m_enqueued; 377 uint64_t ifl_m_dequeued; 378 uint64_t ifl_cl_enqueued; 379 uint64_t ifl_cl_dequeued; 380 #endif 381 /* implicit pad */ 382 bitstr_t *ifl_rx_bitmap; 383 qidx_t ifl_fragidx; 384 /* constant */ 385 qidx_t ifl_size; 386 uint16_t ifl_buf_size; 387 uint16_t ifl_cltype; 388 uma_zone_t ifl_zone; 389 iflib_rxsd_array_t ifl_sds; 390 iflib_rxq_t ifl_rxq; 391 uint8_t ifl_id; 392 bus_dma_tag_t ifl_buf_tag; 393 iflib_dma_info_t ifl_ifdi; 394 uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); 395 caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; 396 qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; 397 } __aligned(CACHE_LINE_SIZE); 398 399 static inline qidx_t 400 get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) 401 { 402 qidx_t used; 403 404 if (pidx > cidx) 405 used = pidx - cidx; 406 else if (pidx < cidx) 407 used = size - cidx + pidx; 408 else if (gen == 0 && pidx == cidx) 409 used = 0; 410 else if (gen == 1 && pidx == cidx) 411 used = size; 412 else 413 panic("bad state"); 414 415 return (used); 416 } 417 418 #define TXQ_AVAIL(txq) (txq->ift_size - get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, txq->ift_gen)) 419 420 #define IDXDIFF(head, tail, wrap) \ 421 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 422 423 struct iflib_rxq { 424 if_ctx_t ifr_ctx; 425 iflib_fl_t ifr_fl; 426 uint64_t ifr_rx_irq; 427 struct pfil_head *pfil; 428 /* 429 * If there is a separate completion queue (IFLIB_HAS_RXCQ), this is 430 * the command queue consumer index. Otherwise it's unused. 431 */ 432 qidx_t ifr_cq_cidx; 433 uint16_t ifr_id; 434 uint8_t ifr_nfl; 435 uint8_t ifr_ntxqirq; 436 uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; 437 uint8_t ifr_fl_offset; 438 struct lro_ctrl ifr_lc; 439 struct grouptask ifr_task; 440 struct callout ifr_watchdog; 441 struct iflib_filter_info ifr_filter_info; 442 iflib_dma_info_t ifr_ifdi; 443 444 /* dynamically allocate if any drivers need a value substantially larger than this */ 445 struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); 446 #ifdef IFLIB_DIAGNOSTICS 447 uint64_t ifr_cpu_exec_count[256]; 448 #endif 449 } __aligned(CACHE_LINE_SIZE); 450 451 typedef struct if_rxsd { 452 caddr_t *ifsd_cl; 453 iflib_fl_t ifsd_fl; 454 } *if_rxsd_t; 455 456 /* multiple of word size */ 457 #ifdef __LP64__ 458 #define PKT_INFO_SIZE 6 459 #define RXD_INFO_SIZE 5 460 #define PKT_TYPE uint64_t 461 #else 462 #define PKT_INFO_SIZE 11 463 #define RXD_INFO_SIZE 8 464 #define PKT_TYPE uint32_t 465 #endif 466 #define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) 467 #define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) 468 469 typedef struct if_pkt_info_pad { 470 PKT_TYPE pkt_val[PKT_INFO_SIZE]; 471 } *if_pkt_info_pad_t; 472 typedef struct if_rxd_info_pad { 473 PKT_TYPE rxd_val[RXD_INFO_SIZE]; 474 } *if_rxd_info_pad_t; 475 476 CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); 477 CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); 478 479 480 static inline void 481 pkt_info_zero(if_pkt_info_t pi) 482 { 483 if_pkt_info_pad_t pi_pad; 484 485 pi_pad = (if_pkt_info_pad_t)pi; 486 pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; 487 pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; 488 #ifndef __LP64__ 489 pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; 490 pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; 491 #endif 492 } 493 494 static device_method_t iflib_pseudo_methods[] = { 495 DEVMETHOD(device_attach, noop_attach), 496 DEVMETHOD(device_detach, iflib_pseudo_detach), 497 DEVMETHOD_END 498 }; 499 500 driver_t iflib_pseudodriver = { 501 "iflib_pseudo", iflib_pseudo_methods, sizeof(struct iflib_ctx), 502 }; 503 504 static inline void 505 rxd_info_zero(if_rxd_info_t ri) 506 { 507 if_rxd_info_pad_t ri_pad; 508 int i; 509 510 ri_pad = (if_rxd_info_pad_t)ri; 511 for (i = 0; i < RXD_LOOP_BOUND; i += 4) { 512 ri_pad->rxd_val[i] = 0; 513 ri_pad->rxd_val[i+1] = 0; 514 ri_pad->rxd_val[i+2] = 0; 515 ri_pad->rxd_val[i+3] = 0; 516 } 517 #ifdef __LP64__ 518 ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; 519 #endif 520 } 521 522 /* 523 * Only allow a single packet to take up most 1/nth of the tx ring 524 */ 525 #define MAX_SINGLE_PACKET_FRACTION 12 526 #define IF_BAD_DMA (bus_addr_t)-1 527 528 #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) 529 530 #define CTX_LOCK_INIT(_sc) sx_init(&(_sc)->ifc_ctx_sx, "iflib ctx lock") 531 #define CTX_LOCK(ctx) sx_xlock(&(ctx)->ifc_ctx_sx) 532 #define CTX_UNLOCK(ctx) sx_xunlock(&(ctx)->ifc_ctx_sx) 533 #define CTX_LOCK_DESTROY(ctx) sx_destroy(&(ctx)->ifc_ctx_sx) 534 535 #define STATE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_state_mtx, _name, "iflib state lock", MTX_DEF) 536 #define STATE_LOCK(ctx) mtx_lock(&(ctx)->ifc_state_mtx) 537 #define STATE_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_state_mtx) 538 #define STATE_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_state_mtx) 539 540 #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) 541 #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) 542 543 void 544 iflib_set_detach(if_ctx_t ctx) 545 { 546 STATE_LOCK(ctx); 547 ctx->ifc_flags |= IFC_IN_DETACH; 548 STATE_UNLOCK(ctx); 549 } 550 551 /* Our boot-time initialization hook */ 552 static int iflib_module_event_handler(module_t, int, void *); 553 554 static moduledata_t iflib_moduledata = { 555 "iflib", 556 iflib_module_event_handler, 557 NULL 558 }; 559 560 DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); 561 MODULE_VERSION(iflib, 1); 562 563 MODULE_DEPEND(iflib, pci, 1, 1, 1); 564 MODULE_DEPEND(iflib, ether, 1, 1, 1); 565 566 TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); 567 TASKQGROUP_DEFINE(if_config_tqg, 1, 1); 568 569 #ifndef IFLIB_DEBUG_COUNTERS 570 #ifdef INVARIANTS 571 #define IFLIB_DEBUG_COUNTERS 1 572 #else 573 #define IFLIB_DEBUG_COUNTERS 0 574 #endif /* !INVARIANTS */ 575 #endif 576 577 static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 578 "iflib driver parameters"); 579 580 /* 581 * XXX need to ensure that this can't accidentally cause the head to be moved backwards 582 */ 583 static int iflib_min_tx_latency = 0; 584 SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, 585 &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); 586 static int iflib_no_tx_batch = 0; 587 SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, 588 &iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); 589 590 591 #if IFLIB_DEBUG_COUNTERS 592 593 static int iflib_tx_seen; 594 static int iflib_tx_sent; 595 static int iflib_tx_encap; 596 static int iflib_rx_allocs; 597 static int iflib_fl_refills; 598 static int iflib_fl_refills_large; 599 static int iflib_tx_frees; 600 601 SYSCTL_INT(_net_iflib, OID_AUTO, tx_seen, CTLFLAG_RD, 602 &iflib_tx_seen, 0, "# TX mbufs seen"); 603 SYSCTL_INT(_net_iflib, OID_AUTO, tx_sent, CTLFLAG_RD, 604 &iflib_tx_sent, 0, "# TX mbufs sent"); 605 SYSCTL_INT(_net_iflib, OID_AUTO, tx_encap, CTLFLAG_RD, 606 &iflib_tx_encap, 0, "# TX mbufs encapped"); 607 SYSCTL_INT(_net_iflib, OID_AUTO, tx_frees, CTLFLAG_RD, 608 &iflib_tx_frees, 0, "# TX frees"); 609 SYSCTL_INT(_net_iflib, OID_AUTO, rx_allocs, CTLFLAG_RD, 610 &iflib_rx_allocs, 0, "# RX allocations"); 611 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills, CTLFLAG_RD, 612 &iflib_fl_refills, 0, "# refills"); 613 SYSCTL_INT(_net_iflib, OID_AUTO, fl_refills_large, CTLFLAG_RD, 614 &iflib_fl_refills_large, 0, "# large refills"); 615 616 617 static int iflib_txq_drain_flushing; 618 static int iflib_txq_drain_oactive; 619 static int iflib_txq_drain_notready; 620 621 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_flushing, CTLFLAG_RD, 622 &iflib_txq_drain_flushing, 0, "# drain flushes"); 623 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, 624 &iflib_txq_drain_oactive, 0, "# drain oactives"); 625 SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, 626 &iflib_txq_drain_notready, 0, "# drain notready"); 627 628 629 static int iflib_encap_load_mbuf_fail; 630 static int iflib_encap_pad_mbuf_fail; 631 static int iflib_encap_txq_avail_fail; 632 static int iflib_encap_txd_encap_fail; 633 634 SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, 635 &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); 636 SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, 637 &iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); 638 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, 639 &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); 640 SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, 641 &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); 642 643 static int iflib_task_fn_rxs; 644 static int iflib_rx_intr_enables; 645 static int iflib_fast_intrs; 646 static int iflib_rx_unavail; 647 static int iflib_rx_ctx_inactive; 648 static int iflib_rx_if_input; 649 static int iflib_rxd_flush; 650 651 static int iflib_verbose_debug; 652 653 SYSCTL_INT(_net_iflib, OID_AUTO, task_fn_rx, CTLFLAG_RD, 654 &iflib_task_fn_rxs, 0, "# task_fn_rx calls"); 655 SYSCTL_INT(_net_iflib, OID_AUTO, rx_intr_enables, CTLFLAG_RD, 656 &iflib_rx_intr_enables, 0, "# RX intr enables"); 657 SYSCTL_INT(_net_iflib, OID_AUTO, fast_intrs, CTLFLAG_RD, 658 &iflib_fast_intrs, 0, "# fast_intr calls"); 659 SYSCTL_INT(_net_iflib, OID_AUTO, rx_unavail, CTLFLAG_RD, 660 &iflib_rx_unavail, 0, "# times rxeof called with no available data"); 661 SYSCTL_INT(_net_iflib, OID_AUTO, rx_ctx_inactive, CTLFLAG_RD, 662 &iflib_rx_ctx_inactive, 0, "# times rxeof called with inactive context"); 663 SYSCTL_INT(_net_iflib, OID_AUTO, rx_if_input, CTLFLAG_RD, 664 &iflib_rx_if_input, 0, "# times rxeof called if_input"); 665 SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, 666 &iflib_rxd_flush, 0, "# times rxd_flush called"); 667 SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, 668 &iflib_verbose_debug, 0, "enable verbose debugging"); 669 670 #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) 671 static void 672 iflib_debug_reset(void) 673 { 674 iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = 675 iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = 676 iflib_txq_drain_flushing = iflib_txq_drain_oactive = 677 iflib_txq_drain_notready = 678 iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = 679 iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = 680 iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = 681 iflib_rx_unavail = 682 iflib_rx_ctx_inactive = iflib_rx_if_input = 683 iflib_rxd_flush = 0; 684 } 685 686 #else 687 #define DBG_COUNTER_INC(name) 688 static void iflib_debug_reset(void) {} 689 #endif 690 691 #define IFLIB_DEBUG 0 692 693 static void iflib_tx_structures_free(if_ctx_t ctx); 694 static void iflib_rx_structures_free(if_ctx_t ctx); 695 static int iflib_queues_alloc(if_ctx_t ctx); 696 static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); 697 static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); 698 static int iflib_qset_structures_setup(if_ctx_t ctx); 699 static int iflib_msix_init(if_ctx_t ctx); 700 static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, const char *str); 701 static void iflib_txq_check_drain(iflib_txq_t txq, int budget); 702 static uint32_t iflib_txq_can_drain(struct ifmp_ring *); 703 #ifdef ALTQ 704 static void iflib_altq_if_start(if_t ifp); 705 static int iflib_altq_if_transmit(if_t ifp, struct mbuf *m); 706 #endif 707 static int iflib_register(if_ctx_t); 708 static void iflib_deregister(if_ctx_t); 709 static void iflib_unregister_vlan_handlers(if_ctx_t ctx); 710 static uint16_t iflib_get_mbuf_size_for(unsigned int size); 711 static void iflib_init_locked(if_ctx_t ctx); 712 static void iflib_add_device_sysctl_pre(if_ctx_t ctx); 713 static void iflib_add_device_sysctl_post(if_ctx_t ctx); 714 static void iflib_ifmp_purge(iflib_txq_t txq); 715 static void _iflib_pre_assert(if_softc_ctx_t scctx); 716 static void iflib_if_init_locked(if_ctx_t ctx); 717 static void iflib_free_intr_mem(if_ctx_t ctx); 718 #ifndef __NO_STRICT_ALIGNMENT 719 static struct mbuf * iflib_fixup_rx(struct mbuf *m); 720 #endif 721 722 static SLIST_HEAD(cpu_offset_list, cpu_offset) cpu_offsets = 723 SLIST_HEAD_INITIALIZER(cpu_offsets); 724 struct cpu_offset { 725 SLIST_ENTRY(cpu_offset) entries; 726 cpuset_t set; 727 unsigned int refcount; 728 uint16_t offset; 729 }; 730 static struct mtx cpu_offset_mtx; 731 MTX_SYSINIT(iflib_cpu_offset, &cpu_offset_mtx, "iflib_cpu_offset lock", 732 MTX_DEF); 733 734 DEBUGNET_DEFINE(iflib); 735 736 #ifdef DEV_NETMAP 737 #include <sys/selinfo.h> 738 #include <net/netmap.h> 739 #include <dev/netmap/netmap_kern.h> 740 741 MODULE_DEPEND(iflib, netmap, 1, 1, 1); 742 743 static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); 744 745 /* 746 * device-specific sysctl variables: 747 * 748 * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. 749 * During regular operations the CRC is stripped, but on some 750 * hardware reception of frames not multiple of 64 is slower, 751 * so using crcstrip=0 helps in benchmarks. 752 * 753 * iflib_rx_miss, iflib_rx_miss_bufs: 754 * count packets that might be missed due to lost interrupts. 755 */ 756 SYSCTL_DECL(_dev_netmap); 757 /* 758 * The xl driver by default strips CRCs and we do not override it. 759 */ 760 761 int iflib_crcstrip = 1; 762 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_crcstrip, 763 CTLFLAG_RW, &iflib_crcstrip, 1, "strip CRC on RX frames"); 764 765 int iflib_rx_miss, iflib_rx_miss_bufs; 766 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss, 767 CTLFLAG_RW, &iflib_rx_miss, 0, "potentially missed RX intr"); 768 SYSCTL_INT(_dev_netmap, OID_AUTO, iflib_rx_miss_bufs, 769 CTLFLAG_RW, &iflib_rx_miss_bufs, 0, "potentially missed RX intr bufs"); 770 771 /* 772 * Register/unregister. We are already under netmap lock. 773 * Only called on the first register or the last unregister. 774 */ 775 static int 776 iflib_netmap_register(struct netmap_adapter *na, int onoff) 777 { 778 if_t ifp = na->ifp; 779 if_ctx_t ctx = ifp->if_softc; 780 int status; 781 782 CTX_LOCK(ctx); 783 IFDI_INTR_DISABLE(ctx); 784 785 /* Tell the stack that the interface is no longer active */ 786 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 787 788 if (!CTX_IS_VF(ctx)) 789 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); 790 791 /* enable or disable flags and callbacks in na and ifp */ 792 if (onoff) { 793 nm_set_native_flags(na); 794 } else { 795 nm_clear_native_flags(na); 796 } 797 iflib_stop(ctx); 798 iflib_init_locked(ctx); 799 IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? 800 status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; 801 if (status) 802 nm_clear_native_flags(na); 803 CTX_UNLOCK(ctx); 804 return (status); 805 } 806 807 static int 808 netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) 809 { 810 struct netmap_adapter *na = kring->na; 811 u_int const lim = kring->nkr_num_slots - 1; 812 u_int head = kring->rhead; 813 struct netmap_ring *ring = kring->ring; 814 bus_dmamap_t *map; 815 struct if_rxd_update iru; 816 if_ctx_t ctx = rxq->ifr_ctx; 817 iflib_fl_t fl = &rxq->ifr_fl[0]; 818 uint32_t refill_pidx, nic_i; 819 #if IFLIB_DEBUG_COUNTERS 820 int rf_count = 0; 821 #endif 822 823 if (nm_i == head && __predict_true(!init)) 824 return 0; 825 iru_init(&iru, rxq, 0 /* flid */); 826 map = fl->ifl_sds.ifsd_map; 827 refill_pidx = netmap_idx_k2n(kring, nm_i); 828 /* 829 * IMPORTANT: we must leave one free slot in the ring, 830 * so move head back by one unit 831 */ 832 head = nm_prev(head, lim); 833 nic_i = UINT_MAX; 834 DBG_COUNTER_INC(fl_refills); 835 while (nm_i != head) { 836 #if IFLIB_DEBUG_COUNTERS 837 if (++rf_count == 9) 838 DBG_COUNTER_INC(fl_refills_large); 839 #endif 840 for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { 841 struct netmap_slot *slot = &ring->slot[nm_i]; 842 void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); 843 uint32_t nic_i_dma = refill_pidx; 844 nic_i = netmap_idx_k2n(kring, nm_i); 845 846 MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); 847 848 if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ 849 return netmap_ring_reinit(kring); 850 851 fl->ifl_vm_addrs[tmp_pidx] = addr; 852 if (__predict_false(init)) { 853 netmap_load_map(na, fl->ifl_buf_tag, 854 map[nic_i], addr); 855 } else if (slot->flags & NS_BUF_CHANGED) { 856 /* buffer has changed, reload map */ 857 netmap_reload_map(na, fl->ifl_buf_tag, 858 map[nic_i], addr); 859 } 860 slot->flags &= ~NS_BUF_CHANGED; 861 862 nm_i = nm_next(nm_i, lim); 863 fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); 864 if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) 865 continue; 866 867 iru.iru_pidx = refill_pidx; 868 iru.iru_count = tmp_pidx+1; 869 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 870 refill_pidx = nic_i; 871 for (int n = 0; n < iru.iru_count; n++) { 872 bus_dmamap_sync(fl->ifl_buf_tag, map[nic_i_dma], 873 BUS_DMASYNC_PREREAD); 874 /* XXX - change this to not use the netmap func*/ 875 nic_i_dma = nm_next(nic_i_dma, lim); 876 } 877 } 878 } 879 kring->nr_hwcur = head; 880 881 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 882 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 883 if (__predict_true(nic_i != UINT_MAX)) { 884 ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); 885 DBG_COUNTER_INC(rxd_flush); 886 } 887 return (0); 888 } 889 890 /* 891 * Reconcile kernel and user view of the transmit ring. 892 * 893 * All information is in the kring. 894 * Userspace wants to send packets up to the one before kring->rhead, 895 * kernel knows kring->nr_hwcur is the first unsent packet. 896 * 897 * Here we push packets out (as many as possible), and possibly 898 * reclaim buffers from previously completed transmission. 899 * 900 * The caller (netmap) guarantees that there is only one instance 901 * running at any time. Any interference with other driver 902 * methods should be handled by the individual drivers. 903 */ 904 static int 905 iflib_netmap_txsync(struct netmap_kring *kring, int flags) 906 { 907 struct netmap_adapter *na = kring->na; 908 if_t ifp = na->ifp; 909 struct netmap_ring *ring = kring->ring; 910 u_int nm_i; /* index into the netmap kring */ 911 u_int nic_i; /* index into the NIC ring */ 912 u_int n; 913 u_int const lim = kring->nkr_num_slots - 1; 914 u_int const head = kring->rhead; 915 struct if_pkt_info pi; 916 917 /* 918 * interrupts on every tx packet are expensive so request 919 * them every half ring, or where NS_REPORT is set 920 */ 921 u_int report_frequency = kring->nkr_num_slots >> 1; 922 /* device-specific */ 923 if_ctx_t ctx = ifp->if_softc; 924 iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; 925 926 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 927 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 928 929 /* 930 * First part: process new packets to send. 931 * nm_i is the current index in the netmap kring, 932 * nic_i is the corresponding index in the NIC ring. 933 * 934 * If we have packets to send (nm_i != head) 935 * iterate over the netmap ring, fetch length and update 936 * the corresponding slot in the NIC ring. Some drivers also 937 * need to update the buffer's physical address in the NIC slot 938 * even NS_BUF_CHANGED is not set (PNMB computes the addresses). 939 * 940 * The netmap_reload_map() calls is especially expensive, 941 * even when (as in this case) the tag is 0, so do only 942 * when the buffer has actually changed. 943 * 944 * If possible do not set the report/intr bit on all slots, 945 * but only a few times per ring or when NS_REPORT is set. 946 * 947 * Finally, on 10G and faster drivers, it might be useful 948 * to prefetch the next slot and txr entry. 949 */ 950 951 nm_i = kring->nr_hwcur; 952 if (nm_i != head) { /* we have new packets to send */ 953 pkt_info_zero(&pi); 954 pi.ipi_segs = txq->ift_segs; 955 pi.ipi_qsidx = kring->ring_id; 956 nic_i = netmap_idx_k2n(kring, nm_i); 957 958 __builtin_prefetch(&ring->slot[nm_i]); 959 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); 960 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); 961 962 for (n = 0; nm_i != head; n++) { 963 struct netmap_slot *slot = &ring->slot[nm_i]; 964 u_int len = slot->len; 965 uint64_t paddr; 966 void *addr = PNMB(na, slot, &paddr); 967 int flags = (slot->flags & NS_REPORT || 968 nic_i == 0 || nic_i == report_frequency) ? 969 IPI_TX_INTR : 0; 970 971 /* device-specific */ 972 pi.ipi_len = len; 973 pi.ipi_segs[0].ds_addr = paddr; 974 pi.ipi_segs[0].ds_len = len; 975 pi.ipi_nsegs = 1; 976 pi.ipi_ndescs = 0; 977 pi.ipi_pidx = nic_i; 978 pi.ipi_flags = flags; 979 980 /* Fill the slot in the NIC ring. */ 981 ctx->isc_txd_encap(ctx->ifc_softc, &pi); 982 DBG_COUNTER_INC(tx_encap); 983 984 /* prefetch for next round */ 985 __builtin_prefetch(&ring->slot[nm_i + 1]); 986 __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); 987 __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); 988 989 NM_CHECK_ADDR_LEN(na, addr, len); 990 991 if (slot->flags & NS_BUF_CHANGED) { 992 /* buffer has changed, reload map */ 993 netmap_reload_map(na, txq->ift_buf_tag, 994 txq->ift_sds.ifsd_map[nic_i], addr); 995 } 996 /* make sure changes to the buffer are synced */ 997 bus_dmamap_sync(txq->ift_buf_tag, 998 txq->ift_sds.ifsd_map[nic_i], 999 BUS_DMASYNC_PREWRITE); 1000 1001 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 1002 nm_i = nm_next(nm_i, lim); 1003 nic_i = nm_next(nic_i, lim); 1004 } 1005 kring->nr_hwcur = nm_i; 1006 1007 /* synchronize the NIC ring */ 1008 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1010 1011 /* (re)start the tx unit up to slot nic_i (excluded) */ 1012 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); 1013 } 1014 1015 /* 1016 * Second part: reclaim buffers for completed transmissions. 1017 * 1018 * If there are unclaimed buffers, attempt to reclaim them. 1019 * If none are reclaimed, and TX IRQs are not in use, do an initial 1020 * minimal delay, then trigger the tx handler which will spin in the 1021 * group task queue. 1022 */ 1023 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1024 if (iflib_tx_credits_update(ctx, txq)) { 1025 /* some tx completed, increment avail */ 1026 nic_i = txq->ift_cidx_processed; 1027 kring->nr_hwtail = nm_prev(netmap_idx_n2k(kring, nic_i), lim); 1028 } 1029 } 1030 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) 1031 if (kring->nr_hwtail != nm_prev(kring->nr_hwcur, lim)) { 1032 callout_reset_on(&txq->ift_timer, hz < 2000 ? 1 : hz / 1000, 1033 iflib_timer, txq, txq->ift_timer.c_cpu); 1034 } 1035 return (0); 1036 } 1037 1038 /* 1039 * Reconcile kernel and user view of the receive ring. 1040 * Same as for the txsync, this routine must be efficient. 1041 * The caller guarantees a single invocations, but races against 1042 * the rest of the driver should be handled here. 1043 * 1044 * On call, kring->rhead is the first packet that userspace wants 1045 * to keep, and kring->rcur is the wakeup point. 1046 * The kernel has previously reported packets up to kring->rtail. 1047 * 1048 * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective 1049 * of whether or not we received an interrupt. 1050 */ 1051 static int 1052 iflib_netmap_rxsync(struct netmap_kring *kring, int flags) 1053 { 1054 struct netmap_adapter *na = kring->na; 1055 struct netmap_ring *ring = kring->ring; 1056 if_t ifp = na->ifp; 1057 iflib_fl_t fl; 1058 uint32_t nm_i; /* index into the netmap ring */ 1059 uint32_t nic_i; /* index into the NIC ring */ 1060 u_int i, n; 1061 u_int const lim = kring->nkr_num_slots - 1; 1062 u_int const head = kring->rhead; 1063 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 1064 struct if_rxd_info ri; 1065 1066 if_ctx_t ctx = ifp->if_softc; 1067 iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; 1068 if (head > lim) 1069 return netmap_ring_reinit(kring); 1070 1071 /* 1072 * XXX netmap_fl_refill() only ever (re)fills free list 0 so far. 1073 */ 1074 1075 for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { 1076 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 1077 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1078 } 1079 1080 /* 1081 * First part: import newly received packets. 1082 * 1083 * nm_i is the index of the next free slot in the netmap ring, 1084 * nic_i is the index of the next received packet in the NIC ring, 1085 * and they may differ in case if_init() has been called while 1086 * in netmap mode. For the receive ring we have 1087 * 1088 * nic_i = rxr->next_check; 1089 * nm_i = kring->nr_hwtail (previous) 1090 * and 1091 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1092 * 1093 * rxr->next_check is set to 0 on a ring reinit 1094 */ 1095 if (netmap_no_pendintr || force_update) { 1096 int crclen = iflib_crcstrip ? 0 : 4; 1097 int error, avail; 1098 1099 for (i = 0; i < rxq->ifr_nfl; i++) { 1100 fl = &rxq->ifr_fl[i]; 1101 nic_i = fl->ifl_cidx; 1102 nm_i = netmap_idx_n2k(kring, nic_i); 1103 avail = ctx->isc_rxd_available(ctx->ifc_softc, 1104 rxq->ifr_id, nic_i, USHRT_MAX); 1105 for (n = 0; avail > 0; n++, avail--) { 1106 rxd_info_zero(&ri); 1107 ri.iri_frags = rxq->ifr_frags; 1108 ri.iri_qsidx = kring->ring_id; 1109 ri.iri_ifp = ctx->ifc_ifp; 1110 ri.iri_cidx = nic_i; 1111 1112 error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 1113 ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; 1114 ring->slot[nm_i].flags = 0; 1115 bus_dmamap_sync(fl->ifl_buf_tag, 1116 fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); 1117 nm_i = nm_next(nm_i, lim); 1118 nic_i = nm_next(nic_i, lim); 1119 } 1120 if (n) { /* update the state variables */ 1121 if (netmap_no_pendintr && !force_update) { 1122 /* diagnostics */ 1123 iflib_rx_miss ++; 1124 iflib_rx_miss_bufs += n; 1125 } 1126 fl->ifl_cidx = nic_i; 1127 kring->nr_hwtail = nm_i; 1128 } 1129 kring->nr_kflags &= ~NKR_PENDINTR; 1130 } 1131 } 1132 /* 1133 * Second part: skip past packets that userspace has released. 1134 * (kring->nr_hwcur to head excluded), 1135 * and make the buffers available for reception. 1136 * As usual nm_i is the index in the netmap ring, 1137 * nic_i is the index in the NIC ring, and 1138 * nm_i == (nic_i + kring->nkr_hwofs) % ring_size 1139 */ 1140 /* XXX not sure how this will work with multiple free lists */ 1141 nm_i = kring->nr_hwcur; 1142 1143 return (netmap_fl_refill(rxq, kring, nm_i, false)); 1144 } 1145 1146 static void 1147 iflib_netmap_intr(struct netmap_adapter *na, int onoff) 1148 { 1149 if_ctx_t ctx = na->ifp->if_softc; 1150 1151 CTX_LOCK(ctx); 1152 if (onoff) { 1153 IFDI_INTR_ENABLE(ctx); 1154 } else { 1155 IFDI_INTR_DISABLE(ctx); 1156 } 1157 CTX_UNLOCK(ctx); 1158 } 1159 1160 1161 static int 1162 iflib_netmap_attach(if_ctx_t ctx) 1163 { 1164 struct netmap_adapter na; 1165 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1166 1167 bzero(&na, sizeof(na)); 1168 1169 na.ifp = ctx->ifc_ifp; 1170 na.na_flags = NAF_BDG_MAYSLEEP; 1171 MPASS(ctx->ifc_softc_ctx.isc_ntxqsets); 1172 MPASS(ctx->ifc_softc_ctx.isc_nrxqsets); 1173 1174 na.num_tx_desc = scctx->isc_ntxd[0]; 1175 na.num_rx_desc = scctx->isc_nrxd[0]; 1176 na.nm_txsync = iflib_netmap_txsync; 1177 na.nm_rxsync = iflib_netmap_rxsync; 1178 na.nm_register = iflib_netmap_register; 1179 na.nm_intr = iflib_netmap_intr; 1180 na.num_tx_rings = ctx->ifc_softc_ctx.isc_ntxqsets; 1181 na.num_rx_rings = ctx->ifc_softc_ctx.isc_nrxqsets; 1182 return (netmap_attach(&na)); 1183 } 1184 1185 static void 1186 iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) 1187 { 1188 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1189 struct netmap_slot *slot; 1190 1191 slot = netmap_reset(na, NR_TX, txq->ift_id, 0); 1192 if (slot == NULL) 1193 return; 1194 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { 1195 1196 /* 1197 * In netmap mode, set the map for the packet buffer. 1198 * NOTE: Some drivers (not this one) also need to set 1199 * the physical buffer address in the NIC ring. 1200 * netmap_idx_n2k() maps a nic index, i, into the corresponding 1201 * netmap slot index, si 1202 */ 1203 int si = netmap_idx_n2k(na->tx_rings[txq->ift_id], i); 1204 netmap_load_map(na, txq->ift_buf_tag, txq->ift_sds.ifsd_map[i], 1205 NMB(na, slot + si)); 1206 } 1207 } 1208 1209 static void 1210 iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) 1211 { 1212 struct netmap_adapter *na = NA(ctx->ifc_ifp); 1213 struct netmap_kring *kring = na->rx_rings[rxq->ifr_id]; 1214 struct netmap_slot *slot; 1215 uint32_t nm_i; 1216 1217 slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); 1218 if (slot == NULL) 1219 return; 1220 nm_i = netmap_idx_n2k(kring, 0); 1221 netmap_fl_refill(rxq, kring, nm_i, true); 1222 } 1223 1224 static void 1225 iflib_netmap_timer_adjust(if_ctx_t ctx, iflib_txq_t txq, uint32_t *reset_on) 1226 { 1227 struct netmap_kring *kring; 1228 uint16_t txqid; 1229 1230 txqid = txq->ift_id; 1231 kring = NA(ctx->ifc_ifp)->tx_rings[txqid]; 1232 1233 if (kring->nr_hwcur != nm_next(kring->nr_hwtail, kring->nkr_num_slots - 1)) { 1234 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1235 BUS_DMASYNC_POSTREAD); 1236 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) 1237 netmap_tx_irq(ctx->ifc_ifp, txqid); 1238 if (!(ctx->ifc_flags & IFC_NETMAP_TX_IRQ)) { 1239 if (hz < 2000) 1240 *reset_on = 1; 1241 else 1242 *reset_on = hz / 1000; 1243 } 1244 } 1245 } 1246 1247 #define iflib_netmap_detach(ifp) netmap_detach(ifp) 1248 1249 #else 1250 #define iflib_netmap_txq_init(ctx, txq) 1251 #define iflib_netmap_rxq_init(ctx, rxq) 1252 #define iflib_netmap_detach(ifp) 1253 1254 #define iflib_netmap_attach(ctx) (0) 1255 #define netmap_rx_irq(ifp, qid, budget) (0) 1256 #define netmap_tx_irq(ifp, qid) do {} while (0) 1257 #define iflib_netmap_timer_adjust(ctx, txq, reset_on) 1258 #endif 1259 1260 #if defined(__i386__) || defined(__amd64__) 1261 static __inline void 1262 prefetch(void *x) 1263 { 1264 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1265 } 1266 static __inline void 1267 prefetch2cachelines(void *x) 1268 { 1269 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 1270 #if (CACHE_LINE_SIZE < 128) 1271 __asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); 1272 #endif 1273 } 1274 #else 1275 #define prefetch(x) 1276 #define prefetch2cachelines(x) 1277 #endif 1278 1279 static void 1280 iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) 1281 { 1282 iflib_fl_t fl; 1283 1284 fl = &rxq->ifr_fl[flid]; 1285 iru->iru_paddrs = fl->ifl_bus_addrs; 1286 iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; 1287 iru->iru_idxs = fl->ifl_rxd_idxs; 1288 iru->iru_qsidx = rxq->ifr_id; 1289 iru->iru_buf_size = fl->ifl_buf_size; 1290 iru->iru_flidx = fl->ifl_id; 1291 } 1292 1293 static void 1294 _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 1295 { 1296 if (err) 1297 return; 1298 *(bus_addr_t *) arg = segs[0].ds_addr; 1299 } 1300 1301 int 1302 iflib_dma_alloc_align(if_ctx_t ctx, int size, int align, iflib_dma_info_t dma, int mapflags) 1303 { 1304 int err; 1305 device_t dev = ctx->ifc_dev; 1306 1307 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1308 align, 0, /* alignment, bounds */ 1309 BUS_SPACE_MAXADDR, /* lowaddr */ 1310 BUS_SPACE_MAXADDR, /* highaddr */ 1311 NULL, NULL, /* filter, filterarg */ 1312 size, /* maxsize */ 1313 1, /* nsegments */ 1314 size, /* maxsegsize */ 1315 BUS_DMA_ALLOCNOW, /* flags */ 1316 NULL, /* lockfunc */ 1317 NULL, /* lockarg */ 1318 &dma->idi_tag); 1319 if (err) { 1320 device_printf(dev, 1321 "%s: bus_dma_tag_create failed: %d\n", 1322 __func__, err); 1323 goto fail_0; 1324 } 1325 1326 err = bus_dmamem_alloc(dma->idi_tag, (void**) &dma->idi_vaddr, 1327 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &dma->idi_map); 1328 if (err) { 1329 device_printf(dev, 1330 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 1331 __func__, (uintmax_t)size, err); 1332 goto fail_1; 1333 } 1334 1335 dma->idi_paddr = IF_BAD_DMA; 1336 err = bus_dmamap_load(dma->idi_tag, dma->idi_map, dma->idi_vaddr, 1337 size, _iflib_dmamap_cb, &dma->idi_paddr, mapflags | BUS_DMA_NOWAIT); 1338 if (err || dma->idi_paddr == IF_BAD_DMA) { 1339 device_printf(dev, 1340 "%s: bus_dmamap_load failed: %d\n", 1341 __func__, err); 1342 goto fail_2; 1343 } 1344 1345 dma->idi_size = size; 1346 return (0); 1347 1348 fail_2: 1349 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1350 fail_1: 1351 bus_dma_tag_destroy(dma->idi_tag); 1352 fail_0: 1353 dma->idi_tag = NULL; 1354 1355 return (err); 1356 } 1357 1358 int 1359 iflib_dma_alloc(if_ctx_t ctx, int size, iflib_dma_info_t dma, int mapflags) 1360 { 1361 if_shared_ctx_t sctx = ctx->ifc_sctx; 1362 1363 KASSERT(sctx->isc_q_align != 0, ("alignment value not initialized")); 1364 1365 return (iflib_dma_alloc_align(ctx, size, sctx->isc_q_align, dma, mapflags)); 1366 } 1367 1368 int 1369 iflib_dma_alloc_multi(if_ctx_t ctx, int *sizes, iflib_dma_info_t *dmalist, int mapflags, int count) 1370 { 1371 int i, err; 1372 iflib_dma_info_t *dmaiter; 1373 1374 dmaiter = dmalist; 1375 for (i = 0; i < count; i++, dmaiter++) { 1376 if ((err = iflib_dma_alloc(ctx, sizes[i], *dmaiter, mapflags)) != 0) 1377 break; 1378 } 1379 if (err) 1380 iflib_dma_free_multi(dmalist, i); 1381 return (err); 1382 } 1383 1384 void 1385 iflib_dma_free(iflib_dma_info_t dma) 1386 { 1387 if (dma->idi_tag == NULL) 1388 return; 1389 if (dma->idi_paddr != IF_BAD_DMA) { 1390 bus_dmamap_sync(dma->idi_tag, dma->idi_map, 1391 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1392 bus_dmamap_unload(dma->idi_tag, dma->idi_map); 1393 dma->idi_paddr = IF_BAD_DMA; 1394 } 1395 if (dma->idi_vaddr != NULL) { 1396 bus_dmamem_free(dma->idi_tag, dma->idi_vaddr, dma->idi_map); 1397 dma->idi_vaddr = NULL; 1398 } 1399 bus_dma_tag_destroy(dma->idi_tag); 1400 dma->idi_tag = NULL; 1401 } 1402 1403 void 1404 iflib_dma_free_multi(iflib_dma_info_t *dmalist, int count) 1405 { 1406 int i; 1407 iflib_dma_info_t *dmaiter = dmalist; 1408 1409 for (i = 0; i < count; i++, dmaiter++) 1410 iflib_dma_free(*dmaiter); 1411 } 1412 1413 static int 1414 iflib_fast_intr(void *arg) 1415 { 1416 iflib_filter_info_t info = arg; 1417 struct grouptask *gtask = info->ifi_task; 1418 int result; 1419 1420 DBG_COUNTER_INC(fast_intrs); 1421 if (info->ifi_filter != NULL) { 1422 result = info->ifi_filter(info->ifi_filter_arg); 1423 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1424 return (result); 1425 } 1426 1427 GROUPTASK_ENQUEUE(gtask); 1428 return (FILTER_HANDLED); 1429 } 1430 1431 static int 1432 iflib_fast_intr_rxtx(void *arg) 1433 { 1434 iflib_filter_info_t info = arg; 1435 struct grouptask *gtask = info->ifi_task; 1436 if_ctx_t ctx; 1437 iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; 1438 iflib_txq_t txq; 1439 void *sc; 1440 int i, cidx, result; 1441 qidx_t txqid; 1442 bool intr_enable, intr_legacy; 1443 1444 DBG_COUNTER_INC(fast_intrs); 1445 if (info->ifi_filter != NULL) { 1446 result = info->ifi_filter(info->ifi_filter_arg); 1447 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1448 return (result); 1449 } 1450 1451 ctx = rxq->ifr_ctx; 1452 sc = ctx->ifc_softc; 1453 intr_enable = false; 1454 intr_legacy = !!(ctx->ifc_flags & IFC_LEGACY); 1455 MPASS(rxq->ifr_ntxqirq); 1456 for (i = 0; i < rxq->ifr_ntxqirq; i++) { 1457 txqid = rxq->ifr_txqid[i]; 1458 txq = &ctx->ifc_txqs[txqid]; 1459 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 1460 BUS_DMASYNC_POSTREAD); 1461 if (!ctx->isc_txd_credits_update(sc, txqid, false)) { 1462 if (intr_legacy) 1463 intr_enable = true; 1464 else 1465 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); 1466 continue; 1467 } 1468 GROUPTASK_ENQUEUE(&txq->ift_task); 1469 } 1470 if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) 1471 cidx = rxq->ifr_cq_cidx; 1472 else 1473 cidx = rxq->ifr_fl[0].ifl_cidx; 1474 if (iflib_rxd_avail(ctx, rxq, cidx, 1)) 1475 GROUPTASK_ENQUEUE(gtask); 1476 else { 1477 if (intr_legacy) 1478 intr_enable = true; 1479 else 1480 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 1481 DBG_COUNTER_INC(rx_intr_enables); 1482 } 1483 if (intr_enable) 1484 IFDI_INTR_ENABLE(ctx); 1485 return (FILTER_HANDLED); 1486 } 1487 1488 1489 static int 1490 iflib_fast_intr_ctx(void *arg) 1491 { 1492 iflib_filter_info_t info = arg; 1493 struct grouptask *gtask = info->ifi_task; 1494 int result; 1495 1496 DBG_COUNTER_INC(fast_intrs); 1497 if (info->ifi_filter != NULL) { 1498 result = info->ifi_filter(info->ifi_filter_arg); 1499 if ((result & FILTER_SCHEDULE_THREAD) == 0) 1500 return (result); 1501 } 1502 1503 GROUPTASK_ENQUEUE(gtask); 1504 return (FILTER_HANDLED); 1505 } 1506 1507 static int 1508 _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 1509 driver_filter_t filter, driver_intr_t handler, void *arg, 1510 const char *name) 1511 { 1512 struct resource *res; 1513 void *tag = NULL; 1514 device_t dev = ctx->ifc_dev; 1515 int flags, i, rc; 1516 1517 flags = RF_ACTIVE; 1518 if (ctx->ifc_flags & IFC_LEGACY) 1519 flags |= RF_SHAREABLE; 1520 MPASS(rid < 512); 1521 i = rid; 1522 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, flags); 1523 if (res == NULL) { 1524 device_printf(dev, 1525 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 1526 return (ENOMEM); 1527 } 1528 irq->ii_res = res; 1529 KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); 1530 rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, 1531 filter, handler, arg, &tag); 1532 if (rc != 0) { 1533 device_printf(dev, 1534 "failed to setup interrupt for rid %d, name %s: %d\n", 1535 rid, name ? name : "unknown", rc); 1536 return (rc); 1537 } else if (name) 1538 bus_describe_intr(dev, res, tag, "%s", name); 1539 1540 irq->ii_tag = tag; 1541 return (0); 1542 } 1543 1544 /********************************************************************* 1545 * 1546 * Allocate DMA resources for TX buffers as well as memory for the TX 1547 * mbuf map. TX DMA maps (non-TSO/TSO) and TX mbuf map are kept in a 1548 * iflib_sw_tx_desc_array structure, storing all the information that 1549 * is needed to transmit a packet on the wire. This is called only 1550 * once at attach, setup is done every reset. 1551 * 1552 **********************************************************************/ 1553 static int 1554 iflib_txsd_alloc(iflib_txq_t txq) 1555 { 1556 if_ctx_t ctx = txq->ift_ctx; 1557 if_shared_ctx_t sctx = ctx->ifc_sctx; 1558 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1559 device_t dev = ctx->ifc_dev; 1560 bus_size_t tsomaxsize; 1561 int err, nsegments, ntsosegments; 1562 bool tso; 1563 1564 nsegments = scctx->isc_tx_nsegments; 1565 ntsosegments = scctx->isc_tx_tso_segments_max; 1566 tsomaxsize = scctx->isc_tx_tso_size_max; 1567 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_VLAN_MTU) 1568 tsomaxsize += sizeof(struct ether_vlan_header); 1569 MPASS(scctx->isc_ntxd[0] > 0); 1570 MPASS(scctx->isc_ntxd[txq->ift_br_offset] > 0); 1571 MPASS(nsegments > 0); 1572 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) { 1573 MPASS(ntsosegments > 0); 1574 MPASS(sctx->isc_tso_maxsize >= tsomaxsize); 1575 } 1576 1577 /* 1578 * Set up DMA tags for TX buffers. 1579 */ 1580 if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), 1581 1, 0, /* alignment, bounds */ 1582 BUS_SPACE_MAXADDR, /* lowaddr */ 1583 BUS_SPACE_MAXADDR, /* highaddr */ 1584 NULL, NULL, /* filter, filterarg */ 1585 sctx->isc_tx_maxsize, /* maxsize */ 1586 nsegments, /* nsegments */ 1587 sctx->isc_tx_maxsegsize, /* maxsegsize */ 1588 0, /* flags */ 1589 NULL, /* lockfunc */ 1590 NULL, /* lockfuncarg */ 1591 &txq->ift_buf_tag))) { 1592 device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); 1593 device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", 1594 (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); 1595 goto fail; 1596 } 1597 tso = (if_getcapabilities(ctx->ifc_ifp) & IFCAP_TSO) != 0; 1598 if (tso && (err = bus_dma_tag_create(bus_get_dma_tag(dev), 1599 1, 0, /* alignment, bounds */ 1600 BUS_SPACE_MAXADDR, /* lowaddr */ 1601 BUS_SPACE_MAXADDR, /* highaddr */ 1602 NULL, NULL, /* filter, filterarg */ 1603 tsomaxsize, /* maxsize */ 1604 ntsosegments, /* nsegments */ 1605 sctx->isc_tso_maxsegsize,/* maxsegsize */ 1606 0, /* flags */ 1607 NULL, /* lockfunc */ 1608 NULL, /* lockfuncarg */ 1609 &txq->ift_tso_buf_tag))) { 1610 device_printf(dev, "Unable to allocate TSO TX DMA tag: %d\n", 1611 err); 1612 goto fail; 1613 } 1614 1615 /* Allocate memory for the TX mbuf map. */ 1616 if (!(txq->ift_sds.ifsd_m = 1617 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1618 scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1619 device_printf(dev, "Unable to allocate TX mbuf map memory\n"); 1620 err = ENOMEM; 1621 goto fail; 1622 } 1623 1624 /* 1625 * Create the DMA maps for TX buffers. 1626 */ 1627 if ((txq->ift_sds.ifsd_map = (bus_dmamap_t *)malloc( 1628 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1629 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1630 device_printf(dev, 1631 "Unable to allocate TX buffer DMA map memory\n"); 1632 err = ENOMEM; 1633 goto fail; 1634 } 1635 if (tso && (txq->ift_sds.ifsd_tso_map = (bus_dmamap_t *)malloc( 1636 sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], 1637 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 1638 device_printf(dev, 1639 "Unable to allocate TSO TX buffer map memory\n"); 1640 err = ENOMEM; 1641 goto fail; 1642 } 1643 for (int i = 0; i < scctx->isc_ntxd[txq->ift_br_offset]; i++) { 1644 err = bus_dmamap_create(txq->ift_buf_tag, 0, 1645 &txq->ift_sds.ifsd_map[i]); 1646 if (err != 0) { 1647 device_printf(dev, "Unable to create TX DMA map\n"); 1648 goto fail; 1649 } 1650 if (!tso) 1651 continue; 1652 err = bus_dmamap_create(txq->ift_tso_buf_tag, 0, 1653 &txq->ift_sds.ifsd_tso_map[i]); 1654 if (err != 0) { 1655 device_printf(dev, "Unable to create TSO TX DMA map\n"); 1656 goto fail; 1657 } 1658 } 1659 return (0); 1660 fail: 1661 /* We free all, it handles case where we are in the middle */ 1662 iflib_tx_structures_free(ctx); 1663 return (err); 1664 } 1665 1666 static void 1667 iflib_txsd_destroy(if_ctx_t ctx, iflib_txq_t txq, int i) 1668 { 1669 bus_dmamap_t map; 1670 1671 if (txq->ift_sds.ifsd_map != NULL) { 1672 map = txq->ift_sds.ifsd_map[i]; 1673 bus_dmamap_sync(txq->ift_buf_tag, map, BUS_DMASYNC_POSTWRITE); 1674 bus_dmamap_unload(txq->ift_buf_tag, map); 1675 bus_dmamap_destroy(txq->ift_buf_tag, map); 1676 txq->ift_sds.ifsd_map[i] = NULL; 1677 } 1678 1679 if (txq->ift_sds.ifsd_tso_map != NULL) { 1680 map = txq->ift_sds.ifsd_tso_map[i]; 1681 bus_dmamap_sync(txq->ift_tso_buf_tag, map, 1682 BUS_DMASYNC_POSTWRITE); 1683 bus_dmamap_unload(txq->ift_tso_buf_tag, map); 1684 bus_dmamap_destroy(txq->ift_tso_buf_tag, map); 1685 txq->ift_sds.ifsd_tso_map[i] = NULL; 1686 } 1687 } 1688 1689 static void 1690 iflib_txq_destroy(iflib_txq_t txq) 1691 { 1692 if_ctx_t ctx = txq->ift_ctx; 1693 1694 for (int i = 0; i < txq->ift_size; i++) 1695 iflib_txsd_destroy(ctx, txq, i); 1696 1697 if (txq->ift_br != NULL) { 1698 ifmp_ring_free(txq->ift_br); 1699 txq->ift_br = NULL; 1700 } 1701 1702 mtx_destroy(&txq->ift_mtx); 1703 1704 if (txq->ift_sds.ifsd_map != NULL) { 1705 free(txq->ift_sds.ifsd_map, M_IFLIB); 1706 txq->ift_sds.ifsd_map = NULL; 1707 } 1708 if (txq->ift_sds.ifsd_tso_map != NULL) { 1709 free(txq->ift_sds.ifsd_tso_map, M_IFLIB); 1710 txq->ift_sds.ifsd_tso_map = NULL; 1711 } 1712 if (txq->ift_sds.ifsd_m != NULL) { 1713 free(txq->ift_sds.ifsd_m, M_IFLIB); 1714 txq->ift_sds.ifsd_m = NULL; 1715 } 1716 if (txq->ift_buf_tag != NULL) { 1717 bus_dma_tag_destroy(txq->ift_buf_tag); 1718 txq->ift_buf_tag = NULL; 1719 } 1720 if (txq->ift_tso_buf_tag != NULL) { 1721 bus_dma_tag_destroy(txq->ift_tso_buf_tag); 1722 txq->ift_tso_buf_tag = NULL; 1723 } 1724 if (txq->ift_ifdi != NULL) { 1725 free(txq->ift_ifdi, M_IFLIB); 1726 } 1727 } 1728 1729 static void 1730 iflib_txsd_free(if_ctx_t ctx, iflib_txq_t txq, int i) 1731 { 1732 struct mbuf **mp; 1733 1734 mp = &txq->ift_sds.ifsd_m[i]; 1735 if (*mp == NULL) 1736 return; 1737 1738 if (txq->ift_sds.ifsd_map != NULL) { 1739 bus_dmamap_sync(txq->ift_buf_tag, 1740 txq->ift_sds.ifsd_map[i], BUS_DMASYNC_POSTWRITE); 1741 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[i]); 1742 } 1743 if (txq->ift_sds.ifsd_tso_map != NULL) { 1744 bus_dmamap_sync(txq->ift_tso_buf_tag, 1745 txq->ift_sds.ifsd_tso_map[i], BUS_DMASYNC_POSTWRITE); 1746 bus_dmamap_unload(txq->ift_tso_buf_tag, 1747 txq->ift_sds.ifsd_tso_map[i]); 1748 } 1749 m_free(*mp); 1750 DBG_COUNTER_INC(tx_frees); 1751 *mp = NULL; 1752 } 1753 1754 static int 1755 iflib_txq_setup(iflib_txq_t txq) 1756 { 1757 if_ctx_t ctx = txq->ift_ctx; 1758 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1759 if_shared_ctx_t sctx = ctx->ifc_sctx; 1760 iflib_dma_info_t di; 1761 int i; 1762 1763 /* Set number of descriptors available */ 1764 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 1765 /* XXX make configurable */ 1766 txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; 1767 1768 /* Reset indices */ 1769 txq->ift_cidx_processed = 0; 1770 txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; 1771 txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; 1772 1773 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1774 bzero((void *)di->idi_vaddr, di->idi_size); 1775 1776 IFDI_TXQ_SETUP(ctx, txq->ift_id); 1777 for (i = 0, di = txq->ift_ifdi; i < sctx->isc_ntxqs; i++, di++) 1778 bus_dmamap_sync(di->idi_tag, di->idi_map, 1779 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1780 return (0); 1781 } 1782 1783 /********************************************************************* 1784 * 1785 * Allocate DMA resources for RX buffers as well as memory for the RX 1786 * mbuf map, direct RX cluster pointer map and RX cluster bus address 1787 * map. RX DMA map, RX mbuf map, direct RX cluster pointer map and 1788 * RX cluster map are kept in a iflib_sw_rx_desc_array structure. 1789 * Since we use use one entry in iflib_sw_rx_desc_array per received 1790 * packet, the maximum number of entries we'll need is equal to the 1791 * number of hardware receive descriptors that we've allocated. 1792 * 1793 **********************************************************************/ 1794 static int 1795 iflib_rxsd_alloc(iflib_rxq_t rxq) 1796 { 1797 if_ctx_t ctx = rxq->ifr_ctx; 1798 if_shared_ctx_t sctx = ctx->ifc_sctx; 1799 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 1800 device_t dev = ctx->ifc_dev; 1801 iflib_fl_t fl; 1802 int err; 1803 1804 MPASS(scctx->isc_nrxd[0] > 0); 1805 MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); 1806 1807 fl = rxq->ifr_fl; 1808 for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { 1809 fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ 1810 /* Set up DMA tag for RX buffers. */ 1811 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 1812 1, 0, /* alignment, bounds */ 1813 BUS_SPACE_MAXADDR, /* lowaddr */ 1814 BUS_SPACE_MAXADDR, /* highaddr */ 1815 NULL, NULL, /* filter, filterarg */ 1816 sctx->isc_rx_maxsize, /* maxsize */ 1817 sctx->isc_rx_nsegments, /* nsegments */ 1818 sctx->isc_rx_maxsegsize, /* maxsegsize */ 1819 0, /* flags */ 1820 NULL, /* lockfunc */ 1821 NULL, /* lockarg */ 1822 &fl->ifl_buf_tag); 1823 if (err) { 1824 device_printf(dev, 1825 "Unable to allocate RX DMA tag: %d\n", err); 1826 goto fail; 1827 } 1828 1829 /* Allocate memory for the RX mbuf map. */ 1830 if (!(fl->ifl_sds.ifsd_m = 1831 (struct mbuf **) malloc(sizeof(struct mbuf *) * 1832 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1833 device_printf(dev, 1834 "Unable to allocate RX mbuf map memory\n"); 1835 err = ENOMEM; 1836 goto fail; 1837 } 1838 1839 /* Allocate memory for the direct RX cluster pointer map. */ 1840 if (!(fl->ifl_sds.ifsd_cl = 1841 (caddr_t *) malloc(sizeof(caddr_t) * 1842 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1843 device_printf(dev, 1844 "Unable to allocate RX cluster map memory\n"); 1845 err = ENOMEM; 1846 goto fail; 1847 } 1848 1849 /* Allocate memory for the RX cluster bus address map. */ 1850 if (!(fl->ifl_sds.ifsd_ba = 1851 (bus_addr_t *) malloc(sizeof(bus_addr_t) * 1852 scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1853 device_printf(dev, 1854 "Unable to allocate RX bus address map memory\n"); 1855 err = ENOMEM; 1856 goto fail; 1857 } 1858 1859 /* 1860 * Create the DMA maps for RX buffers. 1861 */ 1862 if (!(fl->ifl_sds.ifsd_map = 1863 (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { 1864 device_printf(dev, 1865 "Unable to allocate RX buffer DMA map memory\n"); 1866 err = ENOMEM; 1867 goto fail; 1868 } 1869 for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { 1870 err = bus_dmamap_create(fl->ifl_buf_tag, 0, 1871 &fl->ifl_sds.ifsd_map[i]); 1872 if (err != 0) { 1873 device_printf(dev, "Unable to create RX buffer DMA map\n"); 1874 goto fail; 1875 } 1876 } 1877 } 1878 return (0); 1879 1880 fail: 1881 iflib_rx_structures_free(ctx); 1882 return (err); 1883 } 1884 1885 1886 /* 1887 * Internal service routines 1888 */ 1889 1890 struct rxq_refill_cb_arg { 1891 int error; 1892 bus_dma_segment_t seg; 1893 int nseg; 1894 }; 1895 1896 static void 1897 _rxq_refill_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1898 { 1899 struct rxq_refill_cb_arg *cb_arg = arg; 1900 1901 cb_arg->error = error; 1902 cb_arg->seg = segs[0]; 1903 cb_arg->nseg = nseg; 1904 } 1905 1906 /** 1907 * _iflib_fl_refill - refill an rxq free-buffer list 1908 * @ctx: the iflib context 1909 * @fl: the free list to refill 1910 * @count: the number of new buffers to allocate 1911 * 1912 * (Re)populate an rxq free-buffer list with up to @count new packet buffers. 1913 * The caller must assure that @count does not exceed the queue's capacity. 1914 */ 1915 static uint8_t 1916 _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) 1917 { 1918 struct if_rxd_update iru; 1919 struct rxq_refill_cb_arg cb_arg; 1920 struct mbuf *m; 1921 caddr_t cl, *sd_cl; 1922 struct mbuf **sd_m; 1923 bus_dmamap_t *sd_map; 1924 bus_addr_t bus_addr, *sd_ba; 1925 int err, frag_idx, i, idx, n, pidx; 1926 qidx_t credits; 1927 1928 sd_m = fl->ifl_sds.ifsd_m; 1929 sd_map = fl->ifl_sds.ifsd_map; 1930 sd_cl = fl->ifl_sds.ifsd_cl; 1931 sd_ba = fl->ifl_sds.ifsd_ba; 1932 pidx = fl->ifl_pidx; 1933 idx = pidx; 1934 frag_idx = fl->ifl_fragidx; 1935 credits = fl->ifl_credits; 1936 1937 i = 0; 1938 n = count; 1939 MPASS(n > 0); 1940 MPASS(credits + n <= fl->ifl_size); 1941 1942 if (pidx < fl->ifl_cidx) 1943 MPASS(pidx + n <= fl->ifl_cidx); 1944 if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) 1945 MPASS(fl->ifl_gen == 0); 1946 if (pidx > fl->ifl_cidx) 1947 MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); 1948 1949 DBG_COUNTER_INC(fl_refills); 1950 if (n > 8) 1951 DBG_COUNTER_INC(fl_refills_large); 1952 iru_init(&iru, fl->ifl_rxq, fl->ifl_id); 1953 while (n--) { 1954 /* 1955 * We allocate an uninitialized mbuf + cluster, mbuf is 1956 * initialized after rx. 1957 * 1958 * If the cluster is still set then we know a minimum sized packet was received 1959 */ 1960 bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, 1961 &frag_idx); 1962 if (frag_idx < 0) 1963 bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); 1964 MPASS(frag_idx >= 0); 1965 if ((cl = sd_cl[frag_idx]) == NULL) { 1966 if ((cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) 1967 break; 1968 1969 cb_arg.error = 0; 1970 MPASS(sd_map != NULL); 1971 err = bus_dmamap_load(fl->ifl_buf_tag, sd_map[frag_idx], 1972 cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 1973 BUS_DMA_NOWAIT); 1974 if (err != 0 || cb_arg.error) { 1975 /* 1976 * !zone_pack ? 1977 */ 1978 if (fl->ifl_zone == zone_pack) 1979 uma_zfree(fl->ifl_zone, cl); 1980 break; 1981 } 1982 1983 sd_ba[frag_idx] = bus_addr = cb_arg.seg.ds_addr; 1984 sd_cl[frag_idx] = cl; 1985 #if MEMORY_LOGGING 1986 fl->ifl_cl_enqueued++; 1987 #endif 1988 } else { 1989 bus_addr = sd_ba[frag_idx]; 1990 } 1991 bus_dmamap_sync(fl->ifl_buf_tag, sd_map[frag_idx], 1992 BUS_DMASYNC_PREREAD); 1993 1994 if (sd_m[frag_idx] == NULL) { 1995 if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { 1996 break; 1997 } 1998 sd_m[frag_idx] = m; 1999 } 2000 bit_set(fl->ifl_rx_bitmap, frag_idx); 2001 #if MEMORY_LOGGING 2002 fl->ifl_m_enqueued++; 2003 #endif 2004 2005 DBG_COUNTER_INC(rx_allocs); 2006 fl->ifl_rxd_idxs[i] = frag_idx; 2007 fl->ifl_bus_addrs[i] = bus_addr; 2008 fl->ifl_vm_addrs[i] = cl; 2009 credits++; 2010 i++; 2011 MPASS(credits <= fl->ifl_size); 2012 if (++idx == fl->ifl_size) { 2013 fl->ifl_gen = 1; 2014 idx = 0; 2015 } 2016 if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { 2017 iru.iru_pidx = pidx; 2018 iru.iru_count = i; 2019 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2020 i = 0; 2021 pidx = idx; 2022 fl->ifl_pidx = idx; 2023 fl->ifl_credits = credits; 2024 } 2025 } 2026 2027 if (i) { 2028 iru.iru_pidx = pidx; 2029 iru.iru_count = i; 2030 ctx->isc_rxd_refill(ctx->ifc_softc, &iru); 2031 fl->ifl_pidx = idx; 2032 fl->ifl_credits = credits; 2033 } 2034 DBG_COUNTER_INC(rxd_flush); 2035 if (fl->ifl_pidx == 0) 2036 pidx = fl->ifl_size - 1; 2037 else 2038 pidx = fl->ifl_pidx - 1; 2039 2040 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2042 ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); 2043 fl->ifl_fragidx = frag_idx + 1; 2044 if (fl->ifl_fragidx == fl->ifl_size) 2045 fl->ifl_fragidx = 0; 2046 2047 return (n == -1 ? 0 : IFLIB_RXEOF_EMPTY); 2048 } 2049 2050 static __inline uint8_t 2051 __iflib_fl_refill_all(if_ctx_t ctx, iflib_fl_t fl) 2052 { 2053 /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ 2054 int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; 2055 #ifdef INVARIANTS 2056 int32_t delta = fl->ifl_size - get_inuse(fl->ifl_size, fl->ifl_cidx, fl->ifl_pidx, fl->ifl_gen) - 1; 2057 #endif 2058 2059 MPASS(fl->ifl_credits <= fl->ifl_size); 2060 MPASS(reclaimable == delta); 2061 2062 if (reclaimable > 0) 2063 return (_iflib_fl_refill(ctx, fl, reclaimable)); 2064 return (0); 2065 } 2066 2067 uint8_t 2068 iflib_in_detach(if_ctx_t ctx) 2069 { 2070 bool in_detach; 2071 2072 STATE_LOCK(ctx); 2073 in_detach = !!(ctx->ifc_flags & IFC_IN_DETACH); 2074 STATE_UNLOCK(ctx); 2075 return (in_detach); 2076 } 2077 2078 static void 2079 iflib_fl_bufs_free(iflib_fl_t fl) 2080 { 2081 iflib_dma_info_t idi = fl->ifl_ifdi; 2082 bus_dmamap_t sd_map; 2083 uint32_t i; 2084 2085 for (i = 0; i < fl->ifl_size; i++) { 2086 struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; 2087 caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; 2088 2089 if (*sd_cl != NULL) { 2090 sd_map = fl->ifl_sds.ifsd_map[i]; 2091 bus_dmamap_sync(fl->ifl_buf_tag, sd_map, 2092 BUS_DMASYNC_POSTREAD); 2093 bus_dmamap_unload(fl->ifl_buf_tag, sd_map); 2094 if (*sd_cl != NULL) 2095 uma_zfree(fl->ifl_zone, *sd_cl); 2096 if (*sd_m != NULL) { 2097 m_init(*sd_m, M_NOWAIT, MT_DATA, 0); 2098 uma_zfree(zone_mbuf, *sd_m); 2099 } 2100 } else { 2101 MPASS(*sd_cl == NULL); 2102 MPASS(*sd_m == NULL); 2103 } 2104 #if MEMORY_LOGGING 2105 fl->ifl_m_dequeued++; 2106 fl->ifl_cl_dequeued++; 2107 #endif 2108 *sd_cl = NULL; 2109 *sd_m = NULL; 2110 } 2111 #ifdef INVARIANTS 2112 for (i = 0; i < fl->ifl_size; i++) { 2113 MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); 2114 MPASS(fl->ifl_sds.ifsd_m[i] == NULL); 2115 } 2116 #endif 2117 /* 2118 * Reset free list values 2119 */ 2120 fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; 2121 bzero(idi->idi_vaddr, idi->idi_size); 2122 } 2123 2124 /********************************************************************* 2125 * 2126 * Initialize a free list and its buffers. 2127 * 2128 **********************************************************************/ 2129 static int 2130 iflib_fl_setup(iflib_fl_t fl) 2131 { 2132 iflib_rxq_t rxq = fl->ifl_rxq; 2133 if_ctx_t ctx = rxq->ifr_ctx; 2134 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2135 int qidx; 2136 2137 bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); 2138 /* 2139 ** Free current RX buffer structs and their mbufs 2140 */ 2141 iflib_fl_bufs_free(fl); 2142 /* Now replenish the mbufs */ 2143 MPASS(fl->ifl_credits == 0); 2144 qidx = rxq->ifr_fl_offset + fl->ifl_id; 2145 if (scctx->isc_rxd_buf_size[qidx] != 0) 2146 fl->ifl_buf_size = scctx->isc_rxd_buf_size[qidx]; 2147 else 2148 fl->ifl_buf_size = ctx->ifc_rx_mbuf_sz; 2149 /* 2150 * ifl_buf_size may be a driver-supplied value, so pull it up 2151 * to the selected mbuf size. 2152 */ 2153 fl->ifl_buf_size = iflib_get_mbuf_size_for(fl->ifl_buf_size); 2154 if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) 2155 ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; 2156 fl->ifl_cltype = m_gettype(fl->ifl_buf_size); 2157 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 2158 2159 2160 /* avoid pre-allocating zillions of clusters to an idle card 2161 * potentially speeding up attach 2162 */ 2163 (void) _iflib_fl_refill(ctx, fl, min(128, fl->ifl_size)); 2164 MPASS(min(128, fl->ifl_size) == fl->ifl_credits); 2165 if (min(128, fl->ifl_size) != fl->ifl_credits) 2166 return (ENOBUFS); 2167 /* 2168 * handle failure 2169 */ 2170 MPASS(rxq != NULL); 2171 MPASS(fl->ifl_ifdi != NULL); 2172 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 2173 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2174 return (0); 2175 } 2176 2177 /********************************************************************* 2178 * 2179 * Free receive ring data structures 2180 * 2181 **********************************************************************/ 2182 static void 2183 iflib_rx_sds_free(iflib_rxq_t rxq) 2184 { 2185 iflib_fl_t fl; 2186 int i, j; 2187 2188 if (rxq->ifr_fl != NULL) { 2189 for (i = 0; i < rxq->ifr_nfl; i++) { 2190 fl = &rxq->ifr_fl[i]; 2191 if (fl->ifl_buf_tag != NULL) { 2192 if (fl->ifl_sds.ifsd_map != NULL) { 2193 for (j = 0; j < fl->ifl_size; j++) { 2194 bus_dmamap_sync( 2195 fl->ifl_buf_tag, 2196 fl->ifl_sds.ifsd_map[j], 2197 BUS_DMASYNC_POSTREAD); 2198 bus_dmamap_unload( 2199 fl->ifl_buf_tag, 2200 fl->ifl_sds.ifsd_map[j]); 2201 bus_dmamap_destroy( 2202 fl->ifl_buf_tag, 2203 fl->ifl_sds.ifsd_map[j]); 2204 } 2205 } 2206 bus_dma_tag_destroy(fl->ifl_buf_tag); 2207 fl->ifl_buf_tag = NULL; 2208 } 2209 free(fl->ifl_sds.ifsd_m, M_IFLIB); 2210 free(fl->ifl_sds.ifsd_cl, M_IFLIB); 2211 free(fl->ifl_sds.ifsd_ba, M_IFLIB); 2212 free(fl->ifl_sds.ifsd_map, M_IFLIB); 2213 fl->ifl_sds.ifsd_m = NULL; 2214 fl->ifl_sds.ifsd_cl = NULL; 2215 fl->ifl_sds.ifsd_ba = NULL; 2216 fl->ifl_sds.ifsd_map = NULL; 2217 } 2218 free(rxq->ifr_fl, M_IFLIB); 2219 rxq->ifr_fl = NULL; 2220 free(rxq->ifr_ifdi, M_IFLIB); 2221 rxq->ifr_ifdi = NULL; 2222 rxq->ifr_cq_cidx = 0; 2223 } 2224 } 2225 2226 /* 2227 * Timer routine 2228 */ 2229 static void 2230 iflib_timer(void *arg) 2231 { 2232 iflib_txq_t txq = arg; 2233 if_ctx_t ctx = txq->ift_ctx; 2234 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2235 uint64_t this_tick = ticks; 2236 uint32_t reset_on = hz / 2; 2237 2238 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 2239 return; 2240 2241 /* 2242 ** Check on the state of the TX queue(s), this 2243 ** can be done without the lock because its RO 2244 ** and the HUNG state will be static if set. 2245 */ 2246 if (this_tick - txq->ift_last_timer_tick >= hz / 2) { 2247 txq->ift_last_timer_tick = this_tick; 2248 IFDI_TIMER(ctx, txq->ift_id); 2249 if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && 2250 ((txq->ift_cleaned_prev == txq->ift_cleaned) || 2251 (sctx->isc_pause_frames == 0))) 2252 goto hung; 2253 2254 if (txq->ift_qstatus != IFLIB_QUEUE_IDLE && 2255 ifmp_ring_is_stalled(txq->ift_br)) { 2256 KASSERT(ctx->ifc_link_state == LINK_STATE_UP, ("queue can't be marked as hung if interface is down")); 2257 txq->ift_qstatus = IFLIB_QUEUE_HUNG; 2258 } 2259 txq->ift_cleaned_prev = txq->ift_cleaned; 2260 } 2261 #ifdef DEV_NETMAP 2262 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 2263 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 2264 #endif 2265 /* handle any laggards */ 2266 if (txq->ift_db_pending) 2267 GROUPTASK_ENQUEUE(&txq->ift_task); 2268 2269 sctx->isc_pause_frames = 0; 2270 if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) 2271 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 2272 return; 2273 2274 hung: 2275 device_printf(ctx->ifc_dev, 2276 "Watchdog timeout (TX: %d desc avail: %d pidx: %d) -- resetting\n", 2277 txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); 2278 STATE_LOCK(ctx); 2279 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2280 ctx->ifc_flags |= (IFC_DO_WATCHDOG|IFC_DO_RESET); 2281 iflib_admin_intr_deferred(ctx); 2282 STATE_UNLOCK(ctx); 2283 } 2284 2285 static uint16_t 2286 iflib_get_mbuf_size_for(unsigned int size) 2287 { 2288 2289 if (size <= MCLBYTES) 2290 return (MCLBYTES); 2291 else 2292 return (MJUMPAGESIZE); 2293 } 2294 2295 static void 2296 iflib_calc_rx_mbuf_sz(if_ctx_t ctx) 2297 { 2298 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2299 2300 /* 2301 * XXX don't set the max_frame_size to larger 2302 * than the hardware can handle 2303 */ 2304 ctx->ifc_rx_mbuf_sz = 2305 iflib_get_mbuf_size_for(sctx->isc_max_frame_size); 2306 } 2307 2308 uint32_t 2309 iflib_get_rx_mbuf_sz(if_ctx_t ctx) 2310 { 2311 2312 return (ctx->ifc_rx_mbuf_sz); 2313 } 2314 2315 static void 2316 iflib_init_locked(if_ctx_t ctx) 2317 { 2318 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 2319 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2320 if_t ifp = ctx->ifc_ifp; 2321 iflib_fl_t fl; 2322 iflib_txq_t txq; 2323 iflib_rxq_t rxq; 2324 int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; 2325 2326 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2327 IFDI_INTR_DISABLE(ctx); 2328 2329 tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); 2330 tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); 2331 /* Set hardware offload abilities */ 2332 if_clearhwassist(ifp); 2333 if (if_getcapenable(ifp) & IFCAP_TXCSUM) 2334 if_sethwassistbits(ifp, tx_ip_csum_flags, 0); 2335 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) 2336 if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); 2337 if (if_getcapenable(ifp) & IFCAP_TSO4) 2338 if_sethwassistbits(ifp, CSUM_IP_TSO, 0); 2339 if (if_getcapenable(ifp) & IFCAP_TSO6) 2340 if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); 2341 2342 for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { 2343 CALLOUT_LOCK(txq); 2344 callout_stop(&txq->ift_timer); 2345 CALLOUT_UNLOCK(txq); 2346 iflib_netmap_txq_init(ctx, txq); 2347 } 2348 2349 /* 2350 * Calculate a suitable Rx mbuf size prior to calling IFDI_INIT, so 2351 * that drivers can use the value when setting up the hardware receive 2352 * buffers. 2353 */ 2354 iflib_calc_rx_mbuf_sz(ctx); 2355 2356 #ifdef INVARIANTS 2357 i = if_getdrvflags(ifp); 2358 #endif 2359 IFDI_INIT(ctx); 2360 MPASS(if_getdrvflags(ifp) == i); 2361 for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { 2362 /* XXX this should really be done on a per-queue basis */ 2363 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2364 MPASS(rxq->ifr_id == i); 2365 iflib_netmap_rxq_init(ctx, rxq); 2366 continue; 2367 } 2368 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 2369 if (iflib_fl_setup(fl)) { 2370 device_printf(ctx->ifc_dev, 2371 "setting up free list %d failed - " 2372 "check cluster settings\n", j); 2373 goto done; 2374 } 2375 } 2376 } 2377 done: 2378 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 2379 IFDI_INTR_ENABLE(ctx); 2380 txq = ctx->ifc_txqs; 2381 for (i = 0; i < sctx->isc_ntxqsets; i++, txq++) 2382 callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, 2383 txq->ift_timer.c_cpu); 2384 } 2385 2386 static int 2387 iflib_media_change(if_t ifp) 2388 { 2389 if_ctx_t ctx = if_getsoftc(ifp); 2390 int err; 2391 2392 CTX_LOCK(ctx); 2393 if ((err = IFDI_MEDIA_CHANGE(ctx)) == 0) 2394 iflib_init_locked(ctx); 2395 CTX_UNLOCK(ctx); 2396 return (err); 2397 } 2398 2399 static void 2400 iflib_media_status(if_t ifp, struct ifmediareq *ifmr) 2401 { 2402 if_ctx_t ctx = if_getsoftc(ifp); 2403 2404 CTX_LOCK(ctx); 2405 IFDI_UPDATE_ADMIN_STATUS(ctx); 2406 IFDI_MEDIA_STATUS(ctx, ifmr); 2407 CTX_UNLOCK(ctx); 2408 } 2409 2410 void 2411 iflib_stop(if_ctx_t ctx) 2412 { 2413 iflib_txq_t txq = ctx->ifc_txqs; 2414 iflib_rxq_t rxq = ctx->ifc_rxqs; 2415 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2416 if_shared_ctx_t sctx = ctx->ifc_sctx; 2417 iflib_dma_info_t di; 2418 iflib_fl_t fl; 2419 int i, j; 2420 2421 /* Tell the stack that the interface is no longer active */ 2422 if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); 2423 2424 IFDI_INTR_DISABLE(ctx); 2425 DELAY(1000); 2426 IFDI_STOP(ctx); 2427 DELAY(1000); 2428 2429 iflib_debug_reset(); 2430 /* Wait for current tx queue users to exit to disarm watchdog timer. */ 2431 for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { 2432 /* make sure all transmitters have completed before proceeding XXX */ 2433 2434 CALLOUT_LOCK(txq); 2435 callout_stop(&txq->ift_timer); 2436 CALLOUT_UNLOCK(txq); 2437 2438 /* clean any enqueued buffers */ 2439 iflib_ifmp_purge(txq); 2440 /* Free any existing tx buffers. */ 2441 for (j = 0; j < txq->ift_size; j++) { 2442 iflib_txsd_free(ctx, txq, j); 2443 } 2444 txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; 2445 txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; 2446 txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; 2447 txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; 2448 txq->ift_pullups = 0; 2449 ifmp_ring_reset_stats(txq->ift_br); 2450 for (j = 0, di = txq->ift_ifdi; j < sctx->isc_ntxqs; j++, di++) 2451 bzero((void *)di->idi_vaddr, di->idi_size); 2452 } 2453 for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { 2454 /* make sure all transmitters have completed before proceeding XXX */ 2455 2456 rxq->ifr_cq_cidx = 0; 2457 for (j = 0, di = rxq->ifr_ifdi; j < sctx->isc_nrxqs; j++, di++) 2458 bzero((void *)di->idi_vaddr, di->idi_size); 2459 /* also resets the free lists pidx/cidx */ 2460 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 2461 iflib_fl_bufs_free(fl); 2462 } 2463 } 2464 2465 static inline caddr_t 2466 calc_next_rxd(iflib_fl_t fl, int cidx) 2467 { 2468 qidx_t size; 2469 int nrxd; 2470 caddr_t start, end, cur, next; 2471 2472 nrxd = fl->ifl_size; 2473 size = fl->ifl_rxd_size; 2474 start = fl->ifl_ifdi->idi_vaddr; 2475 2476 if (__predict_false(size == 0)) 2477 return (start); 2478 cur = start + size*cidx; 2479 end = start + size*nrxd; 2480 next = CACHE_PTR_NEXT(cur); 2481 return (next < end ? next : start); 2482 } 2483 2484 static inline void 2485 prefetch_pkts(iflib_fl_t fl, int cidx) 2486 { 2487 int nextptr; 2488 int nrxd = fl->ifl_size; 2489 caddr_t next_rxd; 2490 2491 2492 nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); 2493 prefetch(&fl->ifl_sds.ifsd_m[nextptr]); 2494 prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); 2495 next_rxd = calc_next_rxd(fl, cidx); 2496 prefetch(next_rxd); 2497 prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); 2498 prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); 2499 prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); 2500 prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); 2501 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); 2502 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); 2503 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); 2504 prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); 2505 } 2506 2507 static struct mbuf * 2508 rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, bool unload, if_rxsd_t sd, 2509 int *pf_rv, if_rxd_info_t ri) 2510 { 2511 bus_dmamap_t map; 2512 iflib_fl_t fl; 2513 caddr_t payload; 2514 struct mbuf *m; 2515 int flid, cidx, len, next; 2516 2517 map = NULL; 2518 flid = irf->irf_flid; 2519 cidx = irf->irf_idx; 2520 fl = &rxq->ifr_fl[flid]; 2521 sd->ifsd_fl = fl; 2522 m = fl->ifl_sds.ifsd_m[cidx]; 2523 sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; 2524 fl->ifl_credits--; 2525 #if MEMORY_LOGGING 2526 fl->ifl_m_dequeued++; 2527 #endif 2528 if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) 2529 prefetch_pkts(fl, cidx); 2530 next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); 2531 prefetch(&fl->ifl_sds.ifsd_map[next]); 2532 map = fl->ifl_sds.ifsd_map[cidx]; 2533 2534 bus_dmamap_sync(fl->ifl_buf_tag, map, BUS_DMASYNC_POSTREAD); 2535 2536 if (rxq->pfil != NULL && PFIL_HOOKED_IN(rxq->pfil) && pf_rv != NULL && 2537 irf->irf_len != 0) { 2538 payload = *sd->ifsd_cl; 2539 payload += ri->iri_pad; 2540 len = ri->iri_len - ri->iri_pad; 2541 *pf_rv = pfil_run_hooks(rxq->pfil, payload, ri->iri_ifp, 2542 len | PFIL_MEMPTR | PFIL_IN, NULL); 2543 switch (*pf_rv) { 2544 case PFIL_DROPPED: 2545 case PFIL_CONSUMED: 2546 /* 2547 * The filter ate it. Everything is recycled. 2548 */ 2549 m = NULL; 2550 unload = 0; 2551 break; 2552 case PFIL_REALLOCED: 2553 /* 2554 * The filter copied it. Everything is recycled. 2555 */ 2556 m = pfil_mem2mbuf(payload); 2557 unload = 0; 2558 break; 2559 case PFIL_PASS: 2560 /* 2561 * Filter said it was OK, so receive like 2562 * normal 2563 */ 2564 fl->ifl_sds.ifsd_m[cidx] = NULL; 2565 break; 2566 default: 2567 MPASS(0); 2568 } 2569 } else { 2570 fl->ifl_sds.ifsd_m[cidx] = NULL; 2571 *pf_rv = PFIL_PASS; 2572 } 2573 2574 if (unload && irf->irf_len != 0) 2575 bus_dmamap_unload(fl->ifl_buf_tag, map); 2576 fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); 2577 if (__predict_false(fl->ifl_cidx == 0)) 2578 fl->ifl_gen = 0; 2579 bit_clear(fl->ifl_rx_bitmap, cidx); 2580 return (m); 2581 } 2582 2583 static struct mbuf * 2584 assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd, int *pf_rv) 2585 { 2586 struct mbuf *m, *mh, *mt; 2587 caddr_t cl; 2588 int *pf_rv_ptr, flags, i, padlen; 2589 bool consumed; 2590 2591 i = 0; 2592 mh = NULL; 2593 consumed = false; 2594 *pf_rv = PFIL_PASS; 2595 pf_rv_ptr = pf_rv; 2596 do { 2597 m = rxd_frag_to_sd(rxq, &ri->iri_frags[i], !consumed, sd, 2598 pf_rv_ptr, ri); 2599 2600 MPASS(*sd->ifsd_cl != NULL); 2601 2602 /* 2603 * Exclude zero-length frags & frags from 2604 * packets the filter has consumed or dropped 2605 */ 2606 if (ri->iri_frags[i].irf_len == 0 || consumed || 2607 *pf_rv == PFIL_CONSUMED || *pf_rv == PFIL_DROPPED) { 2608 if (mh == NULL) { 2609 /* everything saved here */ 2610 consumed = true; 2611 pf_rv_ptr = NULL; 2612 continue; 2613 } 2614 /* XXX we can save the cluster here, but not the mbuf */ 2615 m_init(m, M_NOWAIT, MT_DATA, 0); 2616 m_free(m); 2617 continue; 2618 } 2619 if (mh == NULL) { 2620 flags = M_PKTHDR|M_EXT; 2621 mh = mt = m; 2622 padlen = ri->iri_pad; 2623 } else { 2624 flags = M_EXT; 2625 mt->m_next = m; 2626 mt = m; 2627 /* assuming padding is only on the first fragment */ 2628 padlen = 0; 2629 } 2630 cl = *sd->ifsd_cl; 2631 *sd->ifsd_cl = NULL; 2632 2633 /* Can these two be made one ? */ 2634 m_init(m, M_NOWAIT, MT_DATA, flags); 2635 m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); 2636 /* 2637 * These must follow m_init and m_cljset 2638 */ 2639 m->m_data += padlen; 2640 ri->iri_len -= padlen; 2641 m->m_len = ri->iri_frags[i].irf_len; 2642 } while (++i < ri->iri_nfrags); 2643 2644 return (mh); 2645 } 2646 2647 /* 2648 * Process one software descriptor 2649 */ 2650 static struct mbuf * 2651 iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) 2652 { 2653 struct if_rxsd sd; 2654 struct mbuf *m; 2655 int pf_rv; 2656 2657 /* should I merge this back in now that the two paths are basically duplicated? */ 2658 if (ri->iri_nfrags == 1 && 2659 ri->iri_frags[0].irf_len != 0 && 2660 ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { 2661 m = rxd_frag_to_sd(rxq, &ri->iri_frags[0], false, &sd, 2662 &pf_rv, ri); 2663 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2664 return (m); 2665 if (pf_rv == PFIL_PASS) { 2666 m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); 2667 #ifndef __NO_STRICT_ALIGNMENT 2668 if (!IP_ALIGNED(m)) 2669 m->m_data += 2; 2670 #endif 2671 memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); 2672 m->m_len = ri->iri_frags[0].irf_len; 2673 } 2674 } else { 2675 m = assemble_segments(rxq, ri, &sd, &pf_rv); 2676 if (m == NULL) 2677 return (NULL); 2678 if (pf_rv != PFIL_PASS && pf_rv != PFIL_REALLOCED) 2679 return (m); 2680 } 2681 m->m_pkthdr.len = ri->iri_len; 2682 m->m_pkthdr.rcvif = ri->iri_ifp; 2683 m->m_flags |= ri->iri_flags; 2684 m->m_pkthdr.ether_vtag = ri->iri_vtag; 2685 m->m_pkthdr.flowid = ri->iri_flowid; 2686 M_HASHTYPE_SET(m, ri->iri_rsstype); 2687 m->m_pkthdr.csum_flags = ri->iri_csum_flags; 2688 m->m_pkthdr.csum_data = ri->iri_csum_data; 2689 return (m); 2690 } 2691 2692 #if defined(INET6) || defined(INET) 2693 static void 2694 iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) 2695 { 2696 CURVNET_SET(lc->ifp->if_vnet); 2697 #if defined(INET6) 2698 *v6 = V_ip6_forwarding; 2699 #endif 2700 #if defined(INET) 2701 *v4 = V_ipforwarding; 2702 #endif 2703 CURVNET_RESTORE(); 2704 } 2705 2706 /* 2707 * Returns true if it's possible this packet could be LROed. 2708 * if it returns false, it is guaranteed that tcp_lro_rx() 2709 * would not return zero. 2710 */ 2711 static bool 2712 iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) 2713 { 2714 struct ether_header *eh; 2715 2716 eh = mtod(m, struct ether_header *); 2717 switch (eh->ether_type) { 2718 #if defined(INET6) 2719 case htons(ETHERTYPE_IPV6): 2720 return (!v6_forwarding); 2721 #endif 2722 #if defined (INET) 2723 case htons(ETHERTYPE_IP): 2724 return (!v4_forwarding); 2725 #endif 2726 } 2727 2728 return false; 2729 } 2730 #else 2731 static void 2732 iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) 2733 { 2734 } 2735 #endif 2736 2737 static void 2738 _task_fn_rx_watchdog(void *context) 2739 { 2740 iflib_rxq_t rxq = context; 2741 2742 GROUPTASK_ENQUEUE(&rxq->ifr_task); 2743 } 2744 2745 static uint8_t 2746 iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) 2747 { 2748 if_t ifp; 2749 if_ctx_t ctx = rxq->ifr_ctx; 2750 if_shared_ctx_t sctx = ctx->ifc_sctx; 2751 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 2752 int avail, i; 2753 qidx_t *cidxp; 2754 struct if_rxd_info ri; 2755 int err, budget_left, rx_bytes, rx_pkts; 2756 iflib_fl_t fl; 2757 int lro_enabled; 2758 bool v4_forwarding, v6_forwarding, lro_possible; 2759 uint8_t retval = 0; 2760 2761 /* 2762 * XXX early demux data packets so that if_input processing only handles 2763 * acks in interrupt context 2764 */ 2765 struct mbuf *m, *mh, *mt, *mf; 2766 2767 NET_EPOCH_ASSERT(); 2768 2769 lro_possible = v4_forwarding = v6_forwarding = false; 2770 ifp = ctx->ifc_ifp; 2771 mh = mt = NULL; 2772 MPASS(budget > 0); 2773 rx_pkts = rx_bytes = 0; 2774 if (sctx->isc_flags & IFLIB_HAS_RXCQ) 2775 cidxp = &rxq->ifr_cq_cidx; 2776 else 2777 cidxp = &rxq->ifr_fl[0].ifl_cidx; 2778 if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { 2779 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2780 retval |= __iflib_fl_refill_all(ctx, fl); 2781 DBG_COUNTER_INC(rx_unavail); 2782 return (retval); 2783 } 2784 2785 /* pfil needs the vnet to be set */ 2786 CURVNET_SET_QUIET(ifp->if_vnet); 2787 for (budget_left = budget; budget_left > 0 && avail > 0;) { 2788 if (__predict_false(!CTX_ACTIVE(ctx))) { 2789 DBG_COUNTER_INC(rx_ctx_inactive); 2790 break; 2791 } 2792 /* 2793 * Reset client set fields to their default values 2794 */ 2795 rxd_info_zero(&ri); 2796 ri.iri_qsidx = rxq->ifr_id; 2797 ri.iri_cidx = *cidxp; 2798 ri.iri_ifp = ifp; 2799 ri.iri_frags = rxq->ifr_frags; 2800 err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); 2801 2802 if (err) 2803 goto err; 2804 rx_pkts += 1; 2805 rx_bytes += ri.iri_len; 2806 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 2807 *cidxp = ri.iri_cidx; 2808 /* Update our consumer index */ 2809 /* XXX NB: shurd - check if this is still safe */ 2810 while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) 2811 rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; 2812 /* was this only a completion queue message? */ 2813 if (__predict_false(ri.iri_nfrags == 0)) 2814 continue; 2815 } 2816 MPASS(ri.iri_nfrags != 0); 2817 MPASS(ri.iri_len != 0); 2818 2819 /* will advance the cidx on the corresponding free lists */ 2820 m = iflib_rxd_pkt_get(rxq, &ri); 2821 avail--; 2822 budget_left--; 2823 if (avail == 0 && budget_left) 2824 avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget_left); 2825 2826 if (__predict_false(m == NULL)) 2827 continue; 2828 2829 /* imm_pkt: -- cxgb */ 2830 if (mh == NULL) 2831 mh = mt = m; 2832 else { 2833 mt->m_nextpkt = m; 2834 mt = m; 2835 } 2836 } 2837 CURVNET_RESTORE(); 2838 /* make sure that we can refill faster than drain */ 2839 for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) 2840 retval |= __iflib_fl_refill_all(ctx, fl); 2841 2842 lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); 2843 if (lro_enabled) 2844 iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); 2845 mt = mf = NULL; 2846 while (mh != NULL) { 2847 m = mh; 2848 mh = mh->m_nextpkt; 2849 m->m_nextpkt = NULL; 2850 #ifndef __NO_STRICT_ALIGNMENT 2851 if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) 2852 continue; 2853 #endif 2854 rx_bytes += m->m_pkthdr.len; 2855 rx_pkts++; 2856 #if defined(INET6) || defined(INET) 2857 if (lro_enabled) { 2858 if (!lro_possible) { 2859 lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); 2860 if (lro_possible && mf != NULL) { 2861 ifp->if_input(ifp, mf); 2862 DBG_COUNTER_INC(rx_if_input); 2863 mt = mf = NULL; 2864 } 2865 } 2866 if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == 2867 (CSUM_L4_CALC|CSUM_L4_VALID)) { 2868 if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) 2869 continue; 2870 } 2871 } 2872 #endif 2873 if (lro_possible) { 2874 ifp->if_input(ifp, m); 2875 DBG_COUNTER_INC(rx_if_input); 2876 continue; 2877 } 2878 2879 if (mf == NULL) 2880 mf = m; 2881 if (mt != NULL) 2882 mt->m_nextpkt = m; 2883 mt = m; 2884 } 2885 if (mf != NULL) { 2886 ifp->if_input(ifp, mf); 2887 DBG_COUNTER_INC(rx_if_input); 2888 } 2889 2890 if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); 2891 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); 2892 2893 /* 2894 * Flush any outstanding LRO work 2895 */ 2896 #if defined(INET6) || defined(INET) 2897 tcp_lro_flush_all(&rxq->ifr_lc); 2898 #endif 2899 if (avail != 0 || iflib_rxd_avail(ctx, rxq, *cidxp, 1) != 0) 2900 retval |= IFLIB_RXEOF_MORE; 2901 return (retval); 2902 err: 2903 STATE_LOCK(ctx); 2904 ctx->ifc_flags |= IFC_DO_RESET; 2905 iflib_admin_intr_deferred(ctx); 2906 STATE_UNLOCK(ctx); 2907 return (0); 2908 } 2909 2910 #define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) 2911 static inline qidx_t 2912 txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) 2913 { 2914 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2915 qidx_t minthresh = txq->ift_size / 8; 2916 if (in_use > 4*minthresh) 2917 return (notify_count); 2918 if (in_use > 2*minthresh) 2919 return (notify_count >> 1); 2920 if (in_use > minthresh) 2921 return (notify_count >> 3); 2922 return (0); 2923 } 2924 2925 static inline qidx_t 2926 txq_max_rs_deferred(iflib_txq_t txq) 2927 { 2928 qidx_t notify_count = TXD_NOTIFY_COUNT(txq); 2929 qidx_t minthresh = txq->ift_size / 8; 2930 if (txq->ift_in_use > 4*minthresh) 2931 return (notify_count); 2932 if (txq->ift_in_use > 2*minthresh) 2933 return (notify_count >> 1); 2934 if (txq->ift_in_use > minthresh) 2935 return (notify_count >> 2); 2936 return (2); 2937 } 2938 2939 #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) 2940 #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) 2941 2942 #define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) 2943 #define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) 2944 #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) 2945 2946 /* forward compatibility for cxgb */ 2947 #define FIRST_QSET(ctx) 0 2948 #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) 2949 #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) 2950 #define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) 2951 #define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) 2952 2953 /* XXX we should be setting this to something other than zero */ 2954 #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) 2955 #define MAX_TX_DESC(ctx) max((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max, \ 2956 (ctx)->ifc_softc_ctx.isc_tx_nsegments) 2957 2958 static inline bool 2959 iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) 2960 { 2961 qidx_t dbval, max; 2962 bool rang; 2963 2964 rang = false; 2965 max = TXQ_MAX_DB_DEFERRED(txq, in_use); 2966 if (ring || txq->ift_db_pending >= max) { 2967 dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; 2968 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 2969 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2970 ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); 2971 txq->ift_db_pending = txq->ift_npending = 0; 2972 rang = true; 2973 } 2974 return (rang); 2975 } 2976 2977 #ifdef PKT_DEBUG 2978 static void 2979 print_pkt(if_pkt_info_t pi) 2980 { 2981 printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", 2982 pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); 2983 printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", 2984 pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); 2985 printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", 2986 pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); 2987 } 2988 #endif 2989 2990 #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) 2991 #define IS_TX_OFFLOAD4(pi) ((pi)->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP_TSO)) 2992 #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) 2993 #define IS_TX_OFFLOAD6(pi) ((pi)->ipi_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_TSO)) 2994 2995 static int 2996 iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) 2997 { 2998 if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; 2999 struct ether_vlan_header *eh; 3000 struct mbuf *m; 3001 3002 m = *mp; 3003 if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && 3004 M_WRITABLE(m) == 0) { 3005 if ((m = m_dup(m, M_NOWAIT)) == NULL) { 3006 return (ENOMEM); 3007 } else { 3008 m_freem(*mp); 3009 DBG_COUNTER_INC(tx_frees); 3010 *mp = m; 3011 } 3012 } 3013 3014 /* 3015 * Determine where frame payload starts. 3016 * Jump over vlan headers if already present, 3017 * helpful for QinQ too. 3018 */ 3019 if (__predict_false(m->m_len < sizeof(*eh))) { 3020 txq->ift_pullups++; 3021 if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) 3022 return (ENOMEM); 3023 } 3024 eh = mtod(m, struct ether_vlan_header *); 3025 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3026 pi->ipi_etype = ntohs(eh->evl_proto); 3027 pi->ipi_ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3028 } else { 3029 pi->ipi_etype = ntohs(eh->evl_encap_proto); 3030 pi->ipi_ehdrlen = ETHER_HDR_LEN; 3031 } 3032 3033 switch (pi->ipi_etype) { 3034 #ifdef INET 3035 case ETHERTYPE_IP: 3036 { 3037 struct mbuf *n; 3038 struct ip *ip = NULL; 3039 struct tcphdr *th = NULL; 3040 int minthlen; 3041 3042 minthlen = min(m->m_pkthdr.len, pi->ipi_ehdrlen + sizeof(*ip) + sizeof(*th)); 3043 if (__predict_false(m->m_len < minthlen)) { 3044 /* 3045 * if this code bloat is causing too much of a hit 3046 * move it to a separate function and mark it noinline 3047 */ 3048 if (m->m_len == pi->ipi_ehdrlen) { 3049 n = m->m_next; 3050 MPASS(n); 3051 if (n->m_len >= sizeof(*ip)) { 3052 ip = (struct ip *)n->m_data; 3053 if (n->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3054 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3055 } else { 3056 txq->ift_pullups++; 3057 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3058 return (ENOMEM); 3059 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3060 } 3061 } else { 3062 txq->ift_pullups++; 3063 if (__predict_false((m = m_pullup(m, minthlen)) == NULL)) 3064 return (ENOMEM); 3065 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3066 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3067 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3068 } 3069 } else { 3070 ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); 3071 if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) 3072 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 3073 } 3074 pi->ipi_ip_hlen = ip->ip_hl << 2; 3075 pi->ipi_ipproto = ip->ip_p; 3076 pi->ipi_flags |= IPI_TX_IPV4; 3077 3078 /* TCP checksum offload may require TCP header length */ 3079 if (IS_TX_OFFLOAD4(pi)) { 3080 if (__predict_true(pi->ipi_ipproto == IPPROTO_TCP)) { 3081 if (__predict_false(th == NULL)) { 3082 txq->ift_pullups++; 3083 if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) 3084 return (ENOMEM); 3085 th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); 3086 } 3087 pi->ipi_tcp_hflags = th->th_flags; 3088 pi->ipi_tcp_hlen = th->th_off << 2; 3089 pi->ipi_tcp_seq = th->th_seq; 3090 } 3091 if (IS_TSO4(pi)) { 3092 if (__predict_false(ip->ip_p != IPPROTO_TCP)) 3093 return (ENXIO); 3094 /* 3095 * TSO always requires hardware checksum offload. 3096 */ 3097 pi->ipi_csum_flags |= (CSUM_IP_TCP | CSUM_IP); 3098 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3099 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3100 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3101 if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { 3102 ip->ip_sum = 0; 3103 ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); 3104 } 3105 } 3106 } 3107 if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) 3108 ip->ip_sum = 0; 3109 3110 break; 3111 } 3112 #endif 3113 #ifdef INET6 3114 case ETHERTYPE_IPV6: 3115 { 3116 struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); 3117 struct tcphdr *th; 3118 pi->ipi_ip_hlen = sizeof(struct ip6_hdr); 3119 3120 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { 3121 txq->ift_pullups++; 3122 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) 3123 return (ENOMEM); 3124 } 3125 th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); 3126 3127 /* XXX-BZ this will go badly in case of ext hdrs. */ 3128 pi->ipi_ipproto = ip6->ip6_nxt; 3129 pi->ipi_flags |= IPI_TX_IPV6; 3130 3131 /* TCP checksum offload may require TCP header length */ 3132 if (IS_TX_OFFLOAD6(pi)) { 3133 if (pi->ipi_ipproto == IPPROTO_TCP) { 3134 if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { 3135 txq->ift_pullups++; 3136 if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) 3137 return (ENOMEM); 3138 } 3139 pi->ipi_tcp_hflags = th->th_flags; 3140 pi->ipi_tcp_hlen = th->th_off << 2; 3141 pi->ipi_tcp_seq = th->th_seq; 3142 } 3143 if (IS_TSO6(pi)) { 3144 if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) 3145 return (ENXIO); 3146 /* 3147 * TSO always requires hardware checksum offload. 3148 */ 3149 pi->ipi_csum_flags |= CSUM_IP6_TCP; 3150 th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); 3151 pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; 3152 } 3153 } 3154 break; 3155 } 3156 #endif 3157 default: 3158 pi->ipi_csum_flags &= ~CSUM_OFFLOAD; 3159 pi->ipi_ip_hlen = 0; 3160 break; 3161 } 3162 *mp = m; 3163 3164 return (0); 3165 } 3166 3167 /* 3168 * If dodgy hardware rejects the scatter gather chain we've handed it 3169 * we'll need to remove the mbuf chain from ifsg_m[] before we can add the 3170 * m_defrag'd mbufs 3171 */ 3172 static __noinline struct mbuf * 3173 iflib_remove_mbuf(iflib_txq_t txq) 3174 { 3175 int ntxd, pidx; 3176 struct mbuf *m, **ifsd_m; 3177 3178 ifsd_m = txq->ift_sds.ifsd_m; 3179 ntxd = txq->ift_size; 3180 pidx = txq->ift_pidx & (ntxd - 1); 3181 ifsd_m = txq->ift_sds.ifsd_m; 3182 m = ifsd_m[pidx]; 3183 ifsd_m[pidx] = NULL; 3184 bus_dmamap_unload(txq->ift_buf_tag, txq->ift_sds.ifsd_map[pidx]); 3185 if (txq->ift_sds.ifsd_tso_map != NULL) 3186 bus_dmamap_unload(txq->ift_tso_buf_tag, 3187 txq->ift_sds.ifsd_tso_map[pidx]); 3188 #if MEMORY_LOGGING 3189 txq->ift_dequeued++; 3190 #endif 3191 return (m); 3192 } 3193 3194 static inline caddr_t 3195 calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) 3196 { 3197 qidx_t size; 3198 int ntxd; 3199 caddr_t start, end, cur, next; 3200 3201 ntxd = txq->ift_size; 3202 size = txq->ift_txd_size[qid]; 3203 start = txq->ift_ifdi[qid].idi_vaddr; 3204 3205 if (__predict_false(size == 0)) 3206 return (start); 3207 cur = start + size*cidx; 3208 end = start + size*ntxd; 3209 next = CACHE_PTR_NEXT(cur); 3210 return (next < end ? next : start); 3211 } 3212 3213 /* 3214 * Pad an mbuf to ensure a minimum ethernet frame size. 3215 * min_frame_size is the frame size (less CRC) to pad the mbuf to 3216 */ 3217 static __noinline int 3218 iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) 3219 { 3220 /* 3221 * 18 is enough bytes to pad an ARP packet to 46 bytes, and 3222 * and ARP message is the smallest common payload I can think of 3223 */ 3224 static char pad[18]; /* just zeros */ 3225 int n; 3226 struct mbuf *new_head; 3227 3228 if (!M_WRITABLE(*m_head)) { 3229 new_head = m_dup(*m_head, M_NOWAIT); 3230 if (new_head == NULL) { 3231 m_freem(*m_head); 3232 device_printf(dev, "cannot pad short frame, m_dup() failed"); 3233 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3234 DBG_COUNTER_INC(tx_frees); 3235 return ENOMEM; 3236 } 3237 m_freem(*m_head); 3238 *m_head = new_head; 3239 } 3240 3241 for (n = min_frame_size - (*m_head)->m_pkthdr.len; 3242 n > 0; n -= sizeof(pad)) 3243 if (!m_append(*m_head, min(n, sizeof(pad)), pad)) 3244 break; 3245 3246 if (n > 0) { 3247 m_freem(*m_head); 3248 device_printf(dev, "cannot pad short frame\n"); 3249 DBG_COUNTER_INC(encap_pad_mbuf_fail); 3250 DBG_COUNTER_INC(tx_frees); 3251 return (ENOBUFS); 3252 } 3253 3254 return 0; 3255 } 3256 3257 static int 3258 iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) 3259 { 3260 if_ctx_t ctx; 3261 if_shared_ctx_t sctx; 3262 if_softc_ctx_t scctx; 3263 bus_dma_tag_t buf_tag; 3264 bus_dma_segment_t *segs; 3265 struct mbuf *m_head, **ifsd_m; 3266 void *next_txd; 3267 bus_dmamap_t map; 3268 struct if_pkt_info pi; 3269 int remap = 0; 3270 int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; 3271 3272 ctx = txq->ift_ctx; 3273 sctx = ctx->ifc_sctx; 3274 scctx = &ctx->ifc_softc_ctx; 3275 segs = txq->ift_segs; 3276 ntxd = txq->ift_size; 3277 m_head = *m_headp; 3278 map = NULL; 3279 3280 /* 3281 * If we're doing TSO the next descriptor to clean may be quite far ahead 3282 */ 3283 cidx = txq->ift_cidx; 3284 pidx = txq->ift_pidx; 3285 if (ctx->ifc_flags & IFC_PREFETCH) { 3286 next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); 3287 if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { 3288 next_txd = calc_next_txd(txq, cidx, 0); 3289 prefetch(next_txd); 3290 } 3291 3292 /* prefetch the next cache line of mbuf pointers and flags */ 3293 prefetch(&txq->ift_sds.ifsd_m[next]); 3294 prefetch(&txq->ift_sds.ifsd_map[next]); 3295 next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); 3296 } 3297 map = txq->ift_sds.ifsd_map[pidx]; 3298 ifsd_m = txq->ift_sds.ifsd_m; 3299 3300 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 3301 buf_tag = txq->ift_tso_buf_tag; 3302 max_segs = scctx->isc_tx_tso_segments_max; 3303 map = txq->ift_sds.ifsd_tso_map[pidx]; 3304 MPASS(buf_tag != NULL); 3305 MPASS(max_segs > 0); 3306 } else { 3307 buf_tag = txq->ift_buf_tag; 3308 max_segs = scctx->isc_tx_nsegments; 3309 map = txq->ift_sds.ifsd_map[pidx]; 3310 } 3311 if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && 3312 __predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { 3313 err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); 3314 if (err) { 3315 DBG_COUNTER_INC(encap_txd_encap_fail); 3316 return err; 3317 } 3318 } 3319 m_head = *m_headp; 3320 3321 pkt_info_zero(&pi); 3322 pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); 3323 pi.ipi_pidx = pidx; 3324 pi.ipi_qsidx = txq->ift_id; 3325 pi.ipi_len = m_head->m_pkthdr.len; 3326 pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; 3327 pi.ipi_vtag = M_HAS_VLANTAG(m_head) ? m_head->m_pkthdr.ether_vtag : 0; 3328 3329 /* deliberate bitwise OR to make one condition */ 3330 if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { 3331 if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) { 3332 DBG_COUNTER_INC(encap_txd_encap_fail); 3333 return (err); 3334 } 3335 m_head = *m_headp; 3336 } 3337 3338 retry: 3339 err = bus_dmamap_load_mbuf_sg(buf_tag, map, m_head, segs, &nsegs, 3340 BUS_DMA_NOWAIT); 3341 defrag: 3342 if (__predict_false(err)) { 3343 switch (err) { 3344 case EFBIG: 3345 /* try collapse once and defrag once */ 3346 if (remap == 0) { 3347 m_head = m_collapse(*m_headp, M_NOWAIT, max_segs); 3348 /* try defrag if collapsing fails */ 3349 if (m_head == NULL) 3350 remap++; 3351 } 3352 if (remap == 1) { 3353 txq->ift_mbuf_defrag++; 3354 m_head = m_defrag(*m_headp, M_NOWAIT); 3355 } 3356 /* 3357 * remap should never be >1 unless bus_dmamap_load_mbuf_sg 3358 * failed to map an mbuf that was run through m_defrag 3359 */ 3360 MPASS(remap <= 1); 3361 if (__predict_false(m_head == NULL || remap > 1)) 3362 goto defrag_failed; 3363 remap++; 3364 *m_headp = m_head; 3365 goto retry; 3366 break; 3367 case ENOMEM: 3368 txq->ift_no_tx_dma_setup++; 3369 break; 3370 default: 3371 txq->ift_no_tx_dma_setup++; 3372 m_freem(*m_headp); 3373 DBG_COUNTER_INC(tx_frees); 3374 *m_headp = NULL; 3375 break; 3376 } 3377 txq->ift_map_failed++; 3378 DBG_COUNTER_INC(encap_load_mbuf_fail); 3379 DBG_COUNTER_INC(encap_txd_encap_fail); 3380 return (err); 3381 } 3382 ifsd_m[pidx] = m_head; 3383 /* 3384 * XXX assumes a 1 to 1 relationship between segments and 3385 * descriptors - this does not hold true on all drivers, e.g. 3386 * cxgb 3387 */ 3388 if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { 3389 txq->ift_no_desc_avail++; 3390 bus_dmamap_unload(buf_tag, map); 3391 DBG_COUNTER_INC(encap_txq_avail_fail); 3392 DBG_COUNTER_INC(encap_txd_encap_fail); 3393 if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) 3394 GROUPTASK_ENQUEUE(&txq->ift_task); 3395 return (ENOBUFS); 3396 } 3397 /* 3398 * On Intel cards we can greatly reduce the number of TX interrupts 3399 * we see by only setting report status on every Nth descriptor. 3400 * However, this also means that the driver will need to keep track 3401 * of the descriptors that RS was set on to check them for the DD bit. 3402 */ 3403 txq->ift_rs_pending += nsegs + 1; 3404 if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || 3405 iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs) <= MAX_TX_DESC(ctx) + 2) { 3406 pi.ipi_flags |= IPI_TX_INTR; 3407 txq->ift_rs_pending = 0; 3408 } 3409 3410 pi.ipi_segs = segs; 3411 pi.ipi_nsegs = nsegs; 3412 3413 MPASS(pidx >= 0 && pidx < txq->ift_size); 3414 #ifdef PKT_DEBUG 3415 print_pkt(&pi); 3416 #endif 3417 if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { 3418 bus_dmamap_sync(buf_tag, map, BUS_DMASYNC_PREWRITE); 3419 DBG_COUNTER_INC(tx_encap); 3420 MPASS(pi.ipi_new_pidx < txq->ift_size); 3421 3422 ndesc = pi.ipi_new_pidx - pi.ipi_pidx; 3423 if (pi.ipi_new_pidx < pi.ipi_pidx) { 3424 ndesc += txq->ift_size; 3425 txq->ift_gen = 1; 3426 } 3427 /* 3428 * drivers can need as many as 3429 * two sentinels 3430 */ 3431 MPASS(ndesc <= pi.ipi_nsegs + 2); 3432 MPASS(pi.ipi_new_pidx != pidx); 3433 MPASS(ndesc > 0); 3434 txq->ift_in_use += ndesc; 3435 3436 /* 3437 * We update the last software descriptor again here because there may 3438 * be a sentinel and/or there may be more mbufs than segments 3439 */ 3440 txq->ift_pidx = pi.ipi_new_pidx; 3441 txq->ift_npending += pi.ipi_ndescs; 3442 } else { 3443 *m_headp = m_head = iflib_remove_mbuf(txq); 3444 if (err == EFBIG) { 3445 txq->ift_txd_encap_efbig++; 3446 if (remap < 2) { 3447 remap = 1; 3448 goto defrag; 3449 } 3450 } 3451 goto defrag_failed; 3452 } 3453 /* 3454 * err can't possibly be non-zero here, so we don't neet to test it 3455 * to see if we need to DBG_COUNTER_INC(encap_txd_encap_fail). 3456 */ 3457 return (err); 3458 3459 defrag_failed: 3460 txq->ift_mbuf_defrag_failed++; 3461 txq->ift_map_failed++; 3462 m_freem(*m_headp); 3463 DBG_COUNTER_INC(tx_frees); 3464 *m_headp = NULL; 3465 DBG_COUNTER_INC(encap_txd_encap_fail); 3466 return (ENOMEM); 3467 } 3468 3469 static void 3470 iflib_tx_desc_free(iflib_txq_t txq, int n) 3471 { 3472 uint32_t qsize, cidx, mask, gen; 3473 struct mbuf *m, **ifsd_m; 3474 bool do_prefetch; 3475 3476 cidx = txq->ift_cidx; 3477 gen = txq->ift_gen; 3478 qsize = txq->ift_size; 3479 mask = qsize-1; 3480 ifsd_m = txq->ift_sds.ifsd_m; 3481 do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); 3482 3483 while (n-- > 0) { 3484 if (do_prefetch) { 3485 prefetch(ifsd_m[(cidx + 3) & mask]); 3486 prefetch(ifsd_m[(cidx + 4) & mask]); 3487 } 3488 if ((m = ifsd_m[cidx]) != NULL) { 3489 prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); 3490 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 3491 bus_dmamap_sync(txq->ift_tso_buf_tag, 3492 txq->ift_sds.ifsd_tso_map[cidx], 3493 BUS_DMASYNC_POSTWRITE); 3494 bus_dmamap_unload(txq->ift_tso_buf_tag, 3495 txq->ift_sds.ifsd_tso_map[cidx]); 3496 } else { 3497 bus_dmamap_sync(txq->ift_buf_tag, 3498 txq->ift_sds.ifsd_map[cidx], 3499 BUS_DMASYNC_POSTWRITE); 3500 bus_dmamap_unload(txq->ift_buf_tag, 3501 txq->ift_sds.ifsd_map[cidx]); 3502 } 3503 /* XXX we don't support any drivers that batch packets yet */ 3504 MPASS(m->m_nextpkt == NULL); 3505 m_freem(m); 3506 ifsd_m[cidx] = NULL; 3507 #if MEMORY_LOGGING 3508 txq->ift_dequeued++; 3509 #endif 3510 DBG_COUNTER_INC(tx_frees); 3511 } 3512 if (__predict_false(++cidx == qsize)) { 3513 cidx = 0; 3514 gen = 0; 3515 } 3516 } 3517 txq->ift_cidx = cidx; 3518 txq->ift_gen = gen; 3519 } 3520 3521 static __inline int 3522 iflib_completed_tx_reclaim(iflib_txq_t txq, int thresh) 3523 { 3524 int reclaim; 3525 if_ctx_t ctx = txq->ift_ctx; 3526 3527 KASSERT(thresh >= 0, ("invalid threshold to reclaim")); 3528 MPASS(thresh /*+ MAX_TX_DESC(txq->ift_ctx) */ < txq->ift_size); 3529 3530 /* 3531 * Need a rate-limiting check so that this isn't called every time 3532 */ 3533 iflib_tx_credits_update(ctx, txq); 3534 reclaim = DESC_RECLAIMABLE(txq); 3535 3536 if (reclaim <= thresh /* + MAX_TX_DESC(txq->ift_ctx) */) { 3537 #ifdef INVARIANTS 3538 if (iflib_verbose_debug) { 3539 printf("%s processed=%ju cleaned=%ju tx_nsegments=%d reclaim=%d thresh=%d\n", __FUNCTION__, 3540 txq->ift_processed, txq->ift_cleaned, txq->ift_ctx->ifc_softc_ctx.isc_tx_nsegments, 3541 reclaim, thresh); 3542 3543 } 3544 #endif 3545 return (0); 3546 } 3547 iflib_tx_desc_free(txq, reclaim); 3548 txq->ift_cleaned += reclaim; 3549 txq->ift_in_use -= reclaim; 3550 3551 return (reclaim); 3552 } 3553 3554 static struct mbuf ** 3555 _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) 3556 { 3557 int next, size; 3558 struct mbuf **items; 3559 3560 size = r->size; 3561 next = (cidx + CACHE_PTR_INCREMENT) & (size-1); 3562 items = __DEVOLATILE(struct mbuf **, &r->items[0]); 3563 3564 prefetch(items[(cidx + offset) & (size-1)]); 3565 if (remaining > 1) { 3566 prefetch2cachelines(&items[next]); 3567 prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); 3568 prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); 3569 prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); 3570 } 3571 return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); 3572 } 3573 3574 static void 3575 iflib_txq_check_drain(iflib_txq_t txq, int budget) 3576 { 3577 3578 ifmp_ring_check_drainage(txq->ift_br, budget); 3579 } 3580 3581 static uint32_t 3582 iflib_txq_can_drain(struct ifmp_ring *r) 3583 { 3584 iflib_txq_t txq = r->cookie; 3585 if_ctx_t ctx = txq->ift_ctx; 3586 3587 if (TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) 3588 return (1); 3589 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3590 BUS_DMASYNC_POSTREAD); 3591 return (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, 3592 false)); 3593 } 3594 3595 static uint32_t 3596 iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3597 { 3598 iflib_txq_t txq = r->cookie; 3599 if_ctx_t ctx = txq->ift_ctx; 3600 if_t ifp = ctx->ifc_ifp; 3601 struct mbuf *m, **mp; 3602 int avail, bytes_sent, consumed, count, err, i, in_use_prev; 3603 int mcast_sent, pkt_sent, reclaimed, txq_avail; 3604 bool do_prefetch, rang, ring; 3605 3606 if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || 3607 !LINK_ACTIVE(ctx))) { 3608 DBG_COUNTER_INC(txq_drain_notready); 3609 return (0); 3610 } 3611 reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 3612 rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); 3613 avail = IDXDIFF(pidx, cidx, r->size); 3614 if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { 3615 DBG_COUNTER_INC(txq_drain_flushing); 3616 for (i = 0; i < avail; i++) { 3617 if (__predict_true(r->items[(cidx + i) & (r->size-1)] != (void *)txq)) 3618 m_free(r->items[(cidx + i) & (r->size-1)]); 3619 r->items[(cidx + i) & (r->size-1)] = NULL; 3620 } 3621 return (avail); 3622 } 3623 3624 if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { 3625 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3626 CALLOUT_LOCK(txq); 3627 callout_stop(&txq->ift_timer); 3628 CALLOUT_UNLOCK(txq); 3629 DBG_COUNTER_INC(txq_drain_oactive); 3630 return (0); 3631 } 3632 if (reclaimed) 3633 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3634 consumed = mcast_sent = bytes_sent = pkt_sent = 0; 3635 count = MIN(avail, TX_BATCH_SIZE); 3636 #ifdef INVARIANTS 3637 if (iflib_verbose_debug) 3638 printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, 3639 avail, ctx->ifc_flags, TXQ_AVAIL(txq)); 3640 #endif 3641 do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); 3642 txq_avail = TXQ_AVAIL(txq); 3643 err = 0; 3644 for (i = 0; i < count && txq_avail > MAX_TX_DESC(ctx) + 2; i++) { 3645 int rem = do_prefetch ? count - i : 0; 3646 3647 mp = _ring_peek_one(r, cidx, i, rem); 3648 MPASS(mp != NULL && *mp != NULL); 3649 if (__predict_false(*mp == (struct mbuf *)txq)) { 3650 consumed++; 3651 continue; 3652 } 3653 in_use_prev = txq->ift_in_use; 3654 err = iflib_encap(txq, mp); 3655 if (__predict_false(err)) { 3656 /* no room - bail out */ 3657 if (err == ENOBUFS) 3658 break; 3659 consumed++; 3660 /* we can't send this packet - skip it */ 3661 continue; 3662 } 3663 consumed++; 3664 pkt_sent++; 3665 m = *mp; 3666 DBG_COUNTER_INC(tx_sent); 3667 bytes_sent += m->m_pkthdr.len; 3668 mcast_sent += !!(m->m_flags & M_MCAST); 3669 txq_avail = TXQ_AVAIL(txq); 3670 3671 txq->ift_db_pending += (txq->ift_in_use - in_use_prev); 3672 ETHER_BPF_MTAP(ifp, m); 3673 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 3674 break; 3675 rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); 3676 } 3677 3678 /* deliberate use of bitwise or to avoid gratuitous short-circuit */ 3679 ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); 3680 iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); 3681 if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); 3682 if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); 3683 if (mcast_sent) 3684 if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); 3685 #ifdef INVARIANTS 3686 if (iflib_verbose_debug) 3687 printf("consumed=%d\n", consumed); 3688 #endif 3689 return (consumed); 3690 } 3691 3692 static uint32_t 3693 iflib_txq_drain_always(struct ifmp_ring *r) 3694 { 3695 return (1); 3696 } 3697 3698 static uint32_t 3699 iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) 3700 { 3701 int i, avail; 3702 struct mbuf **mp; 3703 iflib_txq_t txq; 3704 3705 txq = r->cookie; 3706 3707 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 3708 CALLOUT_LOCK(txq); 3709 callout_stop(&txq->ift_timer); 3710 CALLOUT_UNLOCK(txq); 3711 3712 avail = IDXDIFF(pidx, cidx, r->size); 3713 for (i = 0; i < avail; i++) { 3714 mp = _ring_peek_one(r, cidx, i, avail - i); 3715 if (__predict_false(*mp == (struct mbuf *)txq)) 3716 continue; 3717 m_freem(*mp); 3718 DBG_COUNTER_INC(tx_frees); 3719 } 3720 MPASS(ifmp_ring_is_stalled(r) == 0); 3721 return (avail); 3722 } 3723 3724 static void 3725 iflib_ifmp_purge(iflib_txq_t txq) 3726 { 3727 struct ifmp_ring *r; 3728 3729 r = txq->ift_br; 3730 r->drain = iflib_txq_drain_free; 3731 r->can_drain = iflib_txq_drain_always; 3732 3733 ifmp_ring_check_drainage(r, r->size); 3734 3735 r->drain = iflib_txq_drain; 3736 r->can_drain = iflib_txq_can_drain; 3737 } 3738 3739 static void 3740 _task_fn_tx(void *context) 3741 { 3742 iflib_txq_t txq = context; 3743 if_ctx_t ctx = txq->ift_ctx; 3744 #if defined(ALTQ) || defined(DEV_NETMAP) 3745 if_t ifp = ctx->ifc_ifp; 3746 #endif 3747 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3748 3749 #ifdef IFLIB_DIAGNOSTICS 3750 txq->ift_cpu_exec_count[curcpu]++; 3751 #endif 3752 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) 3753 return; 3754 #ifdef DEV_NETMAP 3755 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 3756 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 3757 BUS_DMASYNC_POSTREAD); 3758 if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) 3759 netmap_tx_irq(ifp, txq->ift_id); 3760 if (ctx->ifc_flags & IFC_LEGACY) 3761 IFDI_INTR_ENABLE(ctx); 3762 else 3763 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3764 return; 3765 } 3766 #endif 3767 #ifdef ALTQ 3768 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 3769 iflib_altq_if_start(ifp); 3770 #endif 3771 if (txq->ift_db_pending) 3772 ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE, abdicate); 3773 else if (!abdicate) 3774 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3775 /* 3776 * When abdicating, we always need to check drainage, not just when we don't enqueue 3777 */ 3778 if (abdicate) 3779 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 3780 if (ctx->ifc_flags & IFC_LEGACY) 3781 IFDI_INTR_ENABLE(ctx); 3782 else 3783 IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); 3784 } 3785 3786 static void 3787 _task_fn_rx(void *context) 3788 { 3789 iflib_rxq_t rxq = context; 3790 if_ctx_t ctx = rxq->ifr_ctx; 3791 uint8_t more; 3792 uint16_t budget; 3793 3794 #ifdef IFLIB_DIAGNOSTICS 3795 rxq->ifr_cpu_exec_count[curcpu]++; 3796 #endif 3797 DBG_COUNTER_INC(task_fn_rxs); 3798 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3799 return; 3800 #ifdef DEV_NETMAP 3801 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { 3802 u_int work = 0; 3803 if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { 3804 more = 0; 3805 goto skip_rxeof; 3806 } 3807 } 3808 #endif 3809 budget = ctx->ifc_sysctl_rx_budget; 3810 if (budget == 0) 3811 budget = 16; /* XXX */ 3812 more = iflib_rxeof(rxq, budget); 3813 #ifdef DEV_NETMAP 3814 skip_rxeof: 3815 #endif 3816 if ((more & IFLIB_RXEOF_MORE) == 0) { 3817 if (ctx->ifc_flags & IFC_LEGACY) 3818 IFDI_INTR_ENABLE(ctx); 3819 else 3820 IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); 3821 DBG_COUNTER_INC(rx_intr_enables); 3822 } 3823 if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) 3824 return; 3825 3826 if (more & IFLIB_RXEOF_MORE) 3827 GROUPTASK_ENQUEUE(&rxq->ifr_task); 3828 else if (more & IFLIB_RXEOF_EMPTY) 3829 callout_reset_curcpu(&rxq->ifr_watchdog, 1, &_task_fn_rx_watchdog, rxq); 3830 } 3831 3832 static void 3833 _task_fn_admin(void *context) 3834 { 3835 if_ctx_t ctx = context; 3836 if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; 3837 iflib_txq_t txq; 3838 int i; 3839 bool oactive, running, do_reset, do_watchdog, in_detach; 3840 uint32_t reset_on = hz / 2; 3841 3842 STATE_LOCK(ctx); 3843 running = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING); 3844 oactive = (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE); 3845 do_reset = (ctx->ifc_flags & IFC_DO_RESET); 3846 do_watchdog = (ctx->ifc_flags & IFC_DO_WATCHDOG); 3847 in_detach = (ctx->ifc_flags & IFC_IN_DETACH); 3848 ctx->ifc_flags &= ~(IFC_DO_RESET|IFC_DO_WATCHDOG); 3849 STATE_UNLOCK(ctx); 3850 3851 if ((!running && !oactive) && !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3852 return; 3853 if (in_detach) 3854 return; 3855 3856 CTX_LOCK(ctx); 3857 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3858 CALLOUT_LOCK(txq); 3859 callout_stop(&txq->ift_timer); 3860 CALLOUT_UNLOCK(txq); 3861 } 3862 if (do_watchdog) { 3863 ctx->ifc_watchdog_events++; 3864 IFDI_WATCHDOG_RESET(ctx); 3865 } 3866 IFDI_UPDATE_ADMIN_STATUS(ctx); 3867 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { 3868 #ifdef DEV_NETMAP 3869 reset_on = hz / 2; 3870 if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) 3871 iflib_netmap_timer_adjust(ctx, txq, &reset_on); 3872 #endif 3873 callout_reset_on(&txq->ift_timer, reset_on, iflib_timer, txq, txq->ift_timer.c_cpu); 3874 } 3875 IFDI_LINK_INTR_ENABLE(ctx); 3876 if (do_reset) 3877 iflib_if_init_locked(ctx); 3878 CTX_UNLOCK(ctx); 3879 3880 if (LINK_ACTIVE(ctx) == 0) 3881 return; 3882 for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) 3883 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 3884 } 3885 3886 3887 static void 3888 _task_fn_iov(void *context) 3889 { 3890 if_ctx_t ctx = context; 3891 3892 if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) && 3893 !(ctx->ifc_sctx->isc_flags & IFLIB_ADMIN_ALWAYS_RUN)) 3894 return; 3895 3896 CTX_LOCK(ctx); 3897 IFDI_VFLR_HANDLE(ctx); 3898 CTX_UNLOCK(ctx); 3899 } 3900 3901 static int 3902 iflib_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 3903 { 3904 int err; 3905 if_int_delay_info_t info; 3906 if_ctx_t ctx; 3907 3908 info = (if_int_delay_info_t)arg1; 3909 ctx = info->iidi_ctx; 3910 info->iidi_req = req; 3911 info->iidi_oidp = oidp; 3912 CTX_LOCK(ctx); 3913 err = IFDI_SYSCTL_INT_DELAY(ctx, info); 3914 CTX_UNLOCK(ctx); 3915 return (err); 3916 } 3917 3918 /********************************************************************* 3919 * 3920 * IFNET FUNCTIONS 3921 * 3922 **********************************************************************/ 3923 3924 static void 3925 iflib_if_init_locked(if_ctx_t ctx) 3926 { 3927 iflib_stop(ctx); 3928 iflib_init_locked(ctx); 3929 } 3930 3931 3932 static void 3933 iflib_if_init(void *arg) 3934 { 3935 if_ctx_t ctx = arg; 3936 3937 CTX_LOCK(ctx); 3938 iflib_if_init_locked(ctx); 3939 CTX_UNLOCK(ctx); 3940 } 3941 3942 static int 3943 iflib_if_transmit(if_t ifp, struct mbuf *m) 3944 { 3945 if_ctx_t ctx = if_getsoftc(ifp); 3946 3947 iflib_txq_t txq; 3948 int err, qidx; 3949 int abdicate = ctx->ifc_sysctl_tx_abdicate; 3950 3951 if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { 3952 DBG_COUNTER_INC(tx_frees); 3953 m_freem(m); 3954 return (ENETDOWN); 3955 } 3956 3957 MPASS(m->m_nextpkt == NULL); 3958 /* ALTQ-enabled interfaces always use queue 0. */ 3959 qidx = 0; 3960 if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m) && !ALTQ_IS_ENABLED(&ifp->if_snd)) 3961 qidx = QIDX(ctx, m); 3962 /* 3963 * XXX calculate buf_ring based on flowid (divvy up bits?) 3964 */ 3965 txq = &ctx->ifc_txqs[qidx]; 3966 3967 #ifdef DRIVER_BACKPRESSURE 3968 if (txq->ift_closed) { 3969 while (m != NULL) { 3970 next = m->m_nextpkt; 3971 m->m_nextpkt = NULL; 3972 m_freem(m); 3973 DBG_COUNTER_INC(tx_frees); 3974 m = next; 3975 } 3976 return (ENOBUFS); 3977 } 3978 #endif 3979 #ifdef notyet 3980 qidx = count = 0; 3981 mp = marr; 3982 next = m; 3983 do { 3984 count++; 3985 next = next->m_nextpkt; 3986 } while (next != NULL); 3987 3988 if (count > nitems(marr)) 3989 if ((mp = malloc(count*sizeof(struct mbuf *), M_IFLIB, M_NOWAIT)) == NULL) { 3990 /* XXX check nextpkt */ 3991 m_freem(m); 3992 /* XXX simplify for now */ 3993 DBG_COUNTER_INC(tx_frees); 3994 return (ENOBUFS); 3995 } 3996 for (next = m, i = 0; next != NULL; i++) { 3997 mp[i] = next; 3998 next = next->m_nextpkt; 3999 mp[i]->m_nextpkt = NULL; 4000 } 4001 #endif 4002 DBG_COUNTER_INC(tx_seen); 4003 err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE, abdicate); 4004 4005 if (abdicate) 4006 GROUPTASK_ENQUEUE(&txq->ift_task); 4007 if (err) { 4008 if (!abdicate) 4009 GROUPTASK_ENQUEUE(&txq->ift_task); 4010 /* support forthcoming later */ 4011 #ifdef DRIVER_BACKPRESSURE 4012 txq->ift_closed = TRUE; 4013 #endif 4014 ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); 4015 m_freem(m); 4016 DBG_COUNTER_INC(tx_frees); 4017 } 4018 4019 return (err); 4020 } 4021 4022 #ifdef ALTQ 4023 /* 4024 * The overall approach to integrating iflib with ALTQ is to continue to use 4025 * the iflib mp_ring machinery between the ALTQ queue(s) and the hardware 4026 * ring. Technically, when using ALTQ, queueing to an intermediate mp_ring 4027 * is redundant/unnecessary, but doing so minimizes the amount of 4028 * ALTQ-specific code required in iflib. It is assumed that the overhead of 4029 * redundantly queueing to an intermediate mp_ring is swamped by the 4030 * performance limitations inherent in using ALTQ. 4031 * 4032 * When ALTQ support is compiled in, all iflib drivers will use a transmit 4033 * routine, iflib_altq_if_transmit(), that checks if ALTQ is enabled for the 4034 * given interface. If ALTQ is enabled for an interface, then all 4035 * transmitted packets for that interface will be submitted to the ALTQ 4036 * subsystem via IFQ_ENQUEUE(). We don't use the legacy if_transmit() 4037 * implementation because it uses IFQ_HANDOFF(), which will duplicatively 4038 * update stats that the iflib machinery handles, and which is sensitve to 4039 * the disused IFF_DRV_OACTIVE flag. Additionally, iflib_altq_if_start() 4040 * will be installed as the start routine for use by ALTQ facilities that 4041 * need to trigger queue drains on a scheduled basis. 4042 * 4043 */ 4044 static void 4045 iflib_altq_if_start(if_t ifp) 4046 { 4047 struct ifaltq *ifq = &ifp->if_snd; 4048 struct mbuf *m; 4049 4050 IFQ_LOCK(ifq); 4051 IFQ_DEQUEUE_NOLOCK(ifq, m); 4052 while (m != NULL) { 4053 iflib_if_transmit(ifp, m); 4054 IFQ_DEQUEUE_NOLOCK(ifq, m); 4055 } 4056 IFQ_UNLOCK(ifq); 4057 } 4058 4059 static int 4060 iflib_altq_if_transmit(if_t ifp, struct mbuf *m) 4061 { 4062 int err; 4063 4064 if (ALTQ_IS_ENABLED(&ifp->if_snd)) { 4065 IFQ_ENQUEUE(&ifp->if_snd, m, err); 4066 if (err == 0) 4067 iflib_altq_if_start(ifp); 4068 } else 4069 err = iflib_if_transmit(ifp, m); 4070 4071 return (err); 4072 } 4073 #endif /* ALTQ */ 4074 4075 static void 4076 iflib_if_qflush(if_t ifp) 4077 { 4078 if_ctx_t ctx = if_getsoftc(ifp); 4079 iflib_txq_t txq = ctx->ifc_txqs; 4080 int i; 4081 4082 STATE_LOCK(ctx); 4083 ctx->ifc_flags |= IFC_QFLUSH; 4084 STATE_UNLOCK(ctx); 4085 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 4086 while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) 4087 iflib_txq_check_drain(txq, 0); 4088 STATE_LOCK(ctx); 4089 ctx->ifc_flags &= ~IFC_QFLUSH; 4090 STATE_UNLOCK(ctx); 4091 4092 /* 4093 * When ALTQ is enabled, this will also take care of purging the 4094 * ALTQ queue(s). 4095 */ 4096 if_qflush(ifp); 4097 } 4098 4099 4100 #define IFCAP_FLAGS (IFCAP_HWCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ 4101 IFCAP_TSO | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ 4102 IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | \ 4103 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM | IFCAP_NOMAP) 4104 4105 static int 4106 iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) 4107 { 4108 if_ctx_t ctx = if_getsoftc(ifp); 4109 struct ifreq *ifr = (struct ifreq *)data; 4110 #if defined(INET) || defined(INET6) 4111 struct ifaddr *ifa = (struct ifaddr *)data; 4112 #endif 4113 bool avoid_reset = false; 4114 int err = 0, reinit = 0, bits; 4115 4116 switch (command) { 4117 case SIOCSIFADDR: 4118 #ifdef INET 4119 if (ifa->ifa_addr->sa_family == AF_INET) 4120 avoid_reset = true; 4121 #endif 4122 #ifdef INET6 4123 if (ifa->ifa_addr->sa_family == AF_INET6) 4124 avoid_reset = true; 4125 #endif 4126 /* 4127 ** Calling init results in link renegotiation, 4128 ** so we avoid doing it when possible. 4129 */ 4130 if (avoid_reset) { 4131 if_setflagbits(ifp, IFF_UP,0); 4132 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 4133 reinit = 1; 4134 #ifdef INET 4135 if (!(if_getflags(ifp) & IFF_NOARP)) 4136 arp_ifinit(ifp, ifa); 4137 #endif 4138 } else 4139 err = ether_ioctl(ifp, command, data); 4140 break; 4141 case SIOCSIFMTU: 4142 CTX_LOCK(ctx); 4143 if (ifr->ifr_mtu == if_getmtu(ifp)) { 4144 CTX_UNLOCK(ctx); 4145 break; 4146 } 4147 bits = if_getdrvflags(ifp); 4148 /* stop the driver and free any clusters before proceeding */ 4149 iflib_stop(ctx); 4150 4151 if ((err = IFDI_MTU_SET(ctx, ifr->ifr_mtu)) == 0) { 4152 STATE_LOCK(ctx); 4153 if (ifr->ifr_mtu > ctx->ifc_max_fl_buf_size) 4154 ctx->ifc_flags |= IFC_MULTISEG; 4155 else 4156 ctx->ifc_flags &= ~IFC_MULTISEG; 4157 STATE_UNLOCK(ctx); 4158 err = if_setmtu(ifp, ifr->ifr_mtu); 4159 } 4160 iflib_init_locked(ctx); 4161 STATE_LOCK(ctx); 4162 if_setdrvflags(ifp, bits); 4163 STATE_UNLOCK(ctx); 4164 CTX_UNLOCK(ctx); 4165 break; 4166 case SIOCSIFFLAGS: 4167 CTX_LOCK(ctx); 4168 if (if_getflags(ifp) & IFF_UP) { 4169 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4170 if ((if_getflags(ifp) ^ ctx->ifc_if_flags) & 4171 (IFF_PROMISC | IFF_ALLMULTI)) { 4172 err = IFDI_PROMISC_SET(ctx, if_getflags(ifp)); 4173 } 4174 } else 4175 reinit = 1; 4176 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4177 iflib_stop(ctx); 4178 } 4179 ctx->ifc_if_flags = if_getflags(ifp); 4180 CTX_UNLOCK(ctx); 4181 break; 4182 case SIOCADDMULTI: 4183 case SIOCDELMULTI: 4184 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4185 CTX_LOCK(ctx); 4186 IFDI_INTR_DISABLE(ctx); 4187 IFDI_MULTI_SET(ctx); 4188 IFDI_INTR_ENABLE(ctx); 4189 CTX_UNLOCK(ctx); 4190 } 4191 break; 4192 case SIOCSIFMEDIA: 4193 CTX_LOCK(ctx); 4194 IFDI_MEDIA_SET(ctx); 4195 CTX_UNLOCK(ctx); 4196 /* FALLTHROUGH */ 4197 case SIOCGIFMEDIA: 4198 case SIOCGIFXMEDIA: 4199 err = ifmedia_ioctl(ifp, ifr, ctx->ifc_mediap, command); 4200 break; 4201 case SIOCGI2C: 4202 { 4203 struct ifi2creq i2c; 4204 4205 err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 4206 if (err != 0) 4207 break; 4208 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 4209 err = EINVAL; 4210 break; 4211 } 4212 if (i2c.len > sizeof(i2c.data)) { 4213 err = EINVAL; 4214 break; 4215 } 4216 4217 if ((err = IFDI_I2C_REQ(ctx, &i2c)) == 0) 4218 err = copyout(&i2c, ifr_data_get_ptr(ifr), 4219 sizeof(i2c)); 4220 break; 4221 } 4222 case SIOCSIFCAP: 4223 { 4224 int mask, setmask, oldmask; 4225 4226 oldmask = if_getcapenable(ifp); 4227 mask = ifr->ifr_reqcap ^ oldmask; 4228 mask &= ctx->ifc_softc_ctx.isc_capabilities | IFCAP_NOMAP; 4229 setmask = 0; 4230 #ifdef TCP_OFFLOAD 4231 setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); 4232 #endif 4233 setmask |= (mask & IFCAP_FLAGS); 4234 setmask |= (mask & IFCAP_WOL); 4235 4236 /* 4237 * If any RX csum has changed, change all the ones that 4238 * are supported by the driver. 4239 */ 4240 if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) { 4241 setmask |= ctx->ifc_softc_ctx.isc_capabilities & 4242 (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); 4243 } 4244 4245 /* 4246 * want to ensure that traffic has stopped before we change any of the flags 4247 */ 4248 if (setmask) { 4249 CTX_LOCK(ctx); 4250 bits = if_getdrvflags(ifp); 4251 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4252 iflib_stop(ctx); 4253 STATE_LOCK(ctx); 4254 if_togglecapenable(ifp, setmask); 4255 STATE_UNLOCK(ctx); 4256 if (bits & IFF_DRV_RUNNING && setmask & ~IFCAP_WOL) 4257 iflib_init_locked(ctx); 4258 STATE_LOCK(ctx); 4259 if_setdrvflags(ifp, bits); 4260 STATE_UNLOCK(ctx); 4261 CTX_UNLOCK(ctx); 4262 } 4263 if_vlancap(ifp); 4264 break; 4265 } 4266 case SIOCGPRIVATE_0: 4267 case SIOCSDRVSPEC: 4268 case SIOCGDRVSPEC: 4269 CTX_LOCK(ctx); 4270 err = IFDI_PRIV_IOCTL(ctx, command, data); 4271 CTX_UNLOCK(ctx); 4272 break; 4273 default: 4274 err = ether_ioctl(ifp, command, data); 4275 break; 4276 } 4277 if (reinit) 4278 iflib_if_init(ctx); 4279 return (err); 4280 } 4281 4282 static uint64_t 4283 iflib_if_get_counter(if_t ifp, ift_counter cnt) 4284 { 4285 if_ctx_t ctx = if_getsoftc(ifp); 4286 4287 return (IFDI_GET_COUNTER(ctx, cnt)); 4288 } 4289 4290 /********************************************************************* 4291 * 4292 * OTHER FUNCTIONS EXPORTED TO THE STACK 4293 * 4294 **********************************************************************/ 4295 4296 static void 4297 iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) 4298 { 4299 if_ctx_t ctx = if_getsoftc(ifp); 4300 4301 if ((void *)ctx != arg) 4302 return; 4303 4304 if ((vtag == 0) || (vtag > 4095)) 4305 return; 4306 4307 if (iflib_in_detach(ctx)) 4308 return; 4309 4310 CTX_LOCK(ctx); 4311 /* Driver may need all untagged packets to be flushed */ 4312 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4313 iflib_stop(ctx); 4314 IFDI_VLAN_REGISTER(ctx, vtag); 4315 /* Re-init to load the changes, if required */ 4316 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4317 iflib_init_locked(ctx); 4318 CTX_UNLOCK(ctx); 4319 } 4320 4321 static void 4322 iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) 4323 { 4324 if_ctx_t ctx = if_getsoftc(ifp); 4325 4326 if ((void *)ctx != arg) 4327 return; 4328 4329 if ((vtag == 0) || (vtag > 4095)) 4330 return; 4331 4332 CTX_LOCK(ctx); 4333 /* Driver may need all tagged packets to be flushed */ 4334 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4335 iflib_stop(ctx); 4336 IFDI_VLAN_UNREGISTER(ctx, vtag); 4337 /* Re-init to load the changes, if required */ 4338 if (IFDI_NEEDS_RESTART(ctx, IFLIB_RESTART_VLAN_CONFIG)) 4339 iflib_init_locked(ctx); 4340 CTX_UNLOCK(ctx); 4341 } 4342 4343 static void 4344 iflib_led_func(void *arg, int onoff) 4345 { 4346 if_ctx_t ctx = arg; 4347 4348 CTX_LOCK(ctx); 4349 IFDI_LED_FUNC(ctx, onoff); 4350 CTX_UNLOCK(ctx); 4351 } 4352 4353 /********************************************************************* 4354 * 4355 * BUS FUNCTION DEFINITIONS 4356 * 4357 **********************************************************************/ 4358 4359 int 4360 iflib_device_probe(device_t dev) 4361 { 4362 const pci_vendor_info_t *ent; 4363 if_shared_ctx_t sctx; 4364 uint16_t pci_device_id, pci_rev_id, pci_subdevice_id, pci_subvendor_id; 4365 uint16_t pci_vendor_id; 4366 4367 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 4368 return (ENOTSUP); 4369 4370 pci_vendor_id = pci_get_vendor(dev); 4371 pci_device_id = pci_get_device(dev); 4372 pci_subvendor_id = pci_get_subvendor(dev); 4373 pci_subdevice_id = pci_get_subdevice(dev); 4374 pci_rev_id = pci_get_revid(dev); 4375 if (sctx->isc_parse_devinfo != NULL) 4376 sctx->isc_parse_devinfo(&pci_device_id, &pci_subvendor_id, &pci_subdevice_id, &pci_rev_id); 4377 4378 ent = sctx->isc_vendor_info; 4379 while (ent->pvi_vendor_id != 0) { 4380 if (pci_vendor_id != ent->pvi_vendor_id) { 4381 ent++; 4382 continue; 4383 } 4384 if ((pci_device_id == ent->pvi_device_id) && 4385 ((pci_subvendor_id == ent->pvi_subvendor_id) || 4386 (ent->pvi_subvendor_id == 0)) && 4387 ((pci_subdevice_id == ent->pvi_subdevice_id) || 4388 (ent->pvi_subdevice_id == 0)) && 4389 ((pci_rev_id == ent->pvi_rev_id) || 4390 (ent->pvi_rev_id == 0))) { 4391 4392 device_set_desc_copy(dev, ent->pvi_name); 4393 /* this needs to be changed to zero if the bus probing code 4394 * ever stops re-probing on best match because the sctx 4395 * may have its values over written by register calls 4396 * in subsequent probes 4397 */ 4398 return (BUS_PROBE_DEFAULT); 4399 } 4400 ent++; 4401 } 4402 return (ENXIO); 4403 } 4404 4405 int 4406 iflib_device_probe_vendor(device_t dev) 4407 { 4408 int probe; 4409 4410 probe = iflib_device_probe(dev); 4411 if (probe == BUS_PROBE_DEFAULT) 4412 return (BUS_PROBE_VENDOR); 4413 else 4414 return (probe); 4415 } 4416 4417 static void 4418 iflib_reset_qvalues(if_ctx_t ctx) 4419 { 4420 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4421 if_shared_ctx_t sctx = ctx->ifc_sctx; 4422 device_t dev = ctx->ifc_dev; 4423 int i; 4424 4425 if (ctx->ifc_sysctl_ntxqs != 0) 4426 scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; 4427 if (ctx->ifc_sysctl_nrxqs != 0) 4428 scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; 4429 4430 for (i = 0; i < sctx->isc_ntxqs; i++) { 4431 if (ctx->ifc_sysctl_ntxds[i] != 0) 4432 scctx->isc_ntxd[i] = ctx->ifc_sysctl_ntxds[i]; 4433 else 4434 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4435 } 4436 4437 for (i = 0; i < sctx->isc_nrxqs; i++) { 4438 if (ctx->ifc_sysctl_nrxds[i] != 0) 4439 scctx->isc_nrxd[i] = ctx->ifc_sysctl_nrxds[i]; 4440 else 4441 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4442 } 4443 4444 for (i = 0; i < sctx->isc_nrxqs; i++) { 4445 if (scctx->isc_nrxd[i] < sctx->isc_nrxd_min[i]) { 4446 device_printf(dev, "nrxd%d: %d less than nrxd_min %d - resetting to min\n", 4447 i, scctx->isc_nrxd[i], sctx->isc_nrxd_min[i]); 4448 scctx->isc_nrxd[i] = sctx->isc_nrxd_min[i]; 4449 } 4450 if (scctx->isc_nrxd[i] > sctx->isc_nrxd_max[i]) { 4451 device_printf(dev, "nrxd%d: %d greater than nrxd_max %d - resetting to max\n", 4452 i, scctx->isc_nrxd[i], sctx->isc_nrxd_max[i]); 4453 scctx->isc_nrxd[i] = sctx->isc_nrxd_max[i]; 4454 } 4455 if (!powerof2(scctx->isc_nrxd[i])) { 4456 device_printf(dev, "nrxd%d: %d is not a power of 2 - using default value of %d\n", 4457 i, scctx->isc_nrxd[i], sctx->isc_nrxd_default[i]); 4458 scctx->isc_nrxd[i] = sctx->isc_nrxd_default[i]; 4459 } 4460 } 4461 4462 for (i = 0; i < sctx->isc_ntxqs; i++) { 4463 if (scctx->isc_ntxd[i] < sctx->isc_ntxd_min[i]) { 4464 device_printf(dev, "ntxd%d: %d less than ntxd_min %d - resetting to min\n", 4465 i, scctx->isc_ntxd[i], sctx->isc_ntxd_min[i]); 4466 scctx->isc_ntxd[i] = sctx->isc_ntxd_min[i]; 4467 } 4468 if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { 4469 device_printf(dev, "ntxd%d: %d greater than ntxd_max %d - resetting to max\n", 4470 i, scctx->isc_ntxd[i], sctx->isc_ntxd_max[i]); 4471 scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; 4472 } 4473 if (!powerof2(scctx->isc_ntxd[i])) { 4474 device_printf(dev, "ntxd%d: %d is not a power of 2 - using default value of %d\n", 4475 i, scctx->isc_ntxd[i], sctx->isc_ntxd_default[i]); 4476 scctx->isc_ntxd[i] = sctx->isc_ntxd_default[i]; 4477 } 4478 } 4479 } 4480 4481 static void 4482 iflib_add_pfil(if_ctx_t ctx) 4483 { 4484 struct pfil_head *pfil; 4485 struct pfil_head_args pa; 4486 iflib_rxq_t rxq; 4487 int i; 4488 4489 pa.pa_version = PFIL_VERSION; 4490 pa.pa_flags = PFIL_IN; 4491 pa.pa_type = PFIL_TYPE_ETHERNET; 4492 pa.pa_headname = ctx->ifc_ifp->if_xname; 4493 pfil = pfil_head_register(&pa); 4494 4495 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 4496 rxq->pfil = pfil; 4497 } 4498 } 4499 4500 static void 4501 iflib_rem_pfil(if_ctx_t ctx) 4502 { 4503 struct pfil_head *pfil; 4504 iflib_rxq_t rxq; 4505 int i; 4506 4507 rxq = ctx->ifc_rxqs; 4508 pfil = rxq->pfil; 4509 for (i = 0; i < NRXQSETS(ctx); i++, rxq++) { 4510 rxq->pfil = NULL; 4511 } 4512 pfil_head_unregister(pfil); 4513 } 4514 4515 static uint16_t 4516 get_ctx_core_offset(if_ctx_t ctx) 4517 { 4518 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 4519 struct cpu_offset *op; 4520 uint16_t qc; 4521 uint16_t ret = ctx->ifc_sysctl_core_offset; 4522 4523 if (ret != CORE_OFFSET_UNSPECIFIED) 4524 return (ret); 4525 4526 if (ctx->ifc_sysctl_separate_txrx) 4527 qc = scctx->isc_ntxqsets + scctx->isc_nrxqsets; 4528 else 4529 qc = max(scctx->isc_ntxqsets, scctx->isc_nrxqsets); 4530 4531 mtx_lock(&cpu_offset_mtx); 4532 SLIST_FOREACH(op, &cpu_offsets, entries) { 4533 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4534 ret = op->offset; 4535 op->offset += qc; 4536 MPASS(op->refcount < UINT_MAX); 4537 op->refcount++; 4538 break; 4539 } 4540 } 4541 if (ret == CORE_OFFSET_UNSPECIFIED) { 4542 ret = 0; 4543 op = malloc(sizeof(struct cpu_offset), M_IFLIB, 4544 M_NOWAIT | M_ZERO); 4545 if (op == NULL) { 4546 device_printf(ctx->ifc_dev, 4547 "allocation for cpu offset failed.\n"); 4548 } else { 4549 op->offset = qc; 4550 op->refcount = 1; 4551 CPU_COPY(&ctx->ifc_cpus, &op->set); 4552 SLIST_INSERT_HEAD(&cpu_offsets, op, entries); 4553 } 4554 } 4555 mtx_unlock(&cpu_offset_mtx); 4556 4557 return (ret); 4558 } 4559 4560 static void 4561 unref_ctx_core_offset(if_ctx_t ctx) 4562 { 4563 struct cpu_offset *op, *top; 4564 4565 mtx_lock(&cpu_offset_mtx); 4566 SLIST_FOREACH_SAFE(op, &cpu_offsets, entries, top) { 4567 if (CPU_CMP(&ctx->ifc_cpus, &op->set) == 0) { 4568 MPASS(op->refcount > 0); 4569 op->refcount--; 4570 if (op->refcount == 0) { 4571 SLIST_REMOVE(&cpu_offsets, op, cpu_offset, entries); 4572 free(op, M_IFLIB); 4573 } 4574 break; 4575 } 4576 } 4577 mtx_unlock(&cpu_offset_mtx); 4578 } 4579 4580 int 4581 iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) 4582 { 4583 if_ctx_t ctx; 4584 if_t ifp; 4585 if_softc_ctx_t scctx; 4586 kobjop_desc_t kobj_desc; 4587 kobj_method_t *kobj_method; 4588 int err, msix, rid; 4589 uint16_t main_rxq, main_txq; 4590 4591 ctx = malloc(sizeof(* ctx), M_IFLIB, M_WAITOK|M_ZERO); 4592 4593 if (sc == NULL) { 4594 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4595 device_set_softc(dev, ctx); 4596 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4597 } 4598 4599 ctx->ifc_sctx = sctx; 4600 ctx->ifc_dev = dev; 4601 ctx->ifc_softc = sc; 4602 4603 if ((err = iflib_register(ctx)) != 0) { 4604 device_printf(dev, "iflib_register failed %d\n", err); 4605 goto fail_ctx_free; 4606 } 4607 iflib_add_device_sysctl_pre(ctx); 4608 4609 scctx = &ctx->ifc_softc_ctx; 4610 ifp = ctx->ifc_ifp; 4611 4612 iflib_reset_qvalues(ctx); 4613 CTX_LOCK(ctx); 4614 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4615 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4616 goto fail_unlock; 4617 } 4618 _iflib_pre_assert(scctx); 4619 ctx->ifc_txrx = *scctx->isc_txrx; 4620 4621 if (sctx->isc_flags & IFLIB_DRIVER_MEDIA) 4622 ctx->ifc_mediap = scctx->isc_media; 4623 4624 #ifdef INVARIANTS 4625 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4626 MPASS(scctx->isc_tx_csum_flags); 4627 #endif 4628 4629 if_setcapabilities(ifp, 4630 scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_NOMAP); 4631 if_setcapenable(ifp, 4632 scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_NOMAP); 4633 4634 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4635 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4636 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4637 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4638 4639 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4640 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4641 4642 /* XXX change for per-queue sizes */ 4643 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4644 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4645 4646 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4647 MAX_SINGLE_PACKET_FRACTION) 4648 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4649 MAX_SINGLE_PACKET_FRACTION); 4650 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4651 MAX_SINGLE_PACKET_FRACTION) 4652 scctx->isc_tx_tso_segments_max = max(1, 4653 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4654 4655 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4656 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4657 /* 4658 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4659 * but some MACs do. 4660 */ 4661 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4662 IP_MAXPACKET)); 4663 /* 4664 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4665 * into account. In the worst case, each of these calls will 4666 * add another mbuf and, thus, the requirement for another DMA 4667 * segment. So for best performance, it doesn't make sense to 4668 * advertize a maximum of TSO segments that typically will 4669 * require defragmentation in iflib_encap(). 4670 */ 4671 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4672 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4673 } 4674 if (scctx->isc_rss_table_size == 0) 4675 scctx->isc_rss_table_size = 64; 4676 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4677 4678 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4679 /* XXX format name */ 4680 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4681 NULL, NULL, "admin"); 4682 4683 /* Set up cpu set. If it fails, use the set of all CPUs. */ 4684 if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { 4685 device_printf(dev, "Unable to fetch CPU list\n"); 4686 CPU_COPY(&all_cpus, &ctx->ifc_cpus); 4687 } 4688 MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); 4689 4690 /* 4691 ** Now set up MSI or MSI-X, should return us the number of supported 4692 ** vectors (will be 1 for a legacy interrupt and MSI). 4693 */ 4694 if (sctx->isc_flags & IFLIB_SKIP_MSIX) { 4695 msix = scctx->isc_vectors; 4696 } else if (scctx->isc_msix_bar != 0) 4697 /* 4698 * The simple fact that isc_msix_bar is not 0 does not mean we 4699 * we have a good value there that is known to work. 4700 */ 4701 msix = iflib_msix_init(ctx); 4702 else { 4703 scctx->isc_vectors = 1; 4704 scctx->isc_ntxqsets = 1; 4705 scctx->isc_nrxqsets = 1; 4706 scctx->isc_intr = IFLIB_INTR_LEGACY; 4707 msix = 0; 4708 } 4709 /* Get memory for the station queues */ 4710 if ((err = iflib_queues_alloc(ctx))) { 4711 device_printf(dev, "Unable to allocate queue memory\n"); 4712 goto fail_intr_free; 4713 } 4714 4715 if ((err = iflib_qset_structures_setup(ctx))) 4716 goto fail_queues; 4717 4718 /* 4719 * Now that we know how many queues there are, get the core offset. 4720 */ 4721 ctx->ifc_sysctl_core_offset = get_ctx_core_offset(ctx); 4722 4723 if (msix > 1) { 4724 /* 4725 * When using MSI-X, ensure that ifdi_{r,t}x_queue_intr_enable 4726 * aren't the default NULL implementation. 4727 */ 4728 kobj_desc = &ifdi_rx_queue_intr_enable_desc; 4729 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4730 kobj_desc); 4731 if (kobj_method == &kobj_desc->deflt) { 4732 device_printf(dev, 4733 "MSI-X requires ifdi_rx_queue_intr_enable method"); 4734 err = EOPNOTSUPP; 4735 goto fail_queues; 4736 } 4737 kobj_desc = &ifdi_tx_queue_intr_enable_desc; 4738 kobj_method = kobj_lookup_method(((kobj_t)ctx)->ops->cls, NULL, 4739 kobj_desc); 4740 if (kobj_method == &kobj_desc->deflt) { 4741 device_printf(dev, 4742 "MSI-X requires ifdi_tx_queue_intr_enable method"); 4743 err = EOPNOTSUPP; 4744 goto fail_queues; 4745 } 4746 4747 /* 4748 * Assign the MSI-X vectors. 4749 * Note that the default NULL ifdi_msix_intr_assign method will 4750 * fail here, too. 4751 */ 4752 err = IFDI_MSIX_INTR_ASSIGN(ctx, msix); 4753 if (err != 0) { 4754 device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", 4755 err); 4756 goto fail_queues; 4757 } 4758 } else if (scctx->isc_intr != IFLIB_INTR_MSIX) { 4759 rid = 0; 4760 if (scctx->isc_intr == IFLIB_INTR_MSI) { 4761 MPASS(msix == 1); 4762 rid = 1; 4763 } 4764 if ((err = iflib_legacy_setup(ctx, ctx->isc_legacy_intr, ctx->ifc_softc, &rid, "irq0")) != 0) { 4765 device_printf(dev, "iflib_legacy_setup failed %d\n", err); 4766 goto fail_queues; 4767 } 4768 } else { 4769 device_printf(dev, 4770 "Cannot use iflib with only 1 MSI-X interrupt!\n"); 4771 err = ENODEV; 4772 goto fail_intr_free; 4773 } 4774 4775 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4776 4777 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4778 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4779 goto fail_detach; 4780 } 4781 4782 /* 4783 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4784 * This must appear after the call to ether_ifattach() because 4785 * ether_ifattach() sets if_hdrlen to the default value. 4786 */ 4787 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4788 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4789 4790 if ((err = iflib_netmap_attach(ctx))) { 4791 device_printf(ctx->ifc_dev, "netmap attach failed: %d\n", err); 4792 goto fail_detach; 4793 } 4794 *ctxp = ctx; 4795 4796 DEBUGNET_SET(ctx->ifc_ifp, iflib); 4797 4798 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4799 iflib_add_device_sysctl_post(ctx); 4800 iflib_add_pfil(ctx); 4801 ctx->ifc_flags |= IFC_INIT_DONE; 4802 CTX_UNLOCK(ctx); 4803 4804 return (0); 4805 4806 fail_detach: 4807 ether_ifdetach(ctx->ifc_ifp); 4808 fail_intr_free: 4809 iflib_free_intr_mem(ctx); 4810 fail_queues: 4811 iflib_tx_structures_free(ctx); 4812 iflib_rx_structures_free(ctx); 4813 taskqgroup_detach(qgroup_if_config_tqg, &ctx->ifc_admin_task); 4814 IFDI_DETACH(ctx); 4815 fail_unlock: 4816 CTX_UNLOCK(ctx); 4817 iflib_deregister(ctx); 4818 fail_ctx_free: 4819 device_set_softc(ctx->ifc_dev, NULL); 4820 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 4821 free(ctx->ifc_softc, M_IFLIB); 4822 free(ctx, M_IFLIB); 4823 return (err); 4824 } 4825 4826 int 4827 iflib_pseudo_register(device_t dev, if_shared_ctx_t sctx, if_ctx_t *ctxp, 4828 struct iflib_cloneattach_ctx *clctx) 4829 { 4830 int err; 4831 if_ctx_t ctx; 4832 if_t ifp; 4833 if_softc_ctx_t scctx; 4834 int i; 4835 void *sc; 4836 uint16_t main_txq; 4837 uint16_t main_rxq; 4838 4839 ctx = malloc(sizeof(*ctx), M_IFLIB, M_WAITOK|M_ZERO); 4840 sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); 4841 ctx->ifc_flags |= IFC_SC_ALLOCATED; 4842 if (sctx->isc_flags & (IFLIB_PSEUDO|IFLIB_VIRTUAL)) 4843 ctx->ifc_flags |= IFC_PSEUDO; 4844 4845 ctx->ifc_sctx = sctx; 4846 ctx->ifc_softc = sc; 4847 ctx->ifc_dev = dev; 4848 4849 if ((err = iflib_register(ctx)) != 0) { 4850 device_printf(dev, "%s: iflib_register failed %d\n", __func__, err); 4851 goto fail_ctx_free; 4852 } 4853 iflib_add_device_sysctl_pre(ctx); 4854 4855 scctx = &ctx->ifc_softc_ctx; 4856 ifp = ctx->ifc_ifp; 4857 4858 iflib_reset_qvalues(ctx); 4859 CTX_LOCK(ctx); 4860 if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { 4861 device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); 4862 goto fail_unlock; 4863 } 4864 if (sctx->isc_flags & IFLIB_GEN_MAC) 4865 ether_gen_addr(ifp, &ctx->ifc_mac); 4866 if ((err = IFDI_CLONEATTACH(ctx, clctx->cc_ifc, clctx->cc_name, 4867 clctx->cc_params)) != 0) { 4868 device_printf(dev, "IFDI_CLONEATTACH failed %d\n", err); 4869 goto fail_ctx_free; 4870 } 4871 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 4872 ifmedia_add(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO, 0, NULL); 4873 ifmedia_set(ctx->ifc_mediap, IFM_ETHER | IFM_AUTO); 4874 4875 #ifdef INVARIANTS 4876 if (scctx->isc_capabilities & IFCAP_TXCSUM) 4877 MPASS(scctx->isc_tx_csum_flags); 4878 #endif 4879 4880 if_setcapabilities(ifp, scctx->isc_capabilities | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4881 if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS | IFCAP_LINKSTATE); 4882 4883 ifp->if_flags |= IFF_NOGROUP; 4884 if (sctx->isc_flags & IFLIB_PSEUDO) { 4885 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4886 4887 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4888 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4889 goto fail_detach; 4890 } 4891 *ctxp = ctx; 4892 4893 /* 4894 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4895 * This must appear after the call to ether_ifattach() because 4896 * ether_ifattach() sets if_hdrlen to the default value. 4897 */ 4898 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4899 if_setifheaderlen(ifp, 4900 sizeof(struct ether_vlan_header)); 4901 4902 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4903 iflib_add_device_sysctl_post(ctx); 4904 ctx->ifc_flags |= IFC_INIT_DONE; 4905 CTX_UNLOCK(ctx); 4906 return (0); 4907 } 4908 _iflib_pre_assert(scctx); 4909 ctx->ifc_txrx = *scctx->isc_txrx; 4910 4911 if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) 4912 scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; 4913 if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) 4914 scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; 4915 4916 main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; 4917 main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; 4918 4919 /* XXX change for per-queue sizes */ 4920 device_printf(dev, "Using %d TX descriptors and %d RX descriptors\n", 4921 scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); 4922 4923 if (scctx->isc_tx_nsegments > scctx->isc_ntxd[main_txq] / 4924 MAX_SINGLE_PACKET_FRACTION) 4925 scctx->isc_tx_nsegments = max(1, scctx->isc_ntxd[main_txq] / 4926 MAX_SINGLE_PACKET_FRACTION); 4927 if (scctx->isc_tx_tso_segments_max > scctx->isc_ntxd[main_txq] / 4928 MAX_SINGLE_PACKET_FRACTION) 4929 scctx->isc_tx_tso_segments_max = max(1, 4930 scctx->isc_ntxd[main_txq] / MAX_SINGLE_PACKET_FRACTION); 4931 4932 /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ 4933 if (if_getcapabilities(ifp) & IFCAP_TSO) { 4934 /* 4935 * The stack can't handle a TSO size larger than IP_MAXPACKET, 4936 * but some MACs do. 4937 */ 4938 if_sethwtsomax(ifp, min(scctx->isc_tx_tso_size_max, 4939 IP_MAXPACKET)); 4940 /* 4941 * Take maximum number of m_pullup(9)'s in iflib_parse_header() 4942 * into account. In the worst case, each of these calls will 4943 * add another mbuf and, thus, the requirement for another DMA 4944 * segment. So for best performance, it doesn't make sense to 4945 * advertize a maximum of TSO segments that typically will 4946 * require defragmentation in iflib_encap(). 4947 */ 4948 if_sethwtsomaxsegcount(ifp, scctx->isc_tx_tso_segments_max - 3); 4949 if_sethwtsomaxsegsize(ifp, scctx->isc_tx_tso_segsize_max); 4950 } 4951 if (scctx->isc_rss_table_size == 0) 4952 scctx->isc_rss_table_size = 64; 4953 scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; 4954 4955 GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); 4956 /* XXX format name */ 4957 taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, 4958 NULL, NULL, "admin"); 4959 4960 /* XXX --- can support > 1 -- but keep it simple for now */ 4961 scctx->isc_intr = IFLIB_INTR_LEGACY; 4962 4963 /* Get memory for the station queues */ 4964 if ((err = iflib_queues_alloc(ctx))) { 4965 device_printf(dev, "Unable to allocate queue memory\n"); 4966 goto fail_iflib_detach; 4967 } 4968 4969 if ((err = iflib_qset_structures_setup(ctx))) { 4970 device_printf(dev, "qset structure setup failed %d\n", err); 4971 goto fail_queues; 4972 } 4973 4974 /* 4975 * XXX What if anything do we want to do about interrupts? 4976 */ 4977 ether_ifattach(ctx->ifc_ifp, ctx->ifc_mac.octet); 4978 if ((err = IFDI_ATTACH_POST(ctx)) != 0) { 4979 device_printf(dev, "IFDI_ATTACH_POST failed %d\n", err); 4980 goto fail_detach; 4981 } 4982 4983 /* 4984 * Tell the upper layer(s) if IFCAP_VLAN_MTU is supported. 4985 * This must appear after the call to ether_ifattach() because 4986 * ether_ifattach() sets if_hdrlen to the default value. 4987 */ 4988 if (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) 4989 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 4990 4991 /* XXX handle more than one queue */ 4992 for (i = 0; i < scctx->isc_nrxqsets; i++) 4993 IFDI_RX_CLSET(ctx, 0, i, ctx->ifc_rxqs[i].ifr_fl[0].ifl_sds.ifsd_cl); 4994 4995 *ctxp = ctx; 4996 4997 if_setgetcounterfn(ctx->ifc_ifp, iflib_if_get_counter); 4998 iflib_add_device_sysctl_post(ctx); 4999 ctx->ifc_flags |= IFC_INIT_DONE; 5000 CTX_UNLOCK(ctx); 5001 5002 return (0); 5003 fail_detach: 5004 ether_ifdetach(ctx->ifc_ifp); 5005 fail_queues: 5006 iflib_tx_structures_free(ctx); 5007 iflib_rx_structures_free(ctx); 5008 fail_iflib_detach: 5009 IFDI_DETACH(ctx); 5010 fail_unlock: 5011 CTX_UNLOCK(ctx); 5012 iflib_deregister(ctx); 5013 fail_ctx_free: 5014 free(ctx->ifc_softc, M_IFLIB); 5015 free(ctx, M_IFLIB); 5016 return (err); 5017 } 5018 5019 int 5020 iflib_pseudo_deregister(if_ctx_t ctx) 5021 { 5022 if_t ifp = ctx->ifc_ifp; 5023 iflib_txq_t txq; 5024 iflib_rxq_t rxq; 5025 int i, j; 5026 struct taskqgroup *tqg; 5027 iflib_fl_t fl; 5028 5029 /* Unregister VLAN event handlers early */ 5030 iflib_unregister_vlan_handlers(ctx); 5031 5032 ether_ifdetach(ifp); 5033 /* XXX drain any dependent tasks */ 5034 tqg = qgroup_if_io_tqg; 5035 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5036 callout_drain(&txq->ift_timer); 5037 if (txq->ift_task.gt_uniq != NULL) 5038 taskqgroup_detach(tqg, &txq->ift_task); 5039 } 5040 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5041 callout_drain(&rxq->ifr_watchdog); 5042 if (rxq->ifr_task.gt_uniq != NULL) 5043 taskqgroup_detach(tqg, &rxq->ifr_task); 5044 5045 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5046 free(fl->ifl_rx_bitmap, M_IFLIB); 5047 } 5048 tqg = qgroup_if_config_tqg; 5049 if (ctx->ifc_admin_task.gt_uniq != NULL) 5050 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5051 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5052 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5053 5054 iflib_tx_structures_free(ctx); 5055 iflib_rx_structures_free(ctx); 5056 5057 iflib_deregister(ctx); 5058 5059 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5060 free(ctx->ifc_softc, M_IFLIB); 5061 free(ctx, M_IFLIB); 5062 return (0); 5063 } 5064 5065 int 5066 iflib_device_attach(device_t dev) 5067 { 5068 if_ctx_t ctx; 5069 if_shared_ctx_t sctx; 5070 5071 if ((sctx = DEVICE_REGISTER(dev)) == NULL || sctx->isc_magic != IFLIB_MAGIC) 5072 return (ENOTSUP); 5073 5074 pci_enable_busmaster(dev); 5075 5076 return (iflib_device_register(dev, NULL, sctx, &ctx)); 5077 } 5078 5079 int 5080 iflib_device_deregister(if_ctx_t ctx) 5081 { 5082 if_t ifp = ctx->ifc_ifp; 5083 iflib_txq_t txq; 5084 iflib_rxq_t rxq; 5085 device_t dev = ctx->ifc_dev; 5086 int i, j; 5087 struct taskqgroup *tqg; 5088 iflib_fl_t fl; 5089 5090 /* Make sure VLANS are not using driver */ 5091 if (if_vlantrunkinuse(ifp)) { 5092 device_printf(dev, "Vlan in use, detach first\n"); 5093 return (EBUSY); 5094 } 5095 #ifdef PCI_IOV 5096 if (!CTX_IS_VF(ctx) && pci_iov_detach(dev) != 0) { 5097 device_printf(dev, "SR-IOV in use; detach first.\n"); 5098 return (EBUSY); 5099 } 5100 #endif 5101 5102 STATE_LOCK(ctx); 5103 ctx->ifc_flags |= IFC_IN_DETACH; 5104 STATE_UNLOCK(ctx); 5105 5106 /* Unregister VLAN handlers before calling iflib_stop() */ 5107 iflib_unregister_vlan_handlers(ctx); 5108 5109 iflib_netmap_detach(ifp); 5110 ether_ifdetach(ifp); 5111 5112 CTX_LOCK(ctx); 5113 iflib_stop(ctx); 5114 CTX_UNLOCK(ctx); 5115 5116 iflib_rem_pfil(ctx); 5117 if (ctx->ifc_led_dev != NULL) 5118 led_destroy(ctx->ifc_led_dev); 5119 /* XXX drain any dependent tasks */ 5120 tqg = qgroup_if_io_tqg; 5121 for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { 5122 callout_drain(&txq->ift_timer); 5123 if (txq->ift_task.gt_uniq != NULL) 5124 taskqgroup_detach(tqg, &txq->ift_task); 5125 } 5126 for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { 5127 if (rxq->ifr_task.gt_uniq != NULL) 5128 taskqgroup_detach(tqg, &rxq->ifr_task); 5129 5130 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5131 free(fl->ifl_rx_bitmap, M_IFLIB); 5132 } 5133 tqg = qgroup_if_config_tqg; 5134 if (ctx->ifc_admin_task.gt_uniq != NULL) 5135 taskqgroup_detach(tqg, &ctx->ifc_admin_task); 5136 if (ctx->ifc_vflr_task.gt_uniq != NULL) 5137 taskqgroup_detach(tqg, &ctx->ifc_vflr_task); 5138 CTX_LOCK(ctx); 5139 IFDI_DETACH(ctx); 5140 CTX_UNLOCK(ctx); 5141 5142 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5143 iflib_free_intr_mem(ctx); 5144 5145 bus_generic_detach(dev); 5146 5147 iflib_tx_structures_free(ctx); 5148 iflib_rx_structures_free(ctx); 5149 5150 iflib_deregister(ctx); 5151 5152 device_set_softc(ctx->ifc_dev, NULL); 5153 if (ctx->ifc_flags & IFC_SC_ALLOCATED) 5154 free(ctx->ifc_softc, M_IFLIB); 5155 unref_ctx_core_offset(ctx); 5156 free(ctx, M_IFLIB); 5157 return (0); 5158 } 5159 5160 static void 5161 iflib_free_intr_mem(if_ctx_t ctx) 5162 { 5163 5164 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_MSIX) { 5165 iflib_irq_free(ctx, &ctx->ifc_legacy_irq); 5166 } 5167 if (ctx->ifc_softc_ctx.isc_intr != IFLIB_INTR_LEGACY) { 5168 pci_release_msi(ctx->ifc_dev); 5169 } 5170 if (ctx->ifc_msix_mem != NULL) { 5171 bus_release_resource(ctx->ifc_dev, SYS_RES_MEMORY, 5172 rman_get_rid(ctx->ifc_msix_mem), ctx->ifc_msix_mem); 5173 ctx->ifc_msix_mem = NULL; 5174 } 5175 } 5176 5177 int 5178 iflib_device_detach(device_t dev) 5179 { 5180 if_ctx_t ctx = device_get_softc(dev); 5181 5182 return (iflib_device_deregister(ctx)); 5183 } 5184 5185 int 5186 iflib_device_suspend(device_t dev) 5187 { 5188 if_ctx_t ctx = device_get_softc(dev); 5189 5190 CTX_LOCK(ctx); 5191 IFDI_SUSPEND(ctx); 5192 CTX_UNLOCK(ctx); 5193 5194 return bus_generic_suspend(dev); 5195 } 5196 int 5197 iflib_device_shutdown(device_t dev) 5198 { 5199 if_ctx_t ctx = device_get_softc(dev); 5200 5201 CTX_LOCK(ctx); 5202 IFDI_SHUTDOWN(ctx); 5203 CTX_UNLOCK(ctx); 5204 5205 return bus_generic_suspend(dev); 5206 } 5207 5208 5209 int 5210 iflib_device_resume(device_t dev) 5211 { 5212 if_ctx_t ctx = device_get_softc(dev); 5213 iflib_txq_t txq = ctx->ifc_txqs; 5214 5215 CTX_LOCK(ctx); 5216 IFDI_RESUME(ctx); 5217 iflib_if_init_locked(ctx); 5218 CTX_UNLOCK(ctx); 5219 for (int i = 0; i < NTXQSETS(ctx); i++, txq++) 5220 iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); 5221 5222 return (bus_generic_resume(dev)); 5223 } 5224 5225 int 5226 iflib_device_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 5227 { 5228 int error; 5229 if_ctx_t ctx = device_get_softc(dev); 5230 5231 CTX_LOCK(ctx); 5232 error = IFDI_IOV_INIT(ctx, num_vfs, params); 5233 CTX_UNLOCK(ctx); 5234 5235 return (error); 5236 } 5237 5238 void 5239 iflib_device_iov_uninit(device_t dev) 5240 { 5241 if_ctx_t ctx = device_get_softc(dev); 5242 5243 CTX_LOCK(ctx); 5244 IFDI_IOV_UNINIT(ctx); 5245 CTX_UNLOCK(ctx); 5246 } 5247 5248 int 5249 iflib_device_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 5250 { 5251 int error; 5252 if_ctx_t ctx = device_get_softc(dev); 5253 5254 CTX_LOCK(ctx); 5255 error = IFDI_IOV_VF_ADD(ctx, vfnum, params); 5256 CTX_UNLOCK(ctx); 5257 5258 return (error); 5259 } 5260 5261 /********************************************************************* 5262 * 5263 * MODULE FUNCTION DEFINITIONS 5264 * 5265 **********************************************************************/ 5266 5267 /* 5268 * - Start a fast taskqueue thread for each core 5269 * - Start a taskqueue for control operations 5270 */ 5271 static int 5272 iflib_module_init(void) 5273 { 5274 return (0); 5275 } 5276 5277 static int 5278 iflib_module_event_handler(module_t mod, int what, void *arg) 5279 { 5280 int err; 5281 5282 switch (what) { 5283 case MOD_LOAD: 5284 if ((err = iflib_module_init()) != 0) 5285 return (err); 5286 break; 5287 case MOD_UNLOAD: 5288 return (EBUSY); 5289 default: 5290 return (EOPNOTSUPP); 5291 } 5292 5293 return (0); 5294 } 5295 5296 /********************************************************************* 5297 * 5298 * PUBLIC FUNCTION DEFINITIONS 5299 * ordered as in iflib.h 5300 * 5301 **********************************************************************/ 5302 5303 5304 static void 5305 _iflib_assert(if_shared_ctx_t sctx) 5306 { 5307 int i; 5308 5309 MPASS(sctx->isc_tx_maxsize); 5310 MPASS(sctx->isc_tx_maxsegsize); 5311 5312 MPASS(sctx->isc_rx_maxsize); 5313 MPASS(sctx->isc_rx_nsegments); 5314 MPASS(sctx->isc_rx_maxsegsize); 5315 5316 MPASS(sctx->isc_nrxqs >= 1 && sctx->isc_nrxqs <= 8); 5317 for (i = 0; i < sctx->isc_nrxqs; i++) { 5318 MPASS(sctx->isc_nrxd_min[i]); 5319 MPASS(powerof2(sctx->isc_nrxd_min[i])); 5320 MPASS(sctx->isc_nrxd_max[i]); 5321 MPASS(powerof2(sctx->isc_nrxd_max[i])); 5322 MPASS(sctx->isc_nrxd_default[i]); 5323 MPASS(powerof2(sctx->isc_nrxd_default[i])); 5324 } 5325 5326 MPASS(sctx->isc_ntxqs >= 1 && sctx->isc_ntxqs <= 8); 5327 for (i = 0; i < sctx->isc_ntxqs; i++) { 5328 MPASS(sctx->isc_ntxd_min[i]); 5329 MPASS(powerof2(sctx->isc_ntxd_min[i])); 5330 MPASS(sctx->isc_ntxd_max[i]); 5331 MPASS(powerof2(sctx->isc_ntxd_max[i])); 5332 MPASS(sctx->isc_ntxd_default[i]); 5333 MPASS(powerof2(sctx->isc_ntxd_default[i])); 5334 } 5335 } 5336 5337 static void 5338 _iflib_pre_assert(if_softc_ctx_t scctx) 5339 { 5340 5341 MPASS(scctx->isc_txrx->ift_txd_encap); 5342 MPASS(scctx->isc_txrx->ift_txd_flush); 5343 MPASS(scctx->isc_txrx->ift_txd_credits_update); 5344 MPASS(scctx->isc_txrx->ift_rxd_available); 5345 MPASS(scctx->isc_txrx->ift_rxd_pkt_get); 5346 MPASS(scctx->isc_txrx->ift_rxd_refill); 5347 MPASS(scctx->isc_txrx->ift_rxd_flush); 5348 } 5349 5350 static int 5351 iflib_register(if_ctx_t ctx) 5352 { 5353 if_shared_ctx_t sctx = ctx->ifc_sctx; 5354 driver_t *driver = sctx->isc_driver; 5355 device_t dev = ctx->ifc_dev; 5356 if_t ifp; 5357 5358 if ((sctx->isc_flags & IFLIB_PSEUDO) == 0) 5359 _iflib_assert(sctx); 5360 5361 CTX_LOCK_INIT(ctx); 5362 STATE_LOCK_INIT(ctx, device_get_nameunit(ctx->ifc_dev)); 5363 ifp = ctx->ifc_ifp = if_alloc(IFT_ETHER); 5364 if (ifp == NULL) { 5365 device_printf(dev, "can not allocate ifnet structure\n"); 5366 return (ENOMEM); 5367 } 5368 5369 /* 5370 * Initialize our context's device specific methods 5371 */ 5372 kobj_init((kobj_t) ctx, (kobj_class_t) driver); 5373 kobj_class_compile((kobj_class_t) driver); 5374 5375 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 5376 if_setsoftc(ifp, ctx); 5377 if_setdev(ifp, dev); 5378 if_setinitfn(ifp, iflib_if_init); 5379 if_setioctlfn(ifp, iflib_if_ioctl); 5380 #ifdef ALTQ 5381 if_setstartfn(ifp, iflib_altq_if_start); 5382 if_settransmitfn(ifp, iflib_altq_if_transmit); 5383 if_setsendqready(ifp); 5384 #else 5385 if_settransmitfn(ifp, iflib_if_transmit); 5386 #endif 5387 if_setqflushfn(ifp, iflib_if_qflush); 5388 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 5389 IFF_KNOWSEPOCH); 5390 5391 ctx->ifc_vlan_attach_event = 5392 EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, 5393 EVENTHANDLER_PRI_FIRST); 5394 ctx->ifc_vlan_detach_event = 5395 EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, 5396 EVENTHANDLER_PRI_FIRST); 5397 5398 if ((sctx->isc_flags & IFLIB_DRIVER_MEDIA) == 0) { 5399 ctx->ifc_mediap = &ctx->ifc_media; 5400 ifmedia_init(ctx->ifc_mediap, IFM_IMASK, 5401 iflib_media_change, iflib_media_status); 5402 } 5403 return (0); 5404 } 5405 5406 static void 5407 iflib_unregister_vlan_handlers(if_ctx_t ctx) 5408 { 5409 /* Unregister VLAN events */ 5410 if (ctx->ifc_vlan_attach_event != NULL) { 5411 EVENTHANDLER_DEREGISTER(vlan_config, ctx->ifc_vlan_attach_event); 5412 ctx->ifc_vlan_attach_event = NULL; 5413 } 5414 if (ctx->ifc_vlan_detach_event != NULL) { 5415 EVENTHANDLER_DEREGISTER(vlan_unconfig, ctx->ifc_vlan_detach_event); 5416 ctx->ifc_vlan_detach_event = NULL; 5417 } 5418 5419 } 5420 5421 static void 5422 iflib_deregister(if_ctx_t ctx) 5423 { 5424 if_t ifp = ctx->ifc_ifp; 5425 5426 /* Remove all media */ 5427 ifmedia_removeall(&ctx->ifc_media); 5428 5429 /* Ensure that VLAN event handlers are unregistered */ 5430 iflib_unregister_vlan_handlers(ctx); 5431 5432 /* Release kobject reference */ 5433 kobj_delete((kobj_t) ctx, NULL); 5434 5435 /* Free the ifnet structure */ 5436 if_free(ifp); 5437 5438 STATE_LOCK_DESTROY(ctx); 5439 5440 /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ 5441 CTX_LOCK_DESTROY(ctx); 5442 } 5443 5444 static int 5445 iflib_queues_alloc(if_ctx_t ctx) 5446 { 5447 if_shared_ctx_t sctx = ctx->ifc_sctx; 5448 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 5449 device_t dev = ctx->ifc_dev; 5450 int nrxqsets = scctx->isc_nrxqsets; 5451 int ntxqsets = scctx->isc_ntxqsets; 5452 iflib_txq_t txq; 5453 iflib_rxq_t rxq; 5454 iflib_fl_t fl = NULL; 5455 int i, j, cpu, err, txconf, rxconf; 5456 iflib_dma_info_t ifdip; 5457 uint32_t *rxqsizes = scctx->isc_rxqsizes; 5458 uint32_t *txqsizes = scctx->isc_txqsizes; 5459 uint8_t nrxqs = sctx->isc_nrxqs; 5460 uint8_t ntxqs = sctx->isc_ntxqs; 5461 int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; 5462 caddr_t *vaddrs; 5463 uint64_t *paddrs; 5464 5465 KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); 5466 KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); 5467 5468 /* Allocate the TX ring struct memory */ 5469 if (!(ctx->ifc_txqs = 5470 (iflib_txq_t) malloc(sizeof(struct iflib_txq) * 5471 ntxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5472 device_printf(dev, "Unable to allocate TX ring memory\n"); 5473 err = ENOMEM; 5474 goto fail; 5475 } 5476 5477 /* Now allocate the RX */ 5478 if (!(ctx->ifc_rxqs = 5479 (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * 5480 nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { 5481 device_printf(dev, "Unable to allocate RX ring memory\n"); 5482 err = ENOMEM; 5483 goto rx_fail; 5484 } 5485 5486 txq = ctx->ifc_txqs; 5487 rxq = ctx->ifc_rxqs; 5488 5489 /* 5490 * XXX handle allocation failure 5491 */ 5492 for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { 5493 /* Set up some basics */ 5494 5495 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, 5496 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5497 device_printf(dev, 5498 "Unable to allocate TX DMA info memory\n"); 5499 err = ENOMEM; 5500 goto err_tx_desc; 5501 } 5502 txq->ift_ifdi = ifdip; 5503 for (j = 0; j < ntxqs; j++, ifdip++) { 5504 if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, 0)) { 5505 device_printf(dev, 5506 "Unable to allocate TX descriptors\n"); 5507 err = ENOMEM; 5508 goto err_tx_desc; 5509 } 5510 txq->ift_txd_size[j] = scctx->isc_txd_size[j]; 5511 bzero((void *)ifdip->idi_vaddr, txqsizes[j]); 5512 } 5513 txq->ift_ctx = ctx; 5514 txq->ift_id = i; 5515 if (sctx->isc_flags & IFLIB_HAS_TXCQ) { 5516 txq->ift_br_offset = 1; 5517 } else { 5518 txq->ift_br_offset = 0; 5519 } 5520 /* XXX fix this */ 5521 txq->ift_timer.c_cpu = cpu; 5522 5523 if (iflib_txsd_alloc(txq)) { 5524 device_printf(dev, "Critical Failure setting up TX buffers\n"); 5525 err = ENOMEM; 5526 goto err_tx_desc; 5527 } 5528 5529 /* Initialize the TX lock */ 5530 snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:TX(%d):callout", 5531 device_get_nameunit(dev), txq->ift_id); 5532 mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); 5533 callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); 5534 5535 err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, 5536 iflib_txq_can_drain, M_IFLIB, M_WAITOK); 5537 if (err) { 5538 /* XXX free any allocated rings */ 5539 device_printf(dev, "Unable to allocate buf_ring\n"); 5540 goto err_tx_desc; 5541 } 5542 } 5543 5544 for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { 5545 /* Set up some basics */ 5546 callout_init(&rxq->ifr_watchdog, 1); 5547 5548 if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, 5549 M_IFLIB, M_NOWAIT | M_ZERO)) == NULL) { 5550 device_printf(dev, 5551 "Unable to allocate RX DMA info memory\n"); 5552 err = ENOMEM; 5553 goto err_tx_desc; 5554 } 5555 5556 rxq->ifr_ifdi = ifdip; 5557 /* XXX this needs to be changed if #rx queues != #tx queues */ 5558 rxq->ifr_ntxqirq = 1; 5559 rxq->ifr_txqid[0] = i; 5560 for (j = 0; j < nrxqs; j++, ifdip++) { 5561 if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, 0)) { 5562 device_printf(dev, 5563 "Unable to allocate RX descriptors\n"); 5564 err = ENOMEM; 5565 goto err_tx_desc; 5566 } 5567 bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); 5568 } 5569 rxq->ifr_ctx = ctx; 5570 rxq->ifr_id = i; 5571 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 5572 rxq->ifr_fl_offset = 1; 5573 } else { 5574 rxq->ifr_fl_offset = 0; 5575 } 5576 rxq->ifr_nfl = nfree_lists; 5577 if (!(fl = 5578 (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { 5579 device_printf(dev, "Unable to allocate free list memory\n"); 5580 err = ENOMEM; 5581 goto err_tx_desc; 5582 } 5583 rxq->ifr_fl = fl; 5584 for (j = 0; j < nfree_lists; j++) { 5585 fl[j].ifl_rxq = rxq; 5586 fl[j].ifl_id = j; 5587 fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; 5588 fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; 5589 } 5590 /* Allocate receive buffers for the ring */ 5591 if (iflib_rxsd_alloc(rxq)) { 5592 device_printf(dev, 5593 "Critical Failure setting up receive buffers\n"); 5594 err = ENOMEM; 5595 goto err_rx_desc; 5596 } 5597 5598 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) 5599 fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, 5600 M_WAITOK); 5601 } 5602 5603 /* TXQs */ 5604 vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5605 paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); 5606 for (i = 0; i < ntxqsets; i++) { 5607 iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; 5608 5609 for (j = 0; j < ntxqs; j++, di++) { 5610 vaddrs[i*ntxqs + j] = di->idi_vaddr; 5611 paddrs[i*ntxqs + j] = di->idi_paddr; 5612 } 5613 } 5614 if ((err = IFDI_TX_QUEUES_ALLOC(ctx, vaddrs, paddrs, ntxqs, ntxqsets)) != 0) { 5615 device_printf(ctx->ifc_dev, 5616 "Unable to allocate device TX queue\n"); 5617 iflib_tx_structures_free(ctx); 5618 free(vaddrs, M_IFLIB); 5619 free(paddrs, M_IFLIB); 5620 goto err_rx_desc; 5621 } 5622 free(vaddrs, M_IFLIB); 5623 free(paddrs, M_IFLIB); 5624 5625 /* RXQs */ 5626 vaddrs = malloc(sizeof(caddr_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5627 paddrs = malloc(sizeof(uint64_t)*nrxqsets*nrxqs, M_IFLIB, M_WAITOK); 5628 for (i = 0; i < nrxqsets; i++) { 5629 iflib_dma_info_t di = ctx->ifc_rxqs[i].ifr_ifdi; 5630 5631 for (j = 0; j < nrxqs; j++, di++) { 5632 vaddrs[i*nrxqs + j] = di->idi_vaddr; 5633 paddrs[i*nrxqs + j] = di->idi_paddr; 5634 } 5635 } 5636 if ((err = IFDI_RX_QUEUES_ALLOC(ctx, vaddrs, paddrs, nrxqs, nrxqsets)) != 0) { 5637 device_printf(ctx->ifc_dev, 5638 "Unable to allocate device RX queue\n"); 5639 iflib_tx_structures_free(ctx); 5640 free(vaddrs, M_IFLIB); 5641 free(paddrs, M_IFLIB); 5642 goto err_rx_desc; 5643 } 5644 free(vaddrs, M_IFLIB); 5645 free(paddrs, M_IFLIB); 5646 5647 return (0); 5648 5649 /* XXX handle allocation failure changes */ 5650 err_rx_desc: 5651 err_tx_desc: 5652 rx_fail: 5653 if (ctx->ifc_rxqs != NULL) 5654 free(ctx->ifc_rxqs, M_IFLIB); 5655 ctx->ifc_rxqs = NULL; 5656 if (ctx->ifc_txqs != NULL) 5657 free(ctx->ifc_txqs, M_IFLIB); 5658 ctx->ifc_txqs = NULL; 5659 fail: 5660 return (err); 5661 } 5662 5663 static int 5664 iflib_tx_structures_setup(if_ctx_t ctx) 5665 { 5666 iflib_txq_t txq = ctx->ifc_txqs; 5667 int i; 5668 5669 for (i = 0; i < NTXQSETS(ctx); i++, txq++) 5670 iflib_txq_setup(txq); 5671 5672 return (0); 5673 } 5674 5675 static void 5676 iflib_tx_structures_free(if_ctx_t ctx) 5677 { 5678 iflib_txq_t txq = ctx->ifc_txqs; 5679 if_shared_ctx_t sctx = ctx->ifc_sctx; 5680 int i, j; 5681 5682 for (i = 0; i < NTXQSETS(ctx); i++, txq++) { 5683 for (j = 0; j < sctx->isc_ntxqs; j++) 5684 iflib_dma_free(&txq->ift_ifdi[j]); 5685 iflib_txq_destroy(txq); 5686 } 5687 free(ctx->ifc_txqs, M_IFLIB); 5688 ctx->ifc_txqs = NULL; 5689 IFDI_QUEUES_FREE(ctx); 5690 } 5691 5692 /********************************************************************* 5693 * 5694 * Initialize all receive rings. 5695 * 5696 **********************************************************************/ 5697 static int 5698 iflib_rx_structures_setup(if_ctx_t ctx) 5699 { 5700 iflib_rxq_t rxq = ctx->ifc_rxqs; 5701 int q; 5702 #if defined(INET6) || defined(INET) 5703 int err, i; 5704 #endif 5705 5706 for (q = 0; q < ctx->ifc_softc_ctx.isc_nrxqsets; q++, rxq++) { 5707 #if defined(INET6) || defined(INET) 5708 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) { 5709 err = tcp_lro_init_args(&rxq->ifr_lc, ctx->ifc_ifp, 5710 TCP_LRO_ENTRIES, min(1024, 5711 ctx->ifc_softc_ctx.isc_nrxd[rxq->ifr_fl_offset])); 5712 if (err != 0) { 5713 device_printf(ctx->ifc_dev, 5714 "LRO Initialization failed!\n"); 5715 goto fail; 5716 } 5717 } 5718 #endif 5719 IFDI_RXQ_SETUP(ctx, rxq->ifr_id); 5720 } 5721 return (0); 5722 #if defined(INET6) || defined(INET) 5723 fail: 5724 /* 5725 * Free LRO resources allocated so far, we will only handle 5726 * the rings that completed, the failing case will have 5727 * cleaned up for itself. 'q' failed, so its the terminus. 5728 */ 5729 rxq = ctx->ifc_rxqs; 5730 for (i = 0; i < q; ++i, rxq++) { 5731 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5732 tcp_lro_free(&rxq->ifr_lc); 5733 } 5734 return (err); 5735 #endif 5736 } 5737 5738 /********************************************************************* 5739 * 5740 * Free all receive rings. 5741 * 5742 **********************************************************************/ 5743 static void 5744 iflib_rx_structures_free(if_ctx_t ctx) 5745 { 5746 iflib_rxq_t rxq = ctx->ifc_rxqs; 5747 if_shared_ctx_t sctx = ctx->ifc_sctx; 5748 int i, j; 5749 5750 for (i = 0; i < ctx->ifc_softc_ctx.isc_nrxqsets; i++, rxq++) { 5751 for (j = 0; j < sctx->isc_nrxqs; j++) 5752 iflib_dma_free(&rxq->ifr_ifdi[j]); 5753 iflib_rx_sds_free(rxq); 5754 #if defined(INET6) || defined(INET) 5755 if (if_getcapabilities(ctx->ifc_ifp) & IFCAP_LRO) 5756 tcp_lro_free(&rxq->ifr_lc); 5757 #endif 5758 } 5759 free(ctx->ifc_rxqs, M_IFLIB); 5760 ctx->ifc_rxqs = NULL; 5761 } 5762 5763 static int 5764 iflib_qset_structures_setup(if_ctx_t ctx) 5765 { 5766 int err; 5767 5768 /* 5769 * It is expected that the caller takes care of freeing queues if this 5770 * fails. 5771 */ 5772 if ((err = iflib_tx_structures_setup(ctx)) != 0) { 5773 device_printf(ctx->ifc_dev, "iflib_tx_structures_setup failed: %d\n", err); 5774 return (err); 5775 } 5776 5777 if ((err = iflib_rx_structures_setup(ctx)) != 0) 5778 device_printf(ctx->ifc_dev, "iflib_rx_structures_setup failed: %d\n", err); 5779 5780 return (err); 5781 } 5782 5783 int 5784 iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, 5785 driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, const char *name) 5786 { 5787 5788 return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); 5789 } 5790 5791 #ifdef SMP 5792 static int 5793 find_nth(if_ctx_t ctx, int qid) 5794 { 5795 cpuset_t cpus; 5796 int i, cpuid, eqid, count; 5797 5798 CPU_COPY(&ctx->ifc_cpus, &cpus); 5799 count = CPU_COUNT(&cpus); 5800 eqid = qid % count; 5801 /* clear up to the qid'th bit */ 5802 for (i = 0; i < eqid; i++) { 5803 cpuid = CPU_FFS(&cpus); 5804 MPASS(cpuid != 0); 5805 CPU_CLR(cpuid-1, &cpus); 5806 } 5807 cpuid = CPU_FFS(&cpus); 5808 MPASS(cpuid != 0); 5809 return (cpuid-1); 5810 } 5811 5812 #ifdef SCHED_ULE 5813 extern struct cpu_group *cpu_top; /* CPU topology */ 5814 5815 static int 5816 find_child_with_core(int cpu, struct cpu_group *grp) 5817 { 5818 int i; 5819 5820 if (grp->cg_children == 0) 5821 return -1; 5822 5823 MPASS(grp->cg_child); 5824 for (i = 0; i < grp->cg_children; i++) { 5825 if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) 5826 return i; 5827 } 5828 5829 return -1; 5830 } 5831 5832 /* 5833 * Find the nth "close" core to the specified core 5834 * "close" is defined as the deepest level that shares 5835 * at least an L2 cache. With threads, this will be 5836 * threads on the same core. If the shared cache is L3 5837 * or higher, simply returns the same core. 5838 */ 5839 static int 5840 find_close_core(int cpu, int core_offset) 5841 { 5842 struct cpu_group *grp; 5843 int i; 5844 int fcpu; 5845 cpuset_t cs; 5846 5847 grp = cpu_top; 5848 if (grp == NULL) 5849 return cpu; 5850 i = 0; 5851 while ((i = find_child_with_core(cpu, grp)) != -1) { 5852 /* If the child only has one cpu, don't descend */ 5853 if (grp->cg_child[i].cg_count <= 1) 5854 break; 5855 grp = &grp->cg_child[i]; 5856 } 5857 5858 /* If they don't share at least an L2 cache, use the same CPU */ 5859 if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) 5860 return cpu; 5861 5862 /* Now pick one */ 5863 CPU_COPY(&grp->cg_mask, &cs); 5864 5865 /* Add the selected CPU offset to core offset. */ 5866 for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { 5867 if (fcpu - 1 == cpu) 5868 break; 5869 CPU_CLR(fcpu - 1, &cs); 5870 } 5871 MPASS(fcpu); 5872 5873 core_offset += i; 5874 5875 CPU_COPY(&grp->cg_mask, &cs); 5876 for (i = core_offset % grp->cg_count; i > 0; i--) { 5877 MPASS(CPU_FFS(&cs)); 5878 CPU_CLR(CPU_FFS(&cs) - 1, &cs); 5879 } 5880 MPASS(CPU_FFS(&cs)); 5881 return CPU_FFS(&cs) - 1; 5882 } 5883 #else 5884 static int 5885 find_close_core(int cpu, int core_offset __unused) 5886 { 5887 return cpu; 5888 } 5889 #endif 5890 5891 static int 5892 get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) 5893 { 5894 switch (type) { 5895 case IFLIB_INTR_TX: 5896 /* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ 5897 /* XXX handle multiple RX threads per core and more than two core per L2 group */ 5898 return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; 5899 case IFLIB_INTR_RX: 5900 case IFLIB_INTR_RXTX: 5901 /* RX queues get the specified core */ 5902 return qid / CPU_COUNT(&ctx->ifc_cpus); 5903 default: 5904 return -1; 5905 } 5906 } 5907 #else 5908 #define get_core_offset(ctx, type, qid) CPU_FIRST() 5909 #define find_close_core(cpuid, tid) CPU_FIRST() 5910 #define find_nth(ctx, gid) CPU_FIRST() 5911 #endif 5912 5913 /* Just to avoid copy/paste */ 5914 static inline int 5915 iflib_irq_set_affinity(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, 5916 int qid, struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, 5917 const char *name) 5918 { 5919 device_t dev; 5920 int co, cpuid, err, tid; 5921 5922 dev = ctx->ifc_dev; 5923 co = ctx->ifc_sysctl_core_offset; 5924 if (ctx->ifc_sysctl_separate_txrx && type == IFLIB_INTR_TX) 5925 co += ctx->ifc_softc_ctx.isc_nrxqsets; 5926 cpuid = find_nth(ctx, qid + co); 5927 tid = get_core_offset(ctx, type, qid); 5928 if (tid < 0) { 5929 device_printf(dev, "get_core_offset failed\n"); 5930 return (EOPNOTSUPP); 5931 } 5932 cpuid = find_close_core(cpuid, tid); 5933 err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, dev, irq->ii_res, 5934 name); 5935 if (err) { 5936 device_printf(dev, "taskqgroup_attach_cpu failed %d\n", err); 5937 return (err); 5938 } 5939 #ifdef notyet 5940 if (cpuid > ctx->ifc_cpuid_highest) 5941 ctx->ifc_cpuid_highest = cpuid; 5942 #endif 5943 return (0); 5944 } 5945 5946 int 5947 iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, 5948 iflib_intr_type_t type, driver_filter_t *filter, 5949 void *filter_arg, int qid, const char *name) 5950 { 5951 device_t dev; 5952 struct grouptask *gtask; 5953 struct taskqgroup *tqg; 5954 iflib_filter_info_t info; 5955 gtask_fn_t *fn; 5956 int tqrid, err; 5957 driver_filter_t *intr_fast; 5958 void *q; 5959 5960 info = &ctx->ifc_filter_info; 5961 tqrid = rid; 5962 5963 switch (type) { 5964 /* XXX merge tx/rx for netmap? */ 5965 case IFLIB_INTR_TX: 5966 q = &ctx->ifc_txqs[qid]; 5967 info = &ctx->ifc_txqs[qid].ift_filter_info; 5968 gtask = &ctx->ifc_txqs[qid].ift_task; 5969 tqg = qgroup_if_io_tqg; 5970 fn = _task_fn_tx; 5971 intr_fast = iflib_fast_intr; 5972 GROUPTASK_INIT(gtask, 0, fn, q); 5973 ctx->ifc_flags |= IFC_NETMAP_TX_IRQ; 5974 break; 5975 case IFLIB_INTR_RX: 5976 q = &ctx->ifc_rxqs[qid]; 5977 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5978 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5979 tqg = qgroup_if_io_tqg; 5980 fn = _task_fn_rx; 5981 intr_fast = iflib_fast_intr; 5982 NET_GROUPTASK_INIT(gtask, 0, fn, q); 5983 break; 5984 case IFLIB_INTR_RXTX: 5985 q = &ctx->ifc_rxqs[qid]; 5986 info = &ctx->ifc_rxqs[qid].ifr_filter_info; 5987 gtask = &ctx->ifc_rxqs[qid].ifr_task; 5988 tqg = qgroup_if_io_tqg; 5989 fn = _task_fn_rx; 5990 intr_fast = iflib_fast_intr_rxtx; 5991 NET_GROUPTASK_INIT(gtask, 0, fn, q); 5992 break; 5993 case IFLIB_INTR_ADMIN: 5994 q = ctx; 5995 tqrid = -1; 5996 info = &ctx->ifc_filter_info; 5997 gtask = &ctx->ifc_admin_task; 5998 tqg = qgroup_if_config_tqg; 5999 fn = _task_fn_admin; 6000 intr_fast = iflib_fast_intr_ctx; 6001 break; 6002 default: 6003 device_printf(ctx->ifc_dev, "%s: unknown net intr type\n", 6004 __func__); 6005 return (EINVAL); 6006 } 6007 6008 info->ifi_filter = filter; 6009 info->ifi_filter_arg = filter_arg; 6010 info->ifi_task = gtask; 6011 info->ifi_ctx = q; 6012 6013 dev = ctx->ifc_dev; 6014 err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); 6015 if (err != 0) { 6016 device_printf(dev, "_iflib_irq_alloc failed %d\n", err); 6017 return (err); 6018 } 6019 if (type == IFLIB_INTR_ADMIN) 6020 return (0); 6021 6022 if (tqrid != -1) { 6023 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6024 q, name); 6025 if (err) 6026 return (err); 6027 } else { 6028 taskqgroup_attach(tqg, gtask, q, dev, irq->ii_res, name); 6029 } 6030 6031 return (0); 6032 } 6033 6034 void 6035 iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, const char *name) 6036 { 6037 struct grouptask *gtask; 6038 struct taskqgroup *tqg; 6039 gtask_fn_t *fn; 6040 void *q; 6041 int err; 6042 6043 switch (type) { 6044 case IFLIB_INTR_TX: 6045 q = &ctx->ifc_txqs[qid]; 6046 gtask = &ctx->ifc_txqs[qid].ift_task; 6047 tqg = qgroup_if_io_tqg; 6048 fn = _task_fn_tx; 6049 GROUPTASK_INIT(gtask, 0, fn, q); 6050 break; 6051 case IFLIB_INTR_RX: 6052 q = &ctx->ifc_rxqs[qid]; 6053 gtask = &ctx->ifc_rxqs[qid].ifr_task; 6054 tqg = qgroup_if_io_tqg; 6055 fn = _task_fn_rx; 6056 NET_GROUPTASK_INIT(gtask, 0, fn, q); 6057 break; 6058 case IFLIB_INTR_IOV: 6059 q = ctx; 6060 gtask = &ctx->ifc_vflr_task; 6061 tqg = qgroup_if_config_tqg; 6062 fn = _task_fn_iov; 6063 GROUPTASK_INIT(gtask, 0, fn, q); 6064 break; 6065 default: 6066 panic("unknown net intr type"); 6067 } 6068 if (irq != NULL) { 6069 err = iflib_irq_set_affinity(ctx, irq, type, qid, gtask, tqg, 6070 q, name); 6071 if (err) 6072 taskqgroup_attach(tqg, gtask, q, ctx->ifc_dev, 6073 irq->ii_res, name); 6074 } else { 6075 taskqgroup_attach(tqg, gtask, q, NULL, NULL, name); 6076 } 6077 } 6078 6079 void 6080 iflib_irq_free(if_ctx_t ctx, if_irq_t irq) 6081 { 6082 6083 if (irq->ii_tag) 6084 bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); 6085 6086 if (irq->ii_res) 6087 bus_release_resource(ctx->ifc_dev, SYS_RES_IRQ, 6088 rman_get_rid(irq->ii_res), irq->ii_res); 6089 } 6090 6091 static int 6092 iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, const char *name) 6093 { 6094 iflib_txq_t txq = ctx->ifc_txqs; 6095 iflib_rxq_t rxq = ctx->ifc_rxqs; 6096 if_irq_t irq = &ctx->ifc_legacy_irq; 6097 iflib_filter_info_t info; 6098 device_t dev; 6099 struct grouptask *gtask; 6100 struct resource *res; 6101 struct taskqgroup *tqg; 6102 void *q; 6103 int err, tqrid; 6104 bool rx_only; 6105 6106 q = &ctx->ifc_rxqs[0]; 6107 info = &rxq[0].ifr_filter_info; 6108 gtask = &rxq[0].ifr_task; 6109 tqg = qgroup_if_io_tqg; 6110 tqrid = *rid; 6111 rx_only = (ctx->ifc_sctx->isc_flags & IFLIB_SINGLE_IRQ_RX_ONLY) != 0; 6112 6113 ctx->ifc_flags |= IFC_LEGACY; 6114 info->ifi_filter = filter; 6115 info->ifi_filter_arg = filter_arg; 6116 info->ifi_task = gtask; 6117 info->ifi_ctx = rx_only ? ctx : q; 6118 6119 dev = ctx->ifc_dev; 6120 /* We allocate a single interrupt resource */ 6121 err = _iflib_irq_alloc(ctx, irq, tqrid, rx_only ? iflib_fast_intr_ctx : 6122 iflib_fast_intr_rxtx, NULL, info, name); 6123 if (err != 0) 6124 return (err); 6125 NET_GROUPTASK_INIT(gtask, 0, _task_fn_rx, q); 6126 res = irq->ii_res; 6127 taskqgroup_attach(tqg, gtask, q, dev, res, name); 6128 6129 GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); 6130 taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, dev, res, 6131 "tx"); 6132 return (0); 6133 } 6134 6135 void 6136 iflib_led_create(if_ctx_t ctx) 6137 { 6138 6139 ctx->ifc_led_dev = led_create(iflib_led_func, ctx, 6140 device_get_nameunit(ctx->ifc_dev)); 6141 } 6142 6143 void 6144 iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) 6145 { 6146 6147 GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); 6148 } 6149 6150 void 6151 iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) 6152 { 6153 6154 GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); 6155 } 6156 6157 void 6158 iflib_admin_intr_deferred(if_ctx_t ctx) 6159 { 6160 6161 MPASS(ctx->ifc_admin_task.gt_taskqueue != NULL); 6162 GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); 6163 } 6164 6165 void 6166 iflib_iov_intr_deferred(if_ctx_t ctx) 6167 { 6168 6169 GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); 6170 } 6171 6172 void 6173 iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, const char *name) 6174 { 6175 6176 taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, NULL, NULL, 6177 name); 6178 } 6179 6180 void 6181 iflib_config_gtask_init(void *ctx, struct grouptask *gtask, gtask_fn_t *fn, 6182 const char *name) 6183 { 6184 6185 GROUPTASK_INIT(gtask, 0, fn, ctx); 6186 taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, NULL, NULL, 6187 name); 6188 } 6189 6190 void 6191 iflib_config_gtask_deinit(struct grouptask *gtask) 6192 { 6193 6194 taskqgroup_detach(qgroup_if_config_tqg, gtask); 6195 } 6196 6197 void 6198 iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) 6199 { 6200 if_t ifp = ctx->ifc_ifp; 6201 iflib_txq_t txq = ctx->ifc_txqs; 6202 6203 if_setbaudrate(ifp, baudrate); 6204 if (baudrate >= IF_Gbps(10)) { 6205 STATE_LOCK(ctx); 6206 ctx->ifc_flags |= IFC_PREFETCH; 6207 STATE_UNLOCK(ctx); 6208 } 6209 /* If link down, disable watchdog */ 6210 if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { 6211 for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) 6212 txq->ift_qstatus = IFLIB_QUEUE_IDLE; 6213 } 6214 ctx->ifc_link_state = link_state; 6215 if_link_state_change(ifp, link_state); 6216 } 6217 6218 static int 6219 iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) 6220 { 6221 int credits; 6222 #ifdef INVARIANTS 6223 int credits_pre = txq->ift_cidx_processed; 6224 #endif 6225 6226 bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, 6227 BUS_DMASYNC_POSTREAD); 6228 if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) 6229 return (0); 6230 6231 txq->ift_processed += credits; 6232 txq->ift_cidx_processed += credits; 6233 6234 MPASS(credits_pre + credits == txq->ift_cidx_processed); 6235 if (txq->ift_cidx_processed >= txq->ift_size) 6236 txq->ift_cidx_processed -= txq->ift_size; 6237 return (credits); 6238 } 6239 6240 static int 6241 iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) 6242 { 6243 iflib_fl_t fl; 6244 u_int i; 6245 6246 for (i = 0, fl = &rxq->ifr_fl[0]; i < rxq->ifr_nfl; i++, fl++) 6247 bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, 6248 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6249 return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, 6250 budget)); 6251 } 6252 6253 void 6254 iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, 6255 const char *description, if_int_delay_info_t info, 6256 int offset, int value) 6257 { 6258 info->iidi_ctx = ctx; 6259 info->iidi_offset = offset; 6260 info->iidi_value = value; 6261 SYSCTL_ADD_PROC(device_get_sysctl_ctx(ctx->ifc_dev), 6262 SYSCTL_CHILDREN(device_get_sysctl_tree(ctx->ifc_dev)), 6263 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, 6264 info, 0, iflib_sysctl_int_delay, "I", description); 6265 } 6266 6267 struct sx * 6268 iflib_ctx_lock_get(if_ctx_t ctx) 6269 { 6270 6271 return (&ctx->ifc_ctx_sx); 6272 } 6273 6274 static int 6275 iflib_msix_init(if_ctx_t ctx) 6276 { 6277 device_t dev = ctx->ifc_dev; 6278 if_shared_ctx_t sctx = ctx->ifc_sctx; 6279 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6280 int admincnt, bar, err, iflib_num_rx_queues, iflib_num_tx_queues; 6281 int msgs, queuemsgs, queues, rx_queues, tx_queues, vectors; 6282 6283 iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; 6284 iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; 6285 6286 if (bootverbose) 6287 device_printf(dev, "msix_init qsets capped at %d\n", 6288 imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); 6289 6290 /* Override by tuneable */ 6291 if (scctx->isc_disable_msix) 6292 goto msi; 6293 6294 /* First try MSI-X */ 6295 if ((msgs = pci_msix_count(dev)) == 0) { 6296 if (bootverbose) 6297 device_printf(dev, "MSI-X not supported or disabled\n"); 6298 goto msi; 6299 } 6300 6301 bar = ctx->ifc_softc_ctx.isc_msix_bar; 6302 /* 6303 * bar == -1 => "trust me I know what I'm doing" 6304 * Some drivers are for hardware that is so shoddily 6305 * documented that no one knows which bars are which 6306 * so the developer has to map all bars. This hack 6307 * allows shoddy garbage to use MSI-X in this framework. 6308 */ 6309 if (bar != -1) { 6310 ctx->ifc_msix_mem = bus_alloc_resource_any(dev, 6311 SYS_RES_MEMORY, &bar, RF_ACTIVE); 6312 if (ctx->ifc_msix_mem == NULL) { 6313 device_printf(dev, "Unable to map MSI-X table\n"); 6314 goto msi; 6315 } 6316 } 6317 6318 admincnt = sctx->isc_admin_intrcnt; 6319 #if IFLIB_DEBUG 6320 /* use only 1 qset in debug mode */ 6321 queuemsgs = min(msgs - admincnt, 1); 6322 #else 6323 queuemsgs = msgs - admincnt; 6324 #endif 6325 #ifdef RSS 6326 queues = imin(queuemsgs, rss_getnumbuckets()); 6327 #else 6328 queues = queuemsgs; 6329 #endif 6330 queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); 6331 if (bootverbose) 6332 device_printf(dev, 6333 "intr CPUs: %d queue msgs: %d admincnt: %d\n", 6334 CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); 6335 #ifdef RSS 6336 /* If we're doing RSS, clamp at the number of RSS buckets */ 6337 if (queues > rss_getnumbuckets()) 6338 queues = rss_getnumbuckets(); 6339 #endif 6340 if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) 6341 rx_queues = iflib_num_rx_queues; 6342 else 6343 rx_queues = queues; 6344 6345 if (rx_queues > scctx->isc_nrxqsets) 6346 rx_queues = scctx->isc_nrxqsets; 6347 6348 /* 6349 * We want this to be all logical CPUs by default 6350 */ 6351 if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) 6352 tx_queues = iflib_num_tx_queues; 6353 else 6354 tx_queues = mp_ncpus; 6355 6356 if (tx_queues > scctx->isc_ntxqsets) 6357 tx_queues = scctx->isc_ntxqsets; 6358 6359 if (ctx->ifc_sysctl_qs_eq_override == 0) { 6360 #ifdef INVARIANTS 6361 if (tx_queues != rx_queues) 6362 device_printf(dev, 6363 "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", 6364 min(rx_queues, tx_queues), min(rx_queues, tx_queues)); 6365 #endif 6366 tx_queues = min(rx_queues, tx_queues); 6367 rx_queues = min(rx_queues, tx_queues); 6368 } 6369 6370 vectors = rx_queues + admincnt; 6371 if (msgs < vectors) { 6372 device_printf(dev, 6373 "insufficient number of MSI-X vectors " 6374 "(supported %d, need %d)\n", msgs, vectors); 6375 goto msi; 6376 } 6377 6378 device_printf(dev, "Using %d RX queues %d TX queues\n", rx_queues, 6379 tx_queues); 6380 msgs = vectors; 6381 if ((err = pci_alloc_msix(dev, &vectors)) == 0) { 6382 if (vectors != msgs) { 6383 device_printf(dev, 6384 "Unable to allocate sufficient MSI-X vectors " 6385 "(got %d, need %d)\n", vectors, msgs); 6386 pci_release_msi(dev); 6387 if (bar != -1) { 6388 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6389 ctx->ifc_msix_mem); 6390 ctx->ifc_msix_mem = NULL; 6391 } 6392 goto msi; 6393 } 6394 device_printf(dev, "Using MSI-X interrupts with %d vectors\n", 6395 vectors); 6396 scctx->isc_vectors = vectors; 6397 scctx->isc_nrxqsets = rx_queues; 6398 scctx->isc_ntxqsets = tx_queues; 6399 scctx->isc_intr = IFLIB_INTR_MSIX; 6400 6401 return (vectors); 6402 } else { 6403 device_printf(dev, 6404 "failed to allocate %d MSI-X vectors, err: %d\n", vectors, 6405 err); 6406 if (bar != -1) { 6407 bus_release_resource(dev, SYS_RES_MEMORY, bar, 6408 ctx->ifc_msix_mem); 6409 ctx->ifc_msix_mem = NULL; 6410 } 6411 } 6412 6413 msi: 6414 vectors = pci_msi_count(dev); 6415 scctx->isc_nrxqsets = 1; 6416 scctx->isc_ntxqsets = 1; 6417 scctx->isc_vectors = vectors; 6418 if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0) { 6419 device_printf(dev,"Using an MSI interrupt\n"); 6420 scctx->isc_intr = IFLIB_INTR_MSI; 6421 } else { 6422 scctx->isc_vectors = 1; 6423 device_printf(dev,"Using a Legacy interrupt\n"); 6424 scctx->isc_intr = IFLIB_INTR_LEGACY; 6425 } 6426 6427 return (vectors); 6428 } 6429 6430 static const char *ring_states[] = { "IDLE", "BUSY", "STALLED", "ABDICATED" }; 6431 6432 static int 6433 mp_ring_state_handler(SYSCTL_HANDLER_ARGS) 6434 { 6435 int rc; 6436 uint16_t *state = ((uint16_t *)oidp->oid_arg1); 6437 struct sbuf *sb; 6438 const char *ring_state = "UNKNOWN"; 6439 6440 /* XXX needed ? */ 6441 rc = sysctl_wire_old_buffer(req, 0); 6442 MPASS(rc == 0); 6443 if (rc != 0) 6444 return (rc); 6445 sb = sbuf_new_for_sysctl(NULL, NULL, 80, req); 6446 MPASS(sb != NULL); 6447 if (sb == NULL) 6448 return (ENOMEM); 6449 if (state[3] <= 3) 6450 ring_state = ring_states[state[3]]; 6451 6452 sbuf_printf(sb, "pidx_head: %04hd pidx_tail: %04hd cidx: %04hd state: %s", 6453 state[0], state[1], state[2], ring_state); 6454 rc = sbuf_finish(sb); 6455 sbuf_delete(sb); 6456 return(rc); 6457 } 6458 6459 enum iflib_ndesc_handler { 6460 IFLIB_NTXD_HANDLER, 6461 IFLIB_NRXD_HANDLER, 6462 }; 6463 6464 static int 6465 mp_ndesc_handler(SYSCTL_HANDLER_ARGS) 6466 { 6467 if_ctx_t ctx = (void *)arg1; 6468 enum iflib_ndesc_handler type = arg2; 6469 char buf[256] = {0}; 6470 qidx_t *ndesc; 6471 char *p, *next; 6472 int nqs, rc, i; 6473 6474 nqs = 8; 6475 switch(type) { 6476 case IFLIB_NTXD_HANDLER: 6477 ndesc = ctx->ifc_sysctl_ntxds; 6478 if (ctx->ifc_sctx) 6479 nqs = ctx->ifc_sctx->isc_ntxqs; 6480 break; 6481 case IFLIB_NRXD_HANDLER: 6482 ndesc = ctx->ifc_sysctl_nrxds; 6483 if (ctx->ifc_sctx) 6484 nqs = ctx->ifc_sctx->isc_nrxqs; 6485 break; 6486 default: 6487 printf("%s: unhandled type\n", __func__); 6488 return (EINVAL); 6489 } 6490 if (nqs == 0) 6491 nqs = 8; 6492 6493 for (i=0; i<8; i++) { 6494 if (i >= nqs) 6495 break; 6496 if (i) 6497 strcat(buf, ","); 6498 sprintf(strchr(buf, 0), "%d", ndesc[i]); 6499 } 6500 6501 rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); 6502 if (rc || req->newptr == NULL) 6503 return rc; 6504 6505 for (i = 0, next = buf, p = strsep(&next, " ,"); i < 8 && p; 6506 i++, p = strsep(&next, " ,")) { 6507 ndesc[i] = strtoul(p, NULL, 10); 6508 } 6509 6510 return(rc); 6511 } 6512 6513 #define NAME_BUFLEN 32 6514 static void 6515 iflib_add_device_sysctl_pre(if_ctx_t ctx) 6516 { 6517 device_t dev = iflib_get_dev(ctx); 6518 struct sysctl_oid_list *child, *oid_list; 6519 struct sysctl_ctx_list *ctx_list; 6520 struct sysctl_oid *node; 6521 6522 ctx_list = device_get_sysctl_ctx(dev); 6523 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 6524 ctx->ifc_sysctl_node = node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, "iflib", 6525 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "IFLIB fields"); 6526 oid_list = SYSCTL_CHILDREN(node); 6527 6528 SYSCTL_ADD_CONST_STRING(ctx_list, oid_list, OID_AUTO, "driver_version", 6529 CTLFLAG_RD, ctx->ifc_sctx->isc_driver_version, 6530 "driver version"); 6531 6532 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", 6533 CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, 6534 "# of txqs to use, 0 => use default #"); 6535 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", 6536 CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, 6537 "# of rxqs to use, 0 => use default #"); 6538 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", 6539 CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, 6540 "permit #txq != #rxq"); 6541 SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", 6542 CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, 6543 "disable MSI-X (default 0)"); 6544 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", 6545 CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, 6546 "set the RX budget"); 6547 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "tx_abdicate", 6548 CTLFLAG_RWTUN, &ctx->ifc_sysctl_tx_abdicate, 0, 6549 "cause TX to abdicate instead of running to completion"); 6550 ctx->ifc_sysctl_core_offset = CORE_OFFSET_UNSPECIFIED; 6551 SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "core_offset", 6552 CTLFLAG_RDTUN, &ctx->ifc_sysctl_core_offset, 0, 6553 "offset to start using cores at"); 6554 SYSCTL_ADD_U8(ctx_list, oid_list, OID_AUTO, "separate_txrx", 6555 CTLFLAG_RDTUN, &ctx->ifc_sysctl_separate_txrx, 0, 6556 "use separate cores for TX and RX"); 6557 6558 /* XXX change for per-queue sizes */ 6559 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", 6560 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6561 IFLIB_NTXD_HANDLER, mp_ndesc_handler, "A", 6562 "list of # of TX descriptors to use, 0 = use default #"); 6563 SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", 6564 CTLTYPE_STRING | CTLFLAG_RWTUN | CTLFLAG_NEEDGIANT, ctx, 6565 IFLIB_NRXD_HANDLER, mp_ndesc_handler, "A", 6566 "list of # of RX descriptors to use, 0 = use default #"); 6567 } 6568 6569 static void 6570 iflib_add_device_sysctl_post(if_ctx_t ctx) 6571 { 6572 if_shared_ctx_t sctx = ctx->ifc_sctx; 6573 if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; 6574 device_t dev = iflib_get_dev(ctx); 6575 struct sysctl_oid_list *child; 6576 struct sysctl_ctx_list *ctx_list; 6577 iflib_fl_t fl; 6578 iflib_txq_t txq; 6579 iflib_rxq_t rxq; 6580 int i, j; 6581 char namebuf[NAME_BUFLEN]; 6582 char *qfmt; 6583 struct sysctl_oid *queue_node, *fl_node, *node; 6584 struct sysctl_oid_list *queue_list, *fl_list; 6585 ctx_list = device_get_sysctl_ctx(dev); 6586 6587 node = ctx->ifc_sysctl_node; 6588 child = SYSCTL_CHILDREN(node); 6589 6590 if (scctx->isc_ntxqsets > 100) 6591 qfmt = "txq%03d"; 6592 else if (scctx->isc_ntxqsets > 10) 6593 qfmt = "txq%02d"; 6594 else 6595 qfmt = "txq%d"; 6596 for (i = 0, txq = ctx->ifc_txqs; i < scctx->isc_ntxqsets; i++, txq++) { 6597 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6598 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6599 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6600 queue_list = SYSCTL_CHILDREN(queue_node); 6601 #if MEMORY_LOGGING 6602 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_dequeued", 6603 CTLFLAG_RD, 6604 &txq->ift_dequeued, "total mbufs freed"); 6605 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_enqueued", 6606 CTLFLAG_RD, 6607 &txq->ift_enqueued, "total mbufs enqueued"); 6608 #endif 6609 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag", 6610 CTLFLAG_RD, 6611 &txq->ift_mbuf_defrag, "# of times m_defrag was called"); 6612 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "m_pullups", 6613 CTLFLAG_RD, 6614 &txq->ift_pullups, "# of times m_pullup was called"); 6615 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "mbuf_defrag_failed", 6616 CTLFLAG_RD, 6617 &txq->ift_mbuf_defrag_failed, "# of times m_defrag failed"); 6618 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_desc_avail", 6619 CTLFLAG_RD, 6620 &txq->ift_no_desc_avail, "# of times no descriptors were available"); 6621 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "tx_map_failed", 6622 CTLFLAG_RD, 6623 &txq->ift_map_failed, "# of times DMA map failed"); 6624 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txd_encap_efbig", 6625 CTLFLAG_RD, 6626 &txq->ift_txd_encap_efbig, "# of times txd_encap returned EFBIG"); 6627 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "no_tx_dma_setup", 6628 CTLFLAG_RD, 6629 &txq->ift_no_tx_dma_setup, "# of times map failed for other than EFBIG"); 6630 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_pidx", 6631 CTLFLAG_RD, 6632 &txq->ift_pidx, 1, "Producer Index"); 6633 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx", 6634 CTLFLAG_RD, 6635 &txq->ift_cidx, 1, "Consumer Index"); 6636 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_cidx_processed", 6637 CTLFLAG_RD, 6638 &txq->ift_cidx_processed, 1, "Consumer Index seen by credit update"); 6639 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", 6640 CTLFLAG_RD, 6641 &txq->ift_in_use, 1, "descriptors in use"); 6642 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", 6643 CTLFLAG_RD, 6644 &txq->ift_processed, "descriptors procesed for clean"); 6645 SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", 6646 CTLFLAG_RD, 6647 &txq->ift_cleaned, "total cleaned"); 6648 SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", 6649 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 6650 __DEVOLATILE(uint64_t *, &txq->ift_br->state), 0, 6651 mp_ring_state_handler, "A", "soft ring state"); 6652 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", 6653 CTLFLAG_RD, &txq->ift_br->enqueues, 6654 "# of enqueues to the mp_ring for this queue"); 6655 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", 6656 CTLFLAG_RD, &txq->ift_br->drops, 6657 "# of drops in the mp_ring for this queue"); 6658 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", 6659 CTLFLAG_RD, &txq->ift_br->starts, 6660 "# of normal consumer starts in the mp_ring for this queue"); 6661 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", 6662 CTLFLAG_RD, &txq->ift_br->stalls, 6663 "# of consumer stalls in the mp_ring for this queue"); 6664 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", 6665 CTLFLAG_RD, &txq->ift_br->restarts, 6666 "# of consumer restarts in the mp_ring for this queue"); 6667 SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", 6668 CTLFLAG_RD, &txq->ift_br->abdications, 6669 "# of consumer abdications in the mp_ring for this queue"); 6670 } 6671 6672 if (scctx->isc_nrxqsets > 100) 6673 qfmt = "rxq%03d"; 6674 else if (scctx->isc_nrxqsets > 10) 6675 qfmt = "rxq%02d"; 6676 else 6677 qfmt = "rxq%d"; 6678 for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { 6679 snprintf(namebuf, NAME_BUFLEN, qfmt, i); 6680 queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, 6681 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name"); 6682 queue_list = SYSCTL_CHILDREN(queue_node); 6683 if (sctx->isc_flags & IFLIB_HAS_RXCQ) { 6684 SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", 6685 CTLFLAG_RD, 6686 &rxq->ifr_cq_cidx, 1, "Consumer Index"); 6687 } 6688 6689 for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { 6690 snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); 6691 fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, 6692 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist Name"); 6693 fl_list = SYSCTL_CHILDREN(fl_node); 6694 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", 6695 CTLFLAG_RD, 6696 &fl->ifl_pidx, 1, "Producer Index"); 6697 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "cidx", 6698 CTLFLAG_RD, 6699 &fl->ifl_cidx, 1, "Consumer Index"); 6700 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "credits", 6701 CTLFLAG_RD, 6702 &fl->ifl_credits, 1, "credits available"); 6703 SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "buf_size", 6704 CTLFLAG_RD, 6705 &fl->ifl_buf_size, 1, "buffer size"); 6706 #if MEMORY_LOGGING 6707 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_enqueued", 6708 CTLFLAG_RD, 6709 &fl->ifl_m_enqueued, "mbufs allocated"); 6710 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_m_dequeued", 6711 CTLFLAG_RD, 6712 &fl->ifl_m_dequeued, "mbufs freed"); 6713 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_enqueued", 6714 CTLFLAG_RD, 6715 &fl->ifl_cl_enqueued, "clusters allocated"); 6716 SYSCTL_ADD_QUAD(ctx_list, fl_list, OID_AUTO, "fl_cl_dequeued", 6717 CTLFLAG_RD, 6718 &fl->ifl_cl_dequeued, "clusters freed"); 6719 #endif 6720 6721 } 6722 } 6723 6724 } 6725 6726 void 6727 iflib_request_reset(if_ctx_t ctx) 6728 { 6729 6730 STATE_LOCK(ctx); 6731 ctx->ifc_flags |= IFC_DO_RESET; 6732 STATE_UNLOCK(ctx); 6733 } 6734 6735 #ifndef __NO_STRICT_ALIGNMENT 6736 static struct mbuf * 6737 iflib_fixup_rx(struct mbuf *m) 6738 { 6739 struct mbuf *n; 6740 6741 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 6742 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 6743 m->m_data += ETHER_HDR_LEN; 6744 n = m; 6745 } else { 6746 MGETHDR(n, M_NOWAIT, MT_DATA); 6747 if (n == NULL) { 6748 m_freem(m); 6749 return (NULL); 6750 } 6751 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 6752 m->m_data += ETHER_HDR_LEN; 6753 m->m_len -= ETHER_HDR_LEN; 6754 n->m_len = ETHER_HDR_LEN; 6755 M_MOVE_PKTHDR(n, m); 6756 n->m_next = m; 6757 } 6758 return (n); 6759 } 6760 #endif 6761 6762 #ifdef DEBUGNET 6763 static void 6764 iflib_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 6765 { 6766 if_ctx_t ctx; 6767 6768 ctx = if_getsoftc(ifp); 6769 CTX_LOCK(ctx); 6770 *nrxr = NRXQSETS(ctx); 6771 *ncl = ctx->ifc_rxqs[0].ifr_fl->ifl_size; 6772 *clsize = ctx->ifc_rxqs[0].ifr_fl->ifl_buf_size; 6773 CTX_UNLOCK(ctx); 6774 } 6775 6776 static void 6777 iflib_debugnet_event(if_t ifp, enum debugnet_ev event) 6778 { 6779 if_ctx_t ctx; 6780 if_softc_ctx_t scctx; 6781 iflib_fl_t fl; 6782 iflib_rxq_t rxq; 6783 int i, j; 6784 6785 ctx = if_getsoftc(ifp); 6786 scctx = &ctx->ifc_softc_ctx; 6787 6788 switch (event) { 6789 case DEBUGNET_START: 6790 for (i = 0; i < scctx->isc_nrxqsets; i++) { 6791 rxq = &ctx->ifc_rxqs[i]; 6792 for (j = 0; j < rxq->ifr_nfl; j++) { 6793 fl = rxq->ifr_fl; 6794 fl->ifl_zone = m_getzone(fl->ifl_buf_size); 6795 } 6796 } 6797 iflib_no_tx_batch = 1; 6798 break; 6799 default: 6800 break; 6801 } 6802 } 6803 6804 static int 6805 iflib_debugnet_transmit(if_t ifp, struct mbuf *m) 6806 { 6807 if_ctx_t ctx; 6808 iflib_txq_t txq; 6809 int error; 6810 6811 ctx = if_getsoftc(ifp); 6812 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6813 IFF_DRV_RUNNING) 6814 return (EBUSY); 6815 6816 txq = &ctx->ifc_txqs[0]; 6817 error = iflib_encap(txq, &m); 6818 if (error == 0) 6819 (void)iflib_txd_db_check(ctx, txq, true, txq->ift_in_use); 6820 return (error); 6821 } 6822 6823 static int 6824 iflib_debugnet_poll(if_t ifp, int count) 6825 { 6826 struct epoch_tracker et; 6827 if_ctx_t ctx; 6828 if_softc_ctx_t scctx; 6829 iflib_txq_t txq; 6830 int i; 6831 6832 ctx = if_getsoftc(ifp); 6833 scctx = &ctx->ifc_softc_ctx; 6834 6835 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 6836 IFF_DRV_RUNNING) 6837 return (EBUSY); 6838 6839 txq = &ctx->ifc_txqs[0]; 6840 (void)iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); 6841 6842 NET_EPOCH_ENTER(et); 6843 for (i = 0; i < scctx->isc_nrxqsets; i++) 6844 (void)iflib_rxeof(&ctx->ifc_rxqs[i], 16 /* XXX */); 6845 NET_EPOCH_EXIT(et); 6846 return (0); 6847 } 6848 #endif /* DEBUGNET */ 6849