1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef MLX5_ABI_USER_H 38 #define MLX5_ABI_USER_H 39 40 #ifdef _KERNEL 41 #include <linux/types.h> 42 #else 43 #include <infiniband/types.h> 44 #endif 45 46 enum { 47 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 48 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 49 }; 50 51 enum { 52 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 53 }; 54 55 enum { 56 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 57 }; 58 59 /* Increment this value if any changes that break userspace ABI 60 * compatibility are made. 61 */ 62 #define MLX5_IB_UVERBS_ABI_VERSION 1 63 64 /* Make sure that all structs defined in this file remain laid out so 65 * that they pack the same way on 32-bit and 64-bit architectures (to 66 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 67 * In particular do not use pointer types -- pass pointers in __u64 68 * instead. 69 */ 70 71 struct mlx5_ib_alloc_ucontext_req { 72 __u32 total_num_uuars; 73 __u32 num_low_latency_uuars; 74 }; 75 76 struct mlx5_ib_alloc_ucontext_req_v2 { 77 __u32 total_num_uuars; 78 __u32 num_low_latency_uuars; 79 __u32 flags; 80 __u32 comp_mask; 81 __u8 max_cqe_version; 82 __u8 reserved0; 83 __u16 reserved1; 84 __u32 reserved2; 85 }; 86 87 enum mlx5_ib_alloc_ucontext_resp_mask { 88 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 89 }; 90 91 enum mlx5_user_cmds_supp_uhw { 92 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 93 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 94 }; 95 96 struct mlx5_ib_alloc_ucontext_resp { 97 __u32 qp_tab_size; 98 __u32 bf_reg_size; 99 __u32 tot_uuars; 100 __u32 cache_line_size; 101 __u16 max_sq_desc_sz; 102 __u16 max_rq_desc_sz; 103 __u32 max_send_wqebb; 104 __u32 max_recv_wr; 105 __u32 max_srq_recv_wr; 106 __u16 num_ports; 107 __u16 reserved1; 108 __u32 comp_mask; 109 __u32 response_length; 110 __u8 cqe_version; 111 __u8 cmds_supp_uhw; 112 __u16 reserved2; 113 __u64 hca_core_clock_offset; 114 }; 115 116 struct mlx5_ib_alloc_pd_resp { 117 __u32 pdn; 118 }; 119 120 struct mlx5_ib_tso_caps { 121 __u32 max_tso; /* Maximum tso payload size in bytes */ 122 123 /* Corresponding bit will be set if qp type from 124 * 'enum ib_qp_type' is supported, e.g. 125 * supported_qpts |= 1 << IB_QPT_UD 126 */ 127 __u32 supported_qpts; 128 }; 129 130 struct mlx5_ib_rss_caps { 131 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 132 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 133 __u8 reserved[7]; 134 }; 135 136 struct mlx5_ib_query_device_resp { 137 __u32 comp_mask; 138 __u32 response_length; 139 struct mlx5_ib_tso_caps tso_caps; 140 struct mlx5_ib_rss_caps rss_caps; 141 }; 142 143 struct mlx5_ib_create_cq { 144 __u64 buf_addr; 145 __u64 db_addr; 146 __u32 cqe_size; 147 __u32 reserved; /* explicit padding (optional on i386) */ 148 }; 149 150 struct mlx5_ib_create_cq_resp { 151 __u32 cqn; 152 __u32 reserved; 153 }; 154 155 struct mlx5_ib_resize_cq { 156 __u64 buf_addr; 157 __u16 cqe_size; 158 __u16 reserved0; 159 __u32 reserved1; 160 }; 161 162 struct mlx5_ib_create_srq { 163 __u64 buf_addr; 164 __u64 db_addr; 165 __u32 flags; 166 __u32 reserved0; /* explicit padding (optional on i386) */ 167 __u32 uidx; 168 __u32 reserved1; 169 }; 170 171 struct mlx5_ib_create_srq_resp { 172 __u32 srqn; 173 __u32 reserved; 174 }; 175 176 struct mlx5_ib_create_qp { 177 __u64 buf_addr; 178 __u64 db_addr; 179 __u32 sq_wqe_count; 180 __u32 rq_wqe_count; 181 __u32 rq_wqe_shift; 182 __u32 flags; 183 __u32 uidx; 184 __u32 reserved0; 185 __u64 sq_buf_addr; 186 }; 187 188 /* RX Hash function flags */ 189 enum mlx5_rx_hash_function_flags { 190 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 191 }; 192 193 /* 194 * RX Hash flags, these flags allows to set which incoming packet's field should 195 * participates in RX Hash. Each flag represent certain packet's field, 196 * when the flag is set the field that is represented by the flag will 197 * participate in RX Hash calculation. 198 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 199 * and *TCP and *UDP flags can't be enabled together on the same QP. 200 */ 201 enum mlx5_rx_hash_fields { 202 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 203 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 204 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 205 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 206 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 207 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 208 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 209 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 210 }; 211 212 struct mlx5_ib_create_qp_rss { 213 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 214 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 215 __u8 rx_key_len; /* valid only for Toeplitz */ 216 __u8 reserved[6]; 217 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 218 __u32 comp_mask; 219 __u32 reserved1; 220 }; 221 222 struct mlx5_ib_create_qp_resp { 223 __u32 uuar_index; 224 }; 225 226 struct mlx5_ib_alloc_mw { 227 __u32 comp_mask; 228 __u8 num_klms; 229 __u8 reserved1; 230 __u16 reserved2; 231 }; 232 233 struct mlx5_ib_create_wq { 234 __u64 buf_addr; 235 __u64 db_addr; 236 __u32 rq_wqe_count; 237 __u32 rq_wqe_shift; 238 __u32 user_index; 239 __u32 flags; 240 __u32 comp_mask; 241 __u32 reserved; 242 }; 243 244 struct mlx5_ib_create_ah_resp { 245 __u32 response_length; 246 __u8 dmac[ETH_ALEN]; 247 __u8 reserved[6]; 248 }; 249 250 struct mlx5_ib_create_wq_resp { 251 __u32 response_length; 252 __u32 reserved; 253 }; 254 255 struct mlx5_ib_create_rwq_ind_tbl_resp { 256 __u32 response_length; 257 __u32 reserved; 258 }; 259 260 struct mlx5_ib_modify_wq { 261 __u32 comp_mask; 262 __u32 reserved; 263 }; 264 #endif /* MLX5_ABI_USER_H */ 265