1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_ABI_USER_H 34 #define MLX5_ABI_USER_H 35 36 #ifdef _KERNEL 37 #include <linux/types.h> 38 #else 39 #include <infiniband/types.h> 40 #endif 41 42 enum { 43 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 44 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 45 }; 46 47 enum { 48 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 49 }; 50 51 enum { 52 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 53 }; 54 55 /* Increment this value if any changes that break userspace ABI 56 * compatibility are made. 57 */ 58 #define MLX5_IB_UVERBS_ABI_VERSION 1 59 60 /* Make sure that all structs defined in this file remain laid out so 61 * that they pack the same way on 32-bit and 64-bit architectures (to 62 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 63 * In particular do not use pointer types -- pass pointers in __u64 64 * instead. 65 */ 66 67 struct mlx5_ib_alloc_ucontext_req { 68 __u32 total_num_uuars; 69 __u32 num_low_latency_uuars; 70 }; 71 72 struct mlx5_ib_alloc_ucontext_req_v2 { 73 __u32 total_num_uuars; 74 __u32 num_low_latency_uuars; 75 __u32 flags; 76 __u32 comp_mask; 77 __u8 max_cqe_version; 78 __u8 reserved0; 79 __u16 reserved1; 80 __u32 reserved2; 81 }; 82 83 enum mlx5_ib_alloc_ucontext_resp_mask { 84 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 85 }; 86 87 enum mlx5_user_cmds_supp_uhw { 88 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 89 }; 90 91 struct mlx5_ib_alloc_ucontext_resp { 92 __u32 qp_tab_size; 93 __u32 bf_reg_size; 94 __u32 tot_uuars; 95 __u32 cache_line_size; 96 __u16 max_sq_desc_sz; 97 __u16 max_rq_desc_sz; 98 __u32 max_send_wqebb; 99 __u32 max_recv_wr; 100 __u32 max_srq_recv_wr; 101 __u16 num_ports; 102 __u16 reserved1; 103 __u32 comp_mask; 104 __u32 response_length; 105 __u8 cqe_version; 106 __u8 cmds_supp_uhw; 107 __u16 reserved2; 108 __u64 hca_core_clock_offset; 109 }; 110 111 struct mlx5_ib_alloc_pd_resp { 112 __u32 pdn; 113 }; 114 115 struct mlx5_ib_tso_caps { 116 __u32 max_tso; /* Maximum tso payload size in bytes */ 117 118 /* Corresponding bit will be set if qp type from 119 * 'enum ib_qp_type' is supported, e.g. 120 * supported_qpts |= 1 << IB_QPT_UD 121 */ 122 __u32 supported_qpts; 123 }; 124 125 struct mlx5_ib_rss_caps { 126 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 127 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 128 __u8 reserved[7]; 129 }; 130 131 struct mlx5_ib_query_device_resp { 132 __u32 comp_mask; 133 __u32 response_length; 134 struct mlx5_ib_tso_caps tso_caps; 135 struct mlx5_ib_rss_caps rss_caps; 136 }; 137 138 struct mlx5_ib_create_cq { 139 __u64 buf_addr; 140 __u64 db_addr; 141 __u32 cqe_size; 142 __u32 reserved; /* explicit padding (optional on i386) */ 143 }; 144 145 struct mlx5_ib_create_cq_resp { 146 __u32 cqn; 147 __u32 reserved; 148 }; 149 150 struct mlx5_ib_resize_cq { 151 __u64 buf_addr; 152 __u16 cqe_size; 153 __u16 reserved0; 154 __u32 reserved1; 155 }; 156 157 struct mlx5_ib_create_srq { 158 __u64 buf_addr; 159 __u64 db_addr; 160 __u32 flags; 161 __u32 reserved0; /* explicit padding (optional on i386) */ 162 __u32 uidx; 163 __u32 reserved1; 164 }; 165 166 struct mlx5_ib_create_srq_resp { 167 __u32 srqn; 168 __u32 reserved; 169 }; 170 171 struct mlx5_ib_create_qp { 172 __u64 buf_addr; 173 __u64 db_addr; 174 __u32 sq_wqe_count; 175 __u32 rq_wqe_count; 176 __u32 rq_wqe_shift; 177 __u32 flags; 178 __u32 uidx; 179 __u32 reserved0; 180 __u64 sq_buf_addr; 181 }; 182 183 /* RX Hash function flags */ 184 enum mlx5_rx_hash_function_flags { 185 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 186 }; 187 188 /* 189 * RX Hash flags, these flags allows to set which incoming packet's field should 190 * participates in RX Hash. Each flag represent certain packet's field, 191 * when the flag is set the field that is represented by the flag will 192 * participate in RX Hash calculation. 193 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP 194 * and *TCP and *UDP flags can't be enabled together on the same QP. 195 */ 196 enum mlx5_rx_hash_fields { 197 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 198 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 199 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 200 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 201 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 202 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 203 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 204 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 205 }; 206 207 struct mlx5_ib_create_qp_rss { 208 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */ 209 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */ 210 __u8 rx_key_len; /* valid only for Toeplitz */ 211 __u8 reserved[6]; 212 __u8 rx_hash_key[128]; /* valid only for Toeplitz */ 213 __u32 comp_mask; 214 __u32 reserved1; 215 }; 216 217 struct mlx5_ib_create_qp_resp { 218 __u32 uuar_index; 219 }; 220 221 struct mlx5_ib_alloc_mw { 222 __u32 comp_mask; 223 __u8 num_klms; 224 __u8 reserved1; 225 __u16 reserved2; 226 }; 227 228 struct mlx5_ib_create_wq { 229 __u64 buf_addr; 230 __u64 db_addr; 231 __u32 rq_wqe_count; 232 __u32 rq_wqe_shift; 233 __u32 user_index; 234 __u32 flags; 235 __u32 comp_mask; 236 __u32 reserved; 237 }; 238 239 struct mlx5_ib_create_wq_resp { 240 __u32 response_length; 241 __u32 reserved; 242 }; 243 244 struct mlx5_ib_create_rwq_ind_tbl_resp { 245 __u32 response_length; 246 __u32 reserved; 247 }; 248 249 struct mlx5_ib_modify_wq { 250 __u32 comp_mask; 251 __u32 reserved; 252 }; 253 #endif /* MLX5_ABI_USER_H */ 254