1 /*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by TooLs GmbH. 17 * 4. The name of TooLs GmbH may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 2001 Benno Rice 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57 #include <sys/cdefs.h> 58 __FBSDID("$FreeBSD$"); 59 60 #include "opt_ddb.h" 61 #include "opt_kstack_pages.h" 62 #include "opt_platform.h" 63 64 #include <sys/param.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/bio.h> 68 #include <sys/buf.h> 69 #include <sys/bus.h> 70 #include <sys/cons.h> 71 #include <sys/cpu.h> 72 #include <sys/eventhandler.h> 73 #include <sys/exec.h> 74 #include <sys/imgact.h> 75 #include <sys/kdb.h> 76 #include <sys/kernel.h> 77 #include <sys/ktr.h> 78 #include <sys/linker.h> 79 #include <sys/lock.h> 80 #include <sys/malloc.h> 81 #include <sys/mbuf.h> 82 #include <sys/msgbuf.h> 83 #include <sys/mutex.h> 84 #include <sys/ptrace.h> 85 #include <sys/reboot.h> 86 #include <sys/rwlock.h> 87 #include <sys/signalvar.h> 88 #include <sys/syscallsubr.h> 89 #include <sys/sysctl.h> 90 #include <sys/sysent.h> 91 #include <sys/sysproto.h> 92 #include <sys/ucontext.h> 93 #include <sys/uio.h> 94 #include <sys/vmmeter.h> 95 #include <sys/vnode.h> 96 97 #include <net/netisr.h> 98 99 #include <vm/vm.h> 100 #include <vm/vm_extern.h> 101 #include <vm/vm_kern.h> 102 #include <vm/vm_page.h> 103 #include <vm/vm_map.h> 104 #include <vm/vm_object.h> 105 #include <vm/vm_pager.h> 106 107 #include <machine/altivec.h> 108 #ifndef __powerpc64__ 109 #include <machine/bat.h> 110 #endif 111 #include <machine/cpu.h> 112 #include <machine/elf.h> 113 #include <machine/fpu.h> 114 #include <machine/hid.h> 115 #include <machine/kdb.h> 116 #include <machine/md_var.h> 117 #include <machine/metadata.h> 118 #include <machine/mmuvar.h> 119 #include <machine/pcb.h> 120 #include <machine/reg.h> 121 #include <machine/sigframe.h> 122 #include <machine/spr.h> 123 #include <machine/trap.h> 124 #include <machine/vmparam.h> 125 #include <machine/ofw_machdep.h> 126 127 #include <ddb/ddb.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #ifdef __powerpc64__ 132 #include "mmu_oea64.h" 133 #endif 134 135 #ifndef __powerpc64__ 136 struct bat battable[16]; 137 #endif 138 139 #ifndef __powerpc64__ 140 /* Bits for running on 64-bit systems in 32-bit mode. */ 141 extern void *testppc64, *testppc64size; 142 extern void *restorebridge, *restorebridgesize; 143 extern void *rfid_patch, *rfi_patch1, *rfi_patch2; 144 extern void *trapcode64; 145 146 extern Elf_Addr _GLOBAL_OFFSET_TABLE_[]; 147 #endif 148 149 extern void *rstcode, *rstcodeend; 150 extern void *trapcode, *trapcodeend; 151 extern void *generictrap, *generictrap64; 152 extern void *alitrap, *aliend; 153 extern void *dsitrap, *dsiend; 154 extern void *decrint, *decrsize; 155 extern void *extint, *extsize; 156 extern void *dblow, *dbend; 157 extern void *imisstrap, *imisssize; 158 extern void *dlmisstrap, *dlmisssize; 159 extern void *dsmisstrap, *dsmisssize; 160 161 extern void *ap_pcpu; 162 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); 163 164 void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, 165 void *mdp, uint32_t mdp_cookie); 166 void aim_cpu_init(vm_offset_t toc); 167 168 void 169 aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp, 170 uint32_t mdp_cookie) 171 { 172 register_t scratch; 173 174 /* 175 * If running from an FDT, make sure we are in real mode to avoid 176 * tromping on firmware page tables. Everything in the kernel assumes 177 * 1:1 mappings out of firmware, so this won't break anything not 178 * already broken. This doesn't work if there is live OF, since OF 179 * may internally use non-1:1 mappings. 180 */ 181 if (ofentry == 0) 182 mtmsr(mfmsr() & ~(PSL_IR | PSL_DR)); 183 184 #ifdef __powerpc64__ 185 /* 186 * If in real mode, relocate to high memory so that the kernel 187 * can execute from the direct map. 188 */ 189 if (!(mfmsr() & PSL_DR) && 190 (vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS) 191 __restartkernel(fdt, 0, ofentry, mdp, mdp_cookie, 192 DMAP_BASE_ADDRESS, mfmsr()); 193 #endif 194 195 /* Various very early CPU fix ups */ 196 switch (mfpvr() >> 16) { 197 /* 198 * PowerPC 970 CPUs have a misfeature requested by Apple that 199 * makes them pretend they have a 32-byte cacheline. Turn this 200 * off before we measure the cacheline size. 201 */ 202 case IBM970: 203 case IBM970FX: 204 case IBM970MP: 205 case IBM970GX: 206 scratch = mfspr(SPR_HID5); 207 scratch &= ~HID5_970_DCBZ_SIZE_HI; 208 mtspr(SPR_HID5, scratch); 209 break; 210 #ifdef __powerpc64__ 211 case IBMPOWER7: 212 case IBMPOWER7PLUS: 213 case IBMPOWER8: 214 case IBMPOWER8E: 215 /* XXX: get from ibm,slb-size in device tree */ 216 n_slbs = 32; 217 break; 218 #endif 219 } 220 } 221 222 void 223 aim_cpu_init(vm_offset_t toc) 224 { 225 size_t trap_offset, trapsize; 226 vm_offset_t trap; 227 register_t msr; 228 uint8_t *cache_check; 229 int cacheline_warn; 230 #ifndef __powerpc64__ 231 register_t scratch; 232 int ppc64; 233 #endif 234 235 trap_offset = 0; 236 cacheline_warn = 0; 237 238 /* General setup for AIM CPUs */ 239 psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 240 241 #ifdef __powerpc64__ 242 psl_kernset |= PSL_SF; 243 if (mfmsr() & PSL_HV) 244 psl_kernset |= PSL_HV; 245 #endif 246 psl_userset = psl_kernset | PSL_PR; 247 #ifdef __powerpc64__ 248 psl_userset32 = psl_userset & ~PSL_SF; 249 #endif 250 251 /* Bits that users aren't allowed to change */ 252 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 253 /* 254 * Mask bits from the SRR1 that aren't really the MSR: 255 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) 256 */ 257 psl_userstatic &= ~0x783f0000UL; 258 259 /* 260 * Initialize the interrupt tables and figure out our cache line 261 * size and whether or not we need the 64-bit bridge code. 262 */ 263 264 /* 265 * Disable translation in case the vector area hasn't been 266 * mapped (G5). Note that no OFW calls can be made until 267 * translation is re-enabled. 268 */ 269 270 msr = mfmsr(); 271 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); 272 273 /* 274 * Measure the cacheline size using dcbz 275 * 276 * Use EXC_PGM as a playground. We are about to overwrite it 277 * anyway, we know it exists, and we know it is cache-aligned. 278 */ 279 280 cache_check = (void *)EXC_PGM; 281 282 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++) 283 cache_check[cacheline_size] = 0xff; 284 285 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory"); 286 287 /* Find the first byte dcbz did not zero to get the cache line size */ 288 for (cacheline_size = 0; cacheline_size < 0x100 && 289 cache_check[cacheline_size] == 0; cacheline_size++); 290 291 /* Work around psim bug */ 292 if (cacheline_size == 0) { 293 cacheline_warn = 1; 294 cacheline_size = 32; 295 } 296 297 #ifndef __powerpc64__ 298 /* 299 * Figure out whether we need to use the 64 bit PMAP. This works by 300 * executing an instruction that is only legal on 64-bit PPC (mtmsrd), 301 * and setting ppc64 = 0 if that causes a trap. 302 */ 303 304 ppc64 = 1; 305 306 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size); 307 __syncicache((void *)EXC_PGM, (size_t)&testppc64size); 308 309 __asm __volatile("\ 310 mfmsr %0; \ 311 mtsprg2 %1; \ 312 \ 313 mtmsrd %0; \ 314 mfsprg2 %1;" 315 : "=r"(scratch), "=r"(ppc64)); 316 317 if (ppc64) 318 cpu_features |= PPC_FEATURE_64; 319 320 /* 321 * Now copy restorebridge into all the handlers, if necessary, 322 * and set up the trap tables. 323 */ 324 325 if (cpu_features & PPC_FEATURE_64) { 326 /* Patch the two instances of rfi -> rfid */ 327 bcopy(&rfid_patch,&rfi_patch1,4); 328 #ifdef KDB 329 /* rfi_patch2 is at the end of dbleave */ 330 bcopy(&rfid_patch,&rfi_patch2,4); 331 #endif 332 } 333 #else /* powerpc64 */ 334 cpu_features |= PPC_FEATURE_64; 335 #endif 336 337 trapsize = (size_t)&trapcodeend - (size_t)&trapcode; 338 339 /* 340 * Copy generic handler into every possible trap. Special cases will get 341 * different ones in a minute. 342 */ 343 for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20) 344 bcopy(&trapcode, (void *)trap, trapsize); 345 346 #ifndef __powerpc64__ 347 if (cpu_features & PPC_FEATURE_64) { 348 /* 349 * Copy a code snippet to restore 32-bit bridge mode 350 * to the top of every non-generic trap handler 351 */ 352 353 trap_offset += (size_t)&restorebridgesize; 354 bcopy(&restorebridge, (void *)EXC_RST, trap_offset); 355 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset); 356 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset); 357 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset); 358 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset); 359 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset); 360 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset); 361 } 362 #endif 363 364 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend - 365 (size_t)&rstcode); 366 367 #ifdef KDB 368 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend - 369 (size_t)&dblow); 370 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend - 371 (size_t)&dblow); 372 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend - 373 (size_t)&dblow); 374 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend - 375 (size_t)&dblow); 376 #endif 377 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend - 378 (size_t)&alitrap); 379 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend - 380 (size_t)&dsitrap); 381 382 #ifdef __powerpc64__ 383 /* Set TOC base so that the interrupt code can get at it */ 384 *((void **)TRAP_GENTRAP) = &generictrap; 385 *((register_t *)TRAP_TOCBASE) = toc; 386 #else 387 /* Set branch address for trap code */ 388 if (cpu_features & PPC_FEATURE_64) 389 *((void **)TRAP_GENTRAP) = &generictrap64; 390 else 391 *((void **)TRAP_GENTRAP) = &generictrap; 392 *((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_; 393 394 /* G2-specific TLB miss helper handlers */ 395 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); 396 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); 397 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 398 #endif 399 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 400 401 /* 402 * Restore MSR 403 */ 404 mtmsr(msr); 405 406 /* Warn if cachline size was not determined */ 407 if (cacheline_warn == 1) { 408 printf("WARNING: cacheline size undetermined, setting to 32\n"); 409 } 410 411 /* 412 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority 413 * in case the platform module had a better idea of what we 414 * should do. 415 */ 416 if (cpu_features & PPC_FEATURE_64) 417 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 418 else 419 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 420 } 421 422 /* 423 * Shutdown the CPU as much as possible. 424 */ 425 void 426 cpu_halt(void) 427 { 428 429 OF_exit(); 430 } 431 432 int 433 ptrace_single_step(struct thread *td) 434 { 435 struct trapframe *tf; 436 437 tf = td->td_frame; 438 tf->srr1 |= PSL_SE; 439 440 return (0); 441 } 442 443 int 444 ptrace_clear_single_step(struct thread *td) 445 { 446 struct trapframe *tf; 447 448 tf = td->td_frame; 449 tf->srr1 &= ~PSL_SE; 450 451 return (0); 452 } 453 454 void 455 kdb_cpu_clear_singlestep(void) 456 { 457 458 kdb_frame->srr1 &= ~PSL_SE; 459 } 460 461 void 462 kdb_cpu_set_singlestep(void) 463 { 464 465 kdb_frame->srr1 |= PSL_SE; 466 } 467 468 /* 469 * Initialise a struct pcpu. 470 */ 471 void 472 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 473 { 474 #ifdef __powerpc64__ 475 /* Copy the SLB contents from the current CPU */ 476 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb)); 477 #endif 478 } 479 480 #ifndef __powerpc64__ 481 uint64_t 482 va_to_vsid(pmap_t pm, vm_offset_t va) 483 { 484 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 485 } 486 487 #endif 488 489 /* 490 * These functions need to provide addresses that both (a) work in real mode 491 * (or whatever mode/circumstances the kernel is in in early boot (now)) and 492 * (b) can still, in principle, work once the kernel is going. Because these 493 * rely on existing mappings/real mode, unmap is a no-op. 494 */ 495 vm_offset_t 496 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 497 { 498 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 499 500 /* 501 * If we have the MMU up in early boot, assume it is 1:1. Otherwise, 502 * try to get the address in a memory region compatible with the 503 * direct map for efficiency later. 504 */ 505 if (mfmsr() & PSL_DR) 506 return (pa); 507 else 508 return (DMAP_BASE_ADDRESS + pa); 509 } 510 511 void 512 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 513 { 514 515 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 516 } 517 518 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */ 519 void 520 flush_disable_caches(void) 521 { 522 register_t msr; 523 register_t msscr0; 524 register_t cache_reg; 525 volatile uint32_t *memp; 526 uint32_t temp; 527 int i; 528 int x; 529 530 msr = mfmsr(); 531 powerpc_sync(); 532 mtmsr(msr & ~(PSL_EE | PSL_DR)); 533 msscr0 = mfspr(SPR_MSSCR0); 534 msscr0 &= ~MSSCR0_L2PFE; 535 mtspr(SPR_MSSCR0, msscr0); 536 powerpc_sync(); 537 isync(); 538 __asm__ __volatile__("dssall; sync"); 539 powerpc_sync(); 540 isync(); 541 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 542 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 543 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 544 545 /* Lock the L1 Data cache. */ 546 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); 547 powerpc_sync(); 548 isync(); 549 550 mtspr(SPR_LDSTCR, 0); 551 552 /* 553 * Perform this in two stages: Flush the cache starting in RAM, then do it 554 * from ROM. 555 */ 556 memp = (volatile uint32_t *)0x00000000; 557 for (i = 0; i < 128 * 1024; i++) { 558 temp = *memp; 559 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 560 memp += 32/sizeof(*memp); 561 } 562 563 memp = (volatile uint32_t *)0xfff00000; 564 x = 0xfe; 565 566 for (; x != 0xff;) { 567 mtspr(SPR_LDSTCR, x); 568 for (i = 0; i < 128; i++) { 569 temp = *memp; 570 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 571 memp += 32/sizeof(*memp); 572 } 573 x = ((x << 1) | 1) & 0xff; 574 } 575 mtspr(SPR_LDSTCR, 0); 576 577 cache_reg = mfspr(SPR_L2CR); 578 if (cache_reg & L2CR_L2E) { 579 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450); 580 mtspr(SPR_L2CR, cache_reg); 581 powerpc_sync(); 582 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); 583 while (mfspr(SPR_L2CR) & L2CR_L2HWF) 584 ; /* Busy wait for cache to flush */ 585 powerpc_sync(); 586 cache_reg &= ~L2CR_L2E; 587 mtspr(SPR_L2CR, cache_reg); 588 powerpc_sync(); 589 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); 590 powerpc_sync(); 591 while (mfspr(SPR_L2CR) & L2CR_L2I) 592 ; /* Busy wait for L2 cache invalidate */ 593 powerpc_sync(); 594 } 595 596 cache_reg = mfspr(SPR_L3CR); 597 if (cache_reg & L3CR_L3E) { 598 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO); 599 mtspr(SPR_L3CR, cache_reg); 600 powerpc_sync(); 601 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); 602 while (mfspr(SPR_L3CR) & L3CR_L3HWF) 603 ; /* Busy wait for cache to flush */ 604 powerpc_sync(); 605 cache_reg &= ~L3CR_L3E; 606 mtspr(SPR_L3CR, cache_reg); 607 powerpc_sync(); 608 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); 609 powerpc_sync(); 610 while (mfspr(SPR_L3CR) & L3CR_L3I) 611 ; /* Busy wait for L3 cache invalidate */ 612 powerpc_sync(); 613 } 614 615 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); 616 powerpc_sync(); 617 isync(); 618 619 mtmsr(msr); 620 } 621 622 void 623 cpu_sleep() 624 { 625 static u_quad_t timebase = 0; 626 static register_t sprgs[4]; 627 static register_t srrs[2]; 628 629 jmp_buf resetjb; 630 struct thread *fputd; 631 struct thread *vectd; 632 register_t hid0; 633 register_t msr; 634 register_t saved_msr; 635 636 ap_pcpu = pcpup; 637 638 PCPU_SET(restore, &resetjb); 639 640 saved_msr = mfmsr(); 641 fputd = PCPU_GET(fputhread); 642 vectd = PCPU_GET(vecthread); 643 if (fputd != NULL) 644 save_fpu(fputd); 645 if (vectd != NULL) 646 save_vec(vectd); 647 if (setjmp(resetjb) == 0) { 648 sprgs[0] = mfspr(SPR_SPRG0); 649 sprgs[1] = mfspr(SPR_SPRG1); 650 sprgs[2] = mfspr(SPR_SPRG2); 651 sprgs[3] = mfspr(SPR_SPRG3); 652 srrs[0] = mfspr(SPR_SRR0); 653 srrs[1] = mfspr(SPR_SRR1); 654 timebase = mftb(); 655 powerpc_sync(); 656 flush_disable_caches(); 657 hid0 = mfspr(SPR_HID0); 658 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP; 659 powerpc_sync(); 660 isync(); 661 msr = mfmsr() | PSL_POW; 662 mtspr(SPR_HID0, hid0); 663 powerpc_sync(); 664 665 while (1) 666 mtmsr(msr); 667 } 668 platform_smp_timebase_sync(timebase, 0); 669 PCPU_SET(curthread, curthread); 670 PCPU_SET(curpcb, curthread->td_pcb); 671 pmap_activate(curthread); 672 powerpc_sync(); 673 mtspr(SPR_SPRG0, sprgs[0]); 674 mtspr(SPR_SPRG1, sprgs[1]); 675 mtspr(SPR_SPRG2, sprgs[2]); 676 mtspr(SPR_SPRG3, sprgs[3]); 677 mtspr(SPR_SRR0, srrs[0]); 678 mtspr(SPR_SRR1, srrs[1]); 679 mtmsr(saved_msr); 680 if (fputd == curthread) 681 enable_fpu(curthread); 682 if (vectd == curthread) 683 enable_vec(curthread); 684 powerpc_sync(); 685 } 686 687