1 /*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by TooLs GmbH. 17 * 4. The name of TooLs GmbH may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 2001 Benno Rice 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57 #include <sys/cdefs.h> 58 __FBSDID("$FreeBSD$"); 59 60 #include "opt_ddb.h" 61 #include "opt_kstack_pages.h" 62 #include "opt_platform.h" 63 64 #include <sys/param.h> 65 #include <sys/proc.h> 66 #include <sys/systm.h> 67 #include <sys/bio.h> 68 #include <sys/buf.h> 69 #include <sys/bus.h> 70 #include <sys/cons.h> 71 #include <sys/cpu.h> 72 #include <sys/eventhandler.h> 73 #include <sys/exec.h> 74 #include <sys/imgact.h> 75 #include <sys/kdb.h> 76 #include <sys/kernel.h> 77 #include <sys/ktr.h> 78 #include <sys/linker.h> 79 #include <sys/lock.h> 80 #include <sys/malloc.h> 81 #include <sys/mbuf.h> 82 #include <sys/msgbuf.h> 83 #include <sys/mutex.h> 84 #include <sys/ptrace.h> 85 #include <sys/reboot.h> 86 #include <sys/rwlock.h> 87 #include <sys/signalvar.h> 88 #include <sys/syscallsubr.h> 89 #include <sys/sysctl.h> 90 #include <sys/sysent.h> 91 #include <sys/sysproto.h> 92 #include <sys/ucontext.h> 93 #include <sys/uio.h> 94 #include <sys/vmmeter.h> 95 #include <sys/vnode.h> 96 97 #include <net/netisr.h> 98 99 #include <vm/vm.h> 100 #include <vm/vm_extern.h> 101 #include <vm/vm_kern.h> 102 #include <vm/vm_page.h> 103 #include <vm/vm_map.h> 104 #include <vm/vm_object.h> 105 #include <vm/vm_pager.h> 106 107 #include <machine/altivec.h> 108 #ifndef __powerpc64__ 109 #include <machine/bat.h> 110 #endif 111 #include <machine/cpu.h> 112 #include <machine/elf.h> 113 #include <machine/fpu.h> 114 #include <machine/hid.h> 115 #include <machine/kdb.h> 116 #include <machine/md_var.h> 117 #include <machine/metadata.h> 118 #include <machine/mmuvar.h> 119 #include <machine/pcb.h> 120 #include <machine/reg.h> 121 #include <machine/sigframe.h> 122 #include <machine/spr.h> 123 #include <machine/trap.h> 124 #include <machine/vmparam.h> 125 #include <machine/ofw_machdep.h> 126 127 #include <ddb/ddb.h> 128 129 #include <dev/ofw/openfirm.h> 130 131 #ifdef __powerpc64__ 132 #include "mmu_oea64.h" 133 #endif 134 135 #ifndef __powerpc64__ 136 struct bat battable[16]; 137 #endif 138 139 int radix_mmu = 0; 140 141 #ifndef __powerpc64__ 142 /* Bits for running on 64-bit systems in 32-bit mode. */ 143 extern void *testppc64, *testppc64size; 144 extern void *restorebridge, *restorebridgesize; 145 extern void *rfid_patch, *rfi_patch1, *rfi_patch2; 146 extern void *trapcode64; 147 148 extern Elf_Addr _GLOBAL_OFFSET_TABLE_[]; 149 #endif 150 151 extern void *rstcode, *rstcodeend; 152 extern void *trapcode, *trapcodeend; 153 extern void *hypertrapcode, *hypertrapcodeend; 154 extern void *generictrap, *generictrap64; 155 extern void *alitrap, *aliend; 156 extern void *dsitrap, *dsiend; 157 extern void *decrint, *decrsize; 158 extern void *extint, *extsize; 159 extern void *dblow, *dbend; 160 extern void *imisstrap, *imisssize; 161 extern void *dlmisstrap, *dlmisssize; 162 extern void *dsmisstrap, *dsmisssize; 163 164 extern void *ap_pcpu; 165 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); 166 extern void __restartkernel_virtual(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); 167 168 void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, 169 void *mdp, uint32_t mdp_cookie); 170 void aim_cpu_init(vm_offset_t toc); 171 172 void 173 aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp, 174 uint32_t mdp_cookie) 175 { 176 register_t scratch; 177 178 /* 179 * If running from an FDT, make sure we are in real mode to avoid 180 * tromping on firmware page tables. Everything in the kernel assumes 181 * 1:1 mappings out of firmware, so this won't break anything not 182 * already broken. This doesn't work if there is live OF, since OF 183 * may internally use non-1:1 mappings. 184 */ 185 if (ofentry == 0) 186 mtmsr(mfmsr() & ~(PSL_IR | PSL_DR)); 187 188 #ifdef __powerpc64__ 189 /* 190 * Relocate to high memory so that the kernel 191 * can execute from the direct map. 192 * 193 * If we are in virtual mode already, use a special entry point 194 * that sets up a temporary DMAP to execute from until we can 195 * properly set up the MMU. 196 */ 197 if ((vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS) { 198 if (mfmsr() & PSL_DR) { 199 __restartkernel_virtual(fdt, 0, ofentry, mdp, 200 mdp_cookie, DMAP_BASE_ADDRESS, mfmsr()); 201 } else { 202 __restartkernel(fdt, 0, ofentry, mdp, mdp_cookie, 203 DMAP_BASE_ADDRESS, mfmsr()); 204 } 205 } 206 #endif 207 208 /* Various very early CPU fix ups */ 209 switch (mfpvr() >> 16) { 210 /* 211 * PowerPC 970 CPUs have a misfeature requested by Apple that 212 * makes them pretend they have a 32-byte cacheline. Turn this 213 * off before we measure the cacheline size. 214 */ 215 case IBM970: 216 case IBM970FX: 217 case IBM970MP: 218 case IBM970GX: 219 scratch = mfspr(SPR_HID5); 220 scratch &= ~HID5_970_DCBZ_SIZE_HI; 221 mtspr(SPR_HID5, scratch); 222 break; 223 #ifdef __powerpc64__ 224 case IBMPOWER7: 225 case IBMPOWER7PLUS: 226 case IBMPOWER8: 227 case IBMPOWER8E: 228 case IBMPOWER8NVL: 229 case IBMPOWER9: 230 /* XXX: get from ibm,slb-size in device tree */ 231 n_slbs = 32; 232 break; 233 #endif 234 } 235 } 236 237 void 238 aim_cpu_init(vm_offset_t toc) 239 { 240 size_t trap_offset, trapsize; 241 vm_offset_t trap; 242 register_t msr; 243 uint8_t *cache_check; 244 int cacheline_warn; 245 #ifndef __powerpc64__ 246 register_t scratch; 247 int ppc64; 248 #endif 249 250 trap_offset = 0; 251 cacheline_warn = 0; 252 253 /* General setup for AIM CPUs */ 254 psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 255 256 #ifdef __powerpc64__ 257 psl_kernset |= PSL_SF; 258 if (mfmsr() & PSL_HV) 259 psl_kernset |= PSL_HV; 260 #endif 261 psl_userset = psl_kernset | PSL_PR; 262 #ifdef __powerpc64__ 263 psl_userset32 = psl_userset & ~PSL_SF; 264 #endif 265 266 /* 267 * Zeroed bits in this variable signify that the value of the bit 268 * in its position is allowed to vary between userspace contexts. 269 * 270 * All other bits are required to be identical for every userspace 271 * context. The actual *value* of the bit is determined by 272 * psl_userset and/or psl_userset32, and is not allowed to change. 273 * 274 * Remember to update this set when implementing support for 275 * *conditionally* enabling a processor facility. Failing to do 276 * this will cause swapcontext() in userspace to break when a 277 * process uses a conditionally-enabled facility. 278 * 279 * When *unconditionally* implementing support for a processor 280 * facility, update psl_userset / psl_userset32 instead. 281 * 282 * See the access control check in set_mcontext(). 283 */ 284 psl_userstatic = ~(PSL_VSX | PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 285 /* 286 * Mask bits from the SRR1 that aren't really the MSR: 287 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) 288 */ 289 psl_userstatic &= ~0x783f0000UL; 290 291 /* 292 * Initialize the interrupt tables and figure out our cache line 293 * size and whether or not we need the 64-bit bridge code. 294 */ 295 296 /* 297 * Disable translation in case the vector area hasn't been 298 * mapped (G5). Note that no OFW calls can be made until 299 * translation is re-enabled. 300 */ 301 302 msr = mfmsr(); 303 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); 304 305 /* 306 * Measure the cacheline size using dcbz 307 * 308 * Use EXC_PGM as a playground. We are about to overwrite it 309 * anyway, we know it exists, and we know it is cache-aligned. 310 */ 311 312 cache_check = (void *)EXC_PGM; 313 314 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++) 315 cache_check[cacheline_size] = 0xff; 316 317 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory"); 318 319 /* Find the first byte dcbz did not zero to get the cache line size */ 320 for (cacheline_size = 0; cacheline_size < 0x100 && 321 cache_check[cacheline_size] == 0; cacheline_size++); 322 323 /* Work around psim bug */ 324 if (cacheline_size == 0) { 325 cacheline_warn = 1; 326 cacheline_size = 32; 327 } 328 329 #ifndef __powerpc64__ 330 /* 331 * Figure out whether we need to use the 64 bit PMAP. This works by 332 * executing an instruction that is only legal on 64-bit PPC (mtmsrd), 333 * and setting ppc64 = 0 if that causes a trap. 334 */ 335 336 ppc64 = 1; 337 338 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size); 339 __syncicache((void *)EXC_PGM, (size_t)&testppc64size); 340 341 __asm __volatile("\ 342 mfmsr %0; \ 343 mtsprg2 %1; \ 344 \ 345 mtmsrd %0; \ 346 mfsprg2 %1;" 347 : "=r"(scratch), "=r"(ppc64)); 348 349 if (ppc64) 350 cpu_features |= PPC_FEATURE_64; 351 352 /* 353 * Now copy restorebridge into all the handlers, if necessary, 354 * and set up the trap tables. 355 */ 356 357 if (cpu_features & PPC_FEATURE_64) { 358 /* Patch the two instances of rfi -> rfid */ 359 bcopy(&rfid_patch,&rfi_patch1,4); 360 #ifdef KDB 361 /* rfi_patch2 is at the end of dbleave */ 362 bcopy(&rfid_patch,&rfi_patch2,4); 363 #endif 364 } 365 #else /* powerpc64 */ 366 cpu_features |= PPC_FEATURE_64; 367 #endif 368 369 trapsize = (size_t)&trapcodeend - (size_t)&trapcode; 370 371 /* 372 * Copy generic handler into every possible trap. Special cases will get 373 * different ones in a minute. 374 */ 375 for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20) 376 bcopy(&trapcode, (void *)trap, trapsize); 377 378 #ifndef __powerpc64__ 379 if (cpu_features & PPC_FEATURE_64) { 380 /* 381 * Copy a code snippet to restore 32-bit bridge mode 382 * to the top of every non-generic trap handler 383 */ 384 385 trap_offset += (size_t)&restorebridgesize; 386 bcopy(&restorebridge, (void *)EXC_RST, trap_offset); 387 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset); 388 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset); 389 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset); 390 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset); 391 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset); 392 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset); 393 } 394 #else 395 trapsize = (size_t)&hypertrapcodeend - (size_t)&hypertrapcode; 396 bcopy(&hypertrapcode, (void *)(EXC_HEA + trap_offset), trapsize); 397 bcopy(&hypertrapcode, (void *)(EXC_HMI + trap_offset), trapsize); 398 bcopy(&hypertrapcode, (void *)(EXC_HVI + trap_offset), trapsize); 399 bcopy(&hypertrapcode, (void *)(EXC_SOFT_PATCH + trap_offset), trapsize); 400 #endif 401 402 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend - 403 (size_t)&rstcode); 404 405 #ifdef KDB 406 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend - 407 (size_t)&dblow); 408 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend - 409 (size_t)&dblow); 410 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend - 411 (size_t)&dblow); 412 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend - 413 (size_t)&dblow); 414 #endif 415 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend - 416 (size_t)&alitrap); 417 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend - 418 (size_t)&dsitrap); 419 420 /* Set address of generictrap for self-reloc calculations */ 421 *((void **)TRAP_GENTRAP) = &generictrap; 422 #ifdef __powerpc64__ 423 /* Set TOC base so that the interrupt code can get at it */ 424 *((void **)TRAP_ENTRY) = &generictrap; 425 *((register_t *)TRAP_TOCBASE) = toc; 426 #else 427 /* Set branch address for trap code */ 428 if (cpu_features & PPC_FEATURE_64) 429 *((void **)TRAP_ENTRY) = &generictrap64; 430 else 431 *((void **)TRAP_ENTRY) = &generictrap; 432 *((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_; 433 434 /* G2-specific TLB miss helper handlers */ 435 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); 436 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); 437 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 438 #endif 439 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 440 441 /* 442 * Restore MSR 443 */ 444 mtmsr(msr); 445 446 /* Warn if cachline size was not determined */ 447 if (cacheline_warn == 1) { 448 printf("WARNING: cacheline size undetermined, setting to 32\n"); 449 } 450 451 /* 452 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority 453 * in case the platform module had a better idea of what we 454 * should do. 455 */ 456 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) { 457 radix_mmu = 0; 458 TUNABLE_INT_FETCH("radix_mmu", &radix_mmu); 459 if (radix_mmu) 460 pmap_mmu_install(MMU_TYPE_RADIX, BUS_PROBE_GENERIC); 461 else 462 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 463 } else if (cpu_features & PPC_FEATURE_64) 464 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 465 else 466 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 467 } 468 469 /* 470 * Shutdown the CPU as much as possible. 471 */ 472 void 473 cpu_halt(void) 474 { 475 476 OF_exit(); 477 } 478 479 int 480 ptrace_single_step(struct thread *td) 481 { 482 struct trapframe *tf; 483 484 tf = td->td_frame; 485 tf->srr1 |= PSL_SE; 486 487 return (0); 488 } 489 490 int 491 ptrace_clear_single_step(struct thread *td) 492 { 493 struct trapframe *tf; 494 495 tf = td->td_frame; 496 tf->srr1 &= ~PSL_SE; 497 498 return (0); 499 } 500 501 void 502 kdb_cpu_clear_singlestep(void) 503 { 504 505 kdb_frame->srr1 &= ~PSL_SE; 506 } 507 508 void 509 kdb_cpu_set_singlestep(void) 510 { 511 512 kdb_frame->srr1 |= PSL_SE; 513 } 514 515 /* 516 * Initialise a struct pcpu. 517 */ 518 void 519 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 520 { 521 #ifdef __powerpc64__ 522 /* Copy the SLB contents from the current CPU */ 523 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb)); 524 #endif 525 } 526 527 /* Return 0 on handled success, otherwise signal number. */ 528 int 529 cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode) 530 { 531 #ifdef __powerpc64__ 532 /* 533 * This block is 64-bit CPU specific currently. Punt running in 32-bit 534 * mode on 64-bit CPUs. 535 */ 536 /* Check if the important information is in DSISR */ 537 if ((frame->srr1 & SRR1_MCHK_DATA) != 0) { 538 printf("Machine check, DSISR: %016lx\n", frame->cpu.aim.dsisr); 539 /* SLB multi-hit is recoverable. */ 540 if ((frame->cpu.aim.dsisr & DSISR_MC_SLB_MULTIHIT) != 0) 541 return (0); 542 if ((frame->cpu.aim.dsisr & DSISR_MC_DERAT_MULTIHIT) != 0) { 543 pmap_tlbie_all(); 544 return (0); 545 } 546 /* TODO: Add other machine check recovery procedures. */ 547 } else { 548 if ((frame->srr1 & SRR1_MCHK_IFETCH_M) == SRR1_MCHK_IFETCH_SLBMH) 549 return (0); 550 } 551 #endif 552 *ucode = BUS_OBJERR; 553 return (SIGBUS); 554 } 555 556 557 #ifndef __powerpc64__ 558 uint64_t 559 va_to_vsid(pmap_t pm, vm_offset_t va) 560 { 561 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 562 } 563 564 #endif 565 566 /* 567 * These functions need to provide addresses that both (a) work in real mode 568 * (or whatever mode/circumstances the kernel is in in early boot (now)) and 569 * (b) can still, in principle, work once the kernel is going. Because these 570 * rely on existing mappings/real mode, unmap is a no-op. 571 */ 572 vm_offset_t 573 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 574 { 575 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 576 577 /* 578 * If we have the MMU up in early boot, assume it is 1:1. Otherwise, 579 * try to get the address in a memory region compatible with the 580 * direct map for efficiency later. 581 */ 582 if (mfmsr() & PSL_DR) 583 return (pa); 584 else 585 return (DMAP_BASE_ADDRESS + pa); 586 } 587 588 void 589 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 590 { 591 592 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 593 } 594 595 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */ 596 void 597 flush_disable_caches(void) 598 { 599 register_t msr; 600 register_t msscr0; 601 register_t cache_reg; 602 volatile uint32_t *memp; 603 uint32_t temp; 604 int i; 605 int x; 606 607 msr = mfmsr(); 608 powerpc_sync(); 609 mtmsr(msr & ~(PSL_EE | PSL_DR)); 610 msscr0 = mfspr(SPR_MSSCR0); 611 msscr0 &= ~MSSCR0_L2PFE; 612 mtspr(SPR_MSSCR0, msscr0); 613 powerpc_sync(); 614 isync(); 615 __asm__ __volatile__("dssall; sync"); 616 powerpc_sync(); 617 isync(); 618 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 619 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 620 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 621 622 /* Lock the L1 Data cache. */ 623 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); 624 powerpc_sync(); 625 isync(); 626 627 mtspr(SPR_LDSTCR, 0); 628 629 /* 630 * Perform this in two stages: Flush the cache starting in RAM, then do it 631 * from ROM. 632 */ 633 memp = (volatile uint32_t *)0x00000000; 634 for (i = 0; i < 128 * 1024; i++) { 635 temp = *memp; 636 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 637 memp += 32/sizeof(*memp); 638 } 639 640 memp = (volatile uint32_t *)0xfff00000; 641 x = 0xfe; 642 643 for (; x != 0xff;) { 644 mtspr(SPR_LDSTCR, x); 645 for (i = 0; i < 128; i++) { 646 temp = *memp; 647 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 648 memp += 32/sizeof(*memp); 649 } 650 x = ((x << 1) | 1) & 0xff; 651 } 652 mtspr(SPR_LDSTCR, 0); 653 654 cache_reg = mfspr(SPR_L2CR); 655 if (cache_reg & L2CR_L2E) { 656 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450); 657 mtspr(SPR_L2CR, cache_reg); 658 powerpc_sync(); 659 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); 660 while (mfspr(SPR_L2CR) & L2CR_L2HWF) 661 ; /* Busy wait for cache to flush */ 662 powerpc_sync(); 663 cache_reg &= ~L2CR_L2E; 664 mtspr(SPR_L2CR, cache_reg); 665 powerpc_sync(); 666 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); 667 powerpc_sync(); 668 while (mfspr(SPR_L2CR) & L2CR_L2I) 669 ; /* Busy wait for L2 cache invalidate */ 670 powerpc_sync(); 671 } 672 673 cache_reg = mfspr(SPR_L3CR); 674 if (cache_reg & L3CR_L3E) { 675 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO); 676 mtspr(SPR_L3CR, cache_reg); 677 powerpc_sync(); 678 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); 679 while (mfspr(SPR_L3CR) & L3CR_L3HWF) 680 ; /* Busy wait for cache to flush */ 681 powerpc_sync(); 682 cache_reg &= ~L3CR_L3E; 683 mtspr(SPR_L3CR, cache_reg); 684 powerpc_sync(); 685 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); 686 powerpc_sync(); 687 while (mfspr(SPR_L3CR) & L3CR_L3I) 688 ; /* Busy wait for L3 cache invalidate */ 689 powerpc_sync(); 690 } 691 692 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); 693 powerpc_sync(); 694 isync(); 695 696 mtmsr(msr); 697 } 698 699 void 700 cpu_sleep() 701 { 702 static u_quad_t timebase = 0; 703 static register_t sprgs[4]; 704 static register_t srrs[2]; 705 706 jmp_buf resetjb; 707 struct thread *fputd; 708 struct thread *vectd; 709 register_t hid0; 710 register_t msr; 711 register_t saved_msr; 712 713 ap_pcpu = pcpup; 714 715 PCPU_SET(restore, &resetjb); 716 717 saved_msr = mfmsr(); 718 fputd = PCPU_GET(fputhread); 719 vectd = PCPU_GET(vecthread); 720 if (fputd != NULL) 721 save_fpu(fputd); 722 if (vectd != NULL) 723 save_vec(vectd); 724 if (setjmp(resetjb) == 0) { 725 sprgs[0] = mfspr(SPR_SPRG0); 726 sprgs[1] = mfspr(SPR_SPRG1); 727 sprgs[2] = mfspr(SPR_SPRG2); 728 sprgs[3] = mfspr(SPR_SPRG3); 729 srrs[0] = mfspr(SPR_SRR0); 730 srrs[1] = mfspr(SPR_SRR1); 731 timebase = mftb(); 732 powerpc_sync(); 733 flush_disable_caches(); 734 hid0 = mfspr(SPR_HID0); 735 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP; 736 powerpc_sync(); 737 isync(); 738 msr = mfmsr() | PSL_POW; 739 mtspr(SPR_HID0, hid0); 740 powerpc_sync(); 741 742 while (1) 743 mtmsr(msr); 744 } 745 platform_smp_timebase_sync(timebase, 0); 746 PCPU_SET(curthread, curthread); 747 PCPU_SET(curpcb, curthread->td_pcb); 748 pmap_activate(curthread); 749 powerpc_sync(); 750 mtspr(SPR_SPRG0, sprgs[0]); 751 mtspr(SPR_SPRG1, sprgs[1]); 752 mtspr(SPR_SPRG2, sprgs[2]); 753 mtspr(SPR_SPRG3, sprgs[3]); 754 mtspr(SPR_SRR0, srrs[0]); 755 mtspr(SPR_SRR1, srrs[1]); 756 mtmsr(saved_msr); 757 if (fputd == curthread) 758 enable_fpu(curthread); 759 if (vectd == curthread) 760 enable_vec(curthread); 761 powerpc_sync(); 762 } 763 764