1 /*- 2 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 3 * Copyright (C) 1995, 1996 TooLs GmbH. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by TooLs GmbH. 17 * 4. The name of TooLs GmbH may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 2001 Benno Rice 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $ 55 */ 56 57 #include <sys/cdefs.h> 58 __FBSDID("$FreeBSD$"); 59 60 #include "opt_compat.h" 61 #include "opt_ddb.h" 62 #include "opt_kstack_pages.h" 63 #include "opt_platform.h" 64 65 #include <sys/param.h> 66 #include <sys/proc.h> 67 #include <sys/systm.h> 68 #include <sys/bio.h> 69 #include <sys/buf.h> 70 #include <sys/bus.h> 71 #include <sys/cons.h> 72 #include <sys/cpu.h> 73 #include <sys/eventhandler.h> 74 #include <sys/exec.h> 75 #include <sys/imgact.h> 76 #include <sys/kdb.h> 77 #include <sys/kernel.h> 78 #include <sys/ktr.h> 79 #include <sys/linker.h> 80 #include <sys/lock.h> 81 #include <sys/malloc.h> 82 #include <sys/mbuf.h> 83 #include <sys/msgbuf.h> 84 #include <sys/mutex.h> 85 #include <sys/ptrace.h> 86 #include <sys/reboot.h> 87 #include <sys/rwlock.h> 88 #include <sys/signalvar.h> 89 #include <sys/syscallsubr.h> 90 #include <sys/sysctl.h> 91 #include <sys/sysent.h> 92 #include <sys/sysproto.h> 93 #include <sys/ucontext.h> 94 #include <sys/uio.h> 95 #include <sys/vmmeter.h> 96 #include <sys/vnode.h> 97 98 #include <net/netisr.h> 99 100 #include <vm/vm.h> 101 #include <vm/vm_extern.h> 102 #include <vm/vm_kern.h> 103 #include <vm/vm_page.h> 104 #include <vm/vm_map.h> 105 #include <vm/vm_object.h> 106 #include <vm/vm_pager.h> 107 108 #include <machine/altivec.h> 109 #ifndef __powerpc64__ 110 #include <machine/bat.h> 111 #endif 112 #include <machine/cpu.h> 113 #include <machine/elf.h> 114 #include <machine/fpu.h> 115 #include <machine/hid.h> 116 #include <machine/kdb.h> 117 #include <machine/md_var.h> 118 #include <machine/metadata.h> 119 #include <machine/mmuvar.h> 120 #include <machine/pcb.h> 121 #include <machine/reg.h> 122 #include <machine/sigframe.h> 123 #include <machine/spr.h> 124 #include <machine/trap.h> 125 #include <machine/vmparam.h> 126 #include <machine/ofw_machdep.h> 127 128 #include <ddb/ddb.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #ifdef __powerpc64__ 133 #include "mmu_oea64.h" 134 #endif 135 136 #ifndef __powerpc64__ 137 struct bat battable[16]; 138 #endif 139 140 #ifndef __powerpc64__ 141 /* Bits for running on 64-bit systems in 32-bit mode. */ 142 extern void *testppc64, *testppc64size; 143 extern void *restorebridge, *restorebridgesize; 144 extern void *rfid_patch, *rfi_patch1, *rfi_patch2; 145 extern void *trapcode64; 146 147 extern Elf_Addr _GLOBAL_OFFSET_TABLE_[]; 148 #endif 149 150 extern void *rstcode, *rstcodeend; 151 extern void *trapcode, *trapcodeend; 152 extern void *generictrap, *generictrap64; 153 extern void *alitrap, *aliend; 154 extern void *dsitrap, *dsiend; 155 extern void *decrint, *decrsize; 156 extern void *extint, *extsize; 157 extern void *dblow, *dbend; 158 extern void *imisstrap, *imisssize; 159 extern void *dlmisstrap, *dlmisssize; 160 extern void *dsmisstrap, *dsmisssize; 161 162 extern void *ap_pcpu; 163 164 void aim_cpu_init(vm_offset_t toc); 165 166 void 167 aim_cpu_init(vm_offset_t toc) 168 { 169 size_t trap_offset, trapsize; 170 vm_offset_t trap; 171 register_t msr, scratch; 172 uint8_t *cache_check; 173 int cacheline_warn; 174 #ifndef __powerpc64__ 175 int ppc64; 176 #endif 177 178 trap_offset = 0; 179 cacheline_warn = 0; 180 181 /* General setup for AIM CPUs */ 182 psl_kernset = PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI; 183 184 #ifdef __powerpc64__ 185 psl_kernset |= PSL_SF; 186 if (mfmsr() & PSL_HV) 187 psl_kernset |= PSL_HV; 188 #endif 189 psl_userset = psl_kernset | PSL_PR; 190 #ifdef __powerpc64__ 191 psl_userset32 = psl_userset & ~PSL_SF; 192 #endif 193 194 /* Bits that users aren't allowed to change */ 195 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); 196 /* 197 * Mask bits from the SRR1 that aren't really the MSR: 198 * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) 199 */ 200 psl_userstatic &= ~0x783f0000UL; 201 202 /* Various very early CPU fix ups */ 203 switch (mfpvr() >> 16) { 204 /* 205 * PowerPC 970 CPUs have a misfeature requested by Apple that 206 * makes them pretend they have a 32-byte cacheline. Turn this 207 * off before we measure the cacheline size. 208 */ 209 case IBM970: 210 case IBM970FX: 211 case IBM970MP: 212 case IBM970GX: 213 scratch = mfspr(SPR_HID5); 214 scratch &= ~HID5_970_DCBZ_SIZE_HI; 215 mtspr(SPR_HID5, scratch); 216 break; 217 #ifdef __powerpc64__ 218 case IBMPOWER7: 219 case IBMPOWER7PLUS: 220 case IBMPOWER8: 221 case IBMPOWER8E: 222 /* XXX: get from ibm,slb-size in device tree */ 223 n_slbs = 32; 224 break; 225 #endif 226 } 227 228 /* 229 * Initialize the interrupt tables and figure out our cache line 230 * size and whether or not we need the 64-bit bridge code. 231 */ 232 233 /* 234 * Disable translation in case the vector area hasn't been 235 * mapped (G5). Note that no OFW calls can be made until 236 * translation is re-enabled. 237 */ 238 239 msr = mfmsr(); 240 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); 241 242 /* 243 * Measure the cacheline size using dcbz 244 * 245 * Use EXC_PGM as a playground. We are about to overwrite it 246 * anyway, we know it exists, and we know it is cache-aligned. 247 */ 248 249 cache_check = (void *)EXC_PGM; 250 251 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++) 252 cache_check[cacheline_size] = 0xff; 253 254 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory"); 255 256 /* Find the first byte dcbz did not zero to get the cache line size */ 257 for (cacheline_size = 0; cacheline_size < 0x100 && 258 cache_check[cacheline_size] == 0; cacheline_size++); 259 260 /* Work around psim bug */ 261 if (cacheline_size == 0) { 262 cacheline_warn = 1; 263 cacheline_size = 32; 264 } 265 266 #ifndef __powerpc64__ 267 /* 268 * Figure out whether we need to use the 64 bit PMAP. This works by 269 * executing an instruction that is only legal on 64-bit PPC (mtmsrd), 270 * and setting ppc64 = 0 if that causes a trap. 271 */ 272 273 ppc64 = 1; 274 275 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size); 276 __syncicache((void *)EXC_PGM, (size_t)&testppc64size); 277 278 __asm __volatile("\ 279 mfmsr %0; \ 280 mtsprg2 %1; \ 281 \ 282 mtmsrd %0; \ 283 mfsprg2 %1;" 284 : "=r"(scratch), "=r"(ppc64)); 285 286 if (ppc64) 287 cpu_features |= PPC_FEATURE_64; 288 289 /* 290 * Now copy restorebridge into all the handlers, if necessary, 291 * and set up the trap tables. 292 */ 293 294 if (cpu_features & PPC_FEATURE_64) { 295 /* Patch the two instances of rfi -> rfid */ 296 bcopy(&rfid_patch,&rfi_patch1,4); 297 #ifdef KDB 298 /* rfi_patch2 is at the end of dbleave */ 299 bcopy(&rfid_patch,&rfi_patch2,4); 300 #endif 301 } 302 #else /* powerpc64 */ 303 cpu_features |= PPC_FEATURE_64; 304 #endif 305 306 trapsize = (size_t)&trapcodeend - (size_t)&trapcode; 307 308 /* 309 * Copy generic handler into every possible trap. Special cases will get 310 * different ones in a minute. 311 */ 312 for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20) 313 bcopy(&trapcode, (void *)trap, trapsize); 314 315 #ifndef __powerpc64__ 316 if (cpu_features & PPC_FEATURE_64) { 317 /* 318 * Copy a code snippet to restore 32-bit bridge mode 319 * to the top of every non-generic trap handler 320 */ 321 322 trap_offset += (size_t)&restorebridgesize; 323 bcopy(&restorebridge, (void *)EXC_RST, trap_offset); 324 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset); 325 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset); 326 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset); 327 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset); 328 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset); 329 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset); 330 } 331 #endif 332 333 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstcodeend - 334 (size_t)&rstcode); 335 336 #ifdef KDB 337 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbend - 338 (size_t)&dblow); 339 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbend - 340 (size_t)&dblow); 341 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbend - 342 (size_t)&dblow); 343 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbend - 344 (size_t)&dblow); 345 #endif 346 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&aliend - 347 (size_t)&alitrap); 348 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsiend - 349 (size_t)&dsitrap); 350 351 #ifdef __powerpc64__ 352 /* Set TOC base so that the interrupt code can get at it */ 353 *((void **)TRAP_GENTRAP) = &generictrap; 354 *((register_t *)TRAP_TOCBASE) = toc; 355 #else 356 /* Set branch address for trap code */ 357 if (cpu_features & PPC_FEATURE_64) 358 *((void **)TRAP_GENTRAP) = &generictrap64; 359 else 360 *((void **)TRAP_GENTRAP) = &generictrap; 361 *((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_; 362 363 /* G2-specific TLB miss helper handlers */ 364 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); 365 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); 366 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); 367 #endif 368 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD); 369 370 /* 371 * Restore MSR 372 */ 373 mtmsr(msr); 374 375 /* Warn if cachline size was not determined */ 376 if (cacheline_warn == 1) { 377 printf("WARNING: cacheline size undetermined, setting to 32\n"); 378 } 379 380 /* 381 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority 382 * in case the platform module had a better idea of what we 383 * should do. 384 */ 385 if (cpu_features & PPC_FEATURE_64) 386 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC); 387 else 388 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC); 389 } 390 391 /* 392 * Shutdown the CPU as much as possible. 393 */ 394 void 395 cpu_halt(void) 396 { 397 398 OF_exit(); 399 } 400 401 int 402 ptrace_single_step(struct thread *td) 403 { 404 struct trapframe *tf; 405 406 tf = td->td_frame; 407 tf->srr1 |= PSL_SE; 408 409 return (0); 410 } 411 412 int 413 ptrace_clear_single_step(struct thread *td) 414 { 415 struct trapframe *tf; 416 417 tf = td->td_frame; 418 tf->srr1 &= ~PSL_SE; 419 420 return (0); 421 } 422 423 void 424 kdb_cpu_clear_singlestep(void) 425 { 426 427 kdb_frame->srr1 &= ~PSL_SE; 428 } 429 430 void 431 kdb_cpu_set_singlestep(void) 432 { 433 434 kdb_frame->srr1 |= PSL_SE; 435 } 436 437 /* 438 * Initialise a struct pcpu. 439 */ 440 void 441 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz) 442 { 443 #ifdef __powerpc64__ 444 /* Copy the SLB contents from the current CPU */ 445 memcpy(pcpu->pc_aim.slb, PCPU_GET(aim.slb), sizeof(pcpu->pc_aim.slb)); 446 #endif 447 } 448 449 #ifndef __powerpc64__ 450 uint64_t 451 va_to_vsid(pmap_t pm, vm_offset_t va) 452 { 453 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK); 454 } 455 456 #endif 457 458 /* 459 * These functions need to provide addresses that both (a) work in real mode 460 * (or whatever mode/circumstances the kernel is in in early boot (now)) and 461 * (b) can still, in principle, work once the kernel is going. Because these 462 * rely on existing mappings/real mode, unmap is a no-op. 463 */ 464 vm_offset_t 465 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 466 { 467 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 468 469 /* 470 * If we have the MMU up in early boot, assume it is 1:1. Otherwise, 471 * try to get the address in a memory region compatible with the 472 * direct map for efficiency later. 473 */ 474 if (mfmsr() & PSL_DR) 475 return (pa); 476 else 477 return (DMAP_BASE_ADDRESS + pa); 478 } 479 480 void 481 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 482 { 483 484 KASSERT(!pmap_bootstrapped, ("Not available after PMAP started!")); 485 } 486 487 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */ 488 void 489 flush_disable_caches(void) 490 { 491 register_t msr; 492 register_t msscr0; 493 register_t cache_reg; 494 volatile uint32_t *memp; 495 uint32_t temp; 496 int i; 497 int x; 498 499 msr = mfmsr(); 500 powerpc_sync(); 501 mtmsr(msr & ~(PSL_EE | PSL_DR)); 502 msscr0 = mfspr(SPR_MSSCR0); 503 msscr0 &= ~MSSCR0_L2PFE; 504 mtspr(SPR_MSSCR0, msscr0); 505 powerpc_sync(); 506 isync(); 507 __asm__ __volatile__("dssall; sync"); 508 powerpc_sync(); 509 isync(); 510 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 511 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 512 __asm__ __volatile__("dcbf 0,%0" :: "r"(0)); 513 514 /* Lock the L1 Data cache. */ 515 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); 516 powerpc_sync(); 517 isync(); 518 519 mtspr(SPR_LDSTCR, 0); 520 521 /* 522 * Perform this in two stages: Flush the cache starting in RAM, then do it 523 * from ROM. 524 */ 525 memp = (volatile uint32_t *)0x00000000; 526 for (i = 0; i < 128 * 1024; i++) { 527 temp = *memp; 528 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 529 memp += 32/sizeof(*memp); 530 } 531 532 memp = (volatile uint32_t *)0xfff00000; 533 x = 0xfe; 534 535 for (; x != 0xff;) { 536 mtspr(SPR_LDSTCR, x); 537 for (i = 0; i < 128; i++) { 538 temp = *memp; 539 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp)); 540 memp += 32/sizeof(*memp); 541 } 542 x = ((x << 1) | 1) & 0xff; 543 } 544 mtspr(SPR_LDSTCR, 0); 545 546 cache_reg = mfspr(SPR_L2CR); 547 if (cache_reg & L2CR_L2E) { 548 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450); 549 mtspr(SPR_L2CR, cache_reg); 550 powerpc_sync(); 551 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF); 552 while (mfspr(SPR_L2CR) & L2CR_L2HWF) 553 ; /* Busy wait for cache to flush */ 554 powerpc_sync(); 555 cache_reg &= ~L2CR_L2E; 556 mtspr(SPR_L2CR, cache_reg); 557 powerpc_sync(); 558 mtspr(SPR_L2CR, cache_reg | L2CR_L2I); 559 powerpc_sync(); 560 while (mfspr(SPR_L2CR) & L2CR_L2I) 561 ; /* Busy wait for L2 cache invalidate */ 562 powerpc_sync(); 563 } 564 565 cache_reg = mfspr(SPR_L3CR); 566 if (cache_reg & L3CR_L3E) { 567 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO); 568 mtspr(SPR_L3CR, cache_reg); 569 powerpc_sync(); 570 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF); 571 while (mfspr(SPR_L3CR) & L3CR_L3HWF) 572 ; /* Busy wait for cache to flush */ 573 powerpc_sync(); 574 cache_reg &= ~L3CR_L3E; 575 mtspr(SPR_L3CR, cache_reg); 576 powerpc_sync(); 577 mtspr(SPR_L3CR, cache_reg | L3CR_L3I); 578 powerpc_sync(); 579 while (mfspr(SPR_L3CR) & L3CR_L3I) 580 ; /* Busy wait for L3 cache invalidate */ 581 powerpc_sync(); 582 } 583 584 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); 585 powerpc_sync(); 586 isync(); 587 588 mtmsr(msr); 589 } 590 591 void 592 cpu_sleep() 593 { 594 static u_quad_t timebase = 0; 595 static register_t sprgs[4]; 596 static register_t srrs[2]; 597 598 jmp_buf resetjb; 599 struct thread *fputd; 600 struct thread *vectd; 601 register_t hid0; 602 register_t msr; 603 register_t saved_msr; 604 605 ap_pcpu = pcpup; 606 607 PCPU_SET(restore, &resetjb); 608 609 saved_msr = mfmsr(); 610 fputd = PCPU_GET(fputhread); 611 vectd = PCPU_GET(vecthread); 612 if (fputd != NULL) 613 save_fpu(fputd); 614 if (vectd != NULL) 615 save_vec(vectd); 616 if (setjmp(resetjb) == 0) { 617 sprgs[0] = mfspr(SPR_SPRG0); 618 sprgs[1] = mfspr(SPR_SPRG1); 619 sprgs[2] = mfspr(SPR_SPRG2); 620 sprgs[3] = mfspr(SPR_SPRG3); 621 srrs[0] = mfspr(SPR_SRR0); 622 srrs[1] = mfspr(SPR_SRR1); 623 timebase = mftb(); 624 powerpc_sync(); 625 flush_disable_caches(); 626 hid0 = mfspr(SPR_HID0); 627 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP; 628 powerpc_sync(); 629 isync(); 630 msr = mfmsr() | PSL_POW; 631 mtspr(SPR_HID0, hid0); 632 powerpc_sync(); 633 634 while (1) 635 mtmsr(msr); 636 } 637 platform_smp_timebase_sync(timebase, 0); 638 PCPU_SET(curthread, curthread); 639 PCPU_SET(curpcb, curthread->td_pcb); 640 pmap_activate(curthread); 641 powerpc_sync(); 642 mtspr(SPR_SPRG0, sprgs[0]); 643 mtspr(SPR_SPRG1, sprgs[1]); 644 mtspr(SPR_SPRG2, sprgs[2]); 645 mtspr(SPR_SPRG3, sprgs[3]); 646 mtspr(SPR_SRR0, srrs[0]); 647 mtspr(SPR_SRR1, srrs[1]); 648 mtmsr(saved_msr); 649 if (fputd == curthread) 650 enable_fpu(curthread); 651 if (vectd == curthread) 652 enable_vec(curthread); 653 powerpc_sync(); 654 } 655 656