1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*- 32 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33 * Copyright (C) 1995, 1996 TooLs GmbH. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by TooLs GmbH. 47 * 4. The name of TooLs GmbH may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 62 */ 63 /*- 64 * Copyright (C) 2001 Benno Rice. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 86 */ 87 88 #include <sys/cdefs.h> 89 __FBSDID("$FreeBSD$"); 90 91 /* 92 * Manages physical address maps. 93 * 94 * Since the information managed by this module is also stored by the 95 * logical address mapping module, this module may throw away valid virtual 96 * to physical mappings at almost any time. However, invalidations of 97 * mappings must be done as requested. 98 * 99 * In order to cope with hardware architectures which make virtual to 100 * physical map invalidates expensive, this module may delay invalidate 101 * reduced protection operations until such time as they are actually 102 * necessary. This module is given full information as to which processors 103 * are currently using which maps, and to when physical maps must be made 104 * correct. 105 */ 106 107 #include "opt_kstack_pages.h" 108 109 #include <sys/param.h> 110 #include <sys/kernel.h> 111 #include <sys/conf.h> 112 #include <sys/queue.h> 113 #include <sys/cpuset.h> 114 #include <sys/kerneldump.h> 115 #include <sys/ktr.h> 116 #include <sys/lock.h> 117 #include <sys/msgbuf.h> 118 #include <sys/mutex.h> 119 #include <sys/proc.h> 120 #include <sys/rwlock.h> 121 #include <sys/sched.h> 122 #include <sys/sysctl.h> 123 #include <sys/systm.h> 124 #include <sys/vmmeter.h> 125 126 #include <dev/ofw/openfirm.h> 127 128 #include <vm/vm.h> 129 #include <vm/vm_param.h> 130 #include <vm/vm_kern.h> 131 #include <vm/vm_page.h> 132 #include <vm/vm_map.h> 133 #include <vm/vm_object.h> 134 #include <vm/vm_extern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_phys.h> 137 #include <vm/vm_pageout.h> 138 #include <vm/uma.h> 139 140 #include <machine/cpu.h> 141 #include <machine/platform.h> 142 #include <machine/bat.h> 143 #include <machine/frame.h> 144 #include <machine/md_var.h> 145 #include <machine/psl.h> 146 #include <machine/pte.h> 147 #include <machine/smp.h> 148 #include <machine/sr.h> 149 #include <machine/mmuvar.h> 150 #include <machine/trap.h> 151 152 #define MOEA_DEBUG 153 154 #define TODO panic("%s: not implemented", __func__); 155 156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 157 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 159 160 struct ofw_map { 161 vm_offset_t om_va; 162 vm_size_t om_len; 163 vm_offset_t om_pa; 164 u_int om_mode; 165 }; 166 167 extern unsigned char _etext[]; 168 extern unsigned char _end[]; 169 170 /* 171 * Map of physical memory regions. 172 */ 173 static struct mem_region *regions; 174 static struct mem_region *pregions; 175 static u_int phys_avail_count; 176 static int regions_sz, pregions_sz; 177 static struct ofw_map *translations; 178 179 /* 180 * Lock for the pteg and pvo tables. 181 */ 182 struct mtx moea_table_mutex; 183 struct mtx moea_vsid_mutex; 184 185 /* tlbie instruction synchronization */ 186 static struct mtx tlbie_mtx; 187 188 /* 189 * PTEG data. 190 */ 191 static struct pteg *moea_pteg_table; 192 u_int moea_pteg_count; 193 u_int moea_pteg_mask; 194 195 /* 196 * PVO data. 197 */ 198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 199 struct pvo_head moea_pvo_kunmanaged = 200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 201 202 static struct rwlock_padalign pvh_global_lock; 203 204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 206 207 #define BPVO_POOL_SIZE 32768 208 static struct pvo_entry *moea_bpvo_pool; 209 static int moea_bpvo_pool_index = 0; 210 211 #define VSID_NBPW (sizeof(u_int32_t) * 8) 212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 213 214 static boolean_t moea_initialized = FALSE; 215 216 /* 217 * Statistics. 218 */ 219 u_int moea_pte_valid = 0; 220 u_int moea_pte_overflow = 0; 221 u_int moea_pte_replacements = 0; 222 u_int moea_pvo_entries = 0; 223 u_int moea_pvo_enter_calls = 0; 224 u_int moea_pvo_remove_calls = 0; 225 u_int moea_pte_spills = 0; 226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 227 0, ""); 228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 229 &moea_pte_overflow, 0, ""); 230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 231 &moea_pte_replacements, 0, ""); 232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 233 0, ""); 234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 235 &moea_pvo_enter_calls, 0, ""); 236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 237 &moea_pvo_remove_calls, 0, ""); 238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 239 &moea_pte_spills, 0, ""); 240 241 /* 242 * Allocate physical memory for use in moea_bootstrap. 243 */ 244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 245 246 /* 247 * PTE calls. 248 */ 249 static int moea_pte_insert(u_int, struct pte *); 250 251 /* 252 * PVO calls. 253 */ 254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 255 vm_offset_t, vm_paddr_t, u_int, int); 256 static void moea_pvo_remove(struct pvo_entry *, int); 257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 259 260 /* 261 * Utility routines. 262 */ 263 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 264 vm_prot_t, u_int, int8_t); 265 static void moea_syncicache(vm_paddr_t, vm_size_t); 266 static boolean_t moea_query_bit(vm_page_t, int); 267 static u_int moea_clear_bit(vm_page_t, int); 268 static void moea_kremove(vm_offset_t); 269 int moea_pte_spill(vm_offset_t); 270 271 /* 272 * Kernel MMU interface 273 */ 274 void moea_clear_modify(vm_page_t); 275 void moea_copy_page(vm_page_t, vm_page_t); 276 void moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 277 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 278 int moea_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int, 279 int8_t); 280 void moea_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 void moea_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283 vm_paddr_t moea_extract(pmap_t, vm_offset_t); 284 vm_page_t moea_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 285 void moea_init(void); 286 boolean_t moea_is_modified(vm_page_t); 287 boolean_t moea_is_prefaultable(pmap_t, vm_offset_t); 288 boolean_t moea_is_referenced(vm_page_t); 289 int moea_ts_referenced(vm_page_t); 290 vm_offset_t moea_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 291 boolean_t moea_page_exists_quick(pmap_t, vm_page_t); 292 void moea_page_init(vm_page_t); 293 int moea_page_wired_mappings(vm_page_t); 294 int moea_pinit(pmap_t); 295 void moea_pinit0(pmap_t); 296 void moea_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 297 void moea_qenter(vm_offset_t, vm_page_t *, int); 298 void moea_qremove(vm_offset_t, int); 299 void moea_release(pmap_t); 300 void moea_remove(pmap_t, vm_offset_t, vm_offset_t); 301 void moea_remove_all(vm_page_t); 302 void moea_remove_write(vm_page_t); 303 void moea_unwire(pmap_t, vm_offset_t, vm_offset_t); 304 void moea_zero_page(vm_page_t); 305 void moea_zero_page_area(vm_page_t, int, int); 306 void moea_activate(struct thread *); 307 void moea_deactivate(struct thread *); 308 void moea_cpu_bootstrap(int); 309 void moea_bootstrap(vm_offset_t, vm_offset_t); 310 void *moea_mapdev(vm_paddr_t, vm_size_t); 311 void *moea_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 312 void moea_unmapdev(vm_offset_t, vm_size_t); 313 vm_paddr_t moea_kextract(vm_offset_t); 314 void moea_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t); 315 void moea_kenter(vm_offset_t, vm_paddr_t); 316 void moea_page_set_memattr(vm_page_t m, vm_memattr_t ma); 317 boolean_t moea_dev_direct_mapped(vm_paddr_t, vm_size_t); 318 static void moea_sync_icache(pmap_t, vm_offset_t, vm_size_t); 319 void moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va); 320 void moea_scan_init(void); 321 vm_offset_t moea_quick_enter_page(vm_page_t m); 322 void moea_quick_remove_page(vm_offset_t addr); 323 boolean_t moea_page_is_mapped(vm_page_t m); 324 static int moea_map_user_ptr(pmap_t pm, 325 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 326 static int moea_decode_kernel_ptr(vm_offset_t addr, 327 int *is_user, vm_offset_t *decoded_addr); 328 329 330 static struct pmap_funcs moea_methods = { 331 .clear_modify = moea_clear_modify, 332 .copy_page = moea_copy_page, 333 .copy_pages = moea_copy_pages, 334 .enter = moea_enter, 335 .enter_object = moea_enter_object, 336 .enter_quick = moea_enter_quick, 337 .extract = moea_extract, 338 .extract_and_hold = moea_extract_and_hold, 339 .init = moea_init, 340 .is_modified = moea_is_modified, 341 .is_prefaultable = moea_is_prefaultable, 342 .is_referenced = moea_is_referenced, 343 .ts_referenced = moea_ts_referenced, 344 .map = moea_map, 345 .page_exists_quick = moea_page_exists_quick, 346 .page_init = moea_page_init, 347 .page_wired_mappings = moea_page_wired_mappings, 348 .pinit = moea_pinit, 349 .pinit0 = moea_pinit0, 350 .protect = moea_protect, 351 .qenter = moea_qenter, 352 .qremove = moea_qremove, 353 .release = moea_release, 354 .remove = moea_remove, 355 .remove_all = moea_remove_all, 356 .remove_write = moea_remove_write, 357 .sync_icache = moea_sync_icache, 358 .unwire = moea_unwire, 359 .zero_page = moea_zero_page, 360 .zero_page_area = moea_zero_page_area, 361 .activate = moea_activate, 362 .deactivate = moea_deactivate, 363 .page_set_memattr = moea_page_set_memattr, 364 .quick_enter_page = moea_quick_enter_page, 365 .quick_remove_page = moea_quick_remove_page, 366 .page_is_mapped = moea_page_is_mapped, 367 368 /* Internal interfaces */ 369 .bootstrap = moea_bootstrap, 370 .cpu_bootstrap = moea_cpu_bootstrap, 371 .mapdev_attr = moea_mapdev_attr, 372 .mapdev = moea_mapdev, 373 .unmapdev = moea_unmapdev, 374 .kextract = moea_kextract, 375 .kenter = moea_kenter, 376 .kenter_attr = moea_kenter_attr, 377 .dev_direct_mapped = moea_dev_direct_mapped, 378 .dumpsys_pa_init = moea_scan_init, 379 .dumpsys_map_chunk = moea_dumpsys_map, 380 .map_user_ptr = moea_map_user_ptr, 381 .decode_kernel_ptr = moea_decode_kernel_ptr, 382 }; 383 384 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods); 385 386 static __inline uint32_t 387 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 388 { 389 uint32_t pte_lo; 390 int i; 391 392 if (ma != VM_MEMATTR_DEFAULT) { 393 switch (ma) { 394 case VM_MEMATTR_UNCACHEABLE: 395 return (PTE_I | PTE_G); 396 case VM_MEMATTR_CACHEABLE: 397 return (PTE_M); 398 case VM_MEMATTR_WRITE_COMBINING: 399 case VM_MEMATTR_WRITE_BACK: 400 case VM_MEMATTR_PREFETCHABLE: 401 return (PTE_I); 402 case VM_MEMATTR_WRITE_THROUGH: 403 return (PTE_W | PTE_M); 404 } 405 } 406 407 /* 408 * Assume the page is cache inhibited and access is guarded unless 409 * it's in our available memory array. 410 */ 411 pte_lo = PTE_I | PTE_G; 412 for (i = 0; i < pregions_sz; i++) { 413 if ((pa >= pregions[i].mr_start) && 414 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 415 pte_lo = PTE_M; 416 break; 417 } 418 } 419 420 return pte_lo; 421 } 422 423 static void 424 tlbie(vm_offset_t va) 425 { 426 427 mtx_lock_spin(&tlbie_mtx); 428 __asm __volatile("ptesync"); 429 __asm __volatile("tlbie %0" :: "r"(va)); 430 __asm __volatile("eieio; tlbsync; ptesync"); 431 mtx_unlock_spin(&tlbie_mtx); 432 } 433 434 static void 435 tlbia(void) 436 { 437 vm_offset_t va; 438 439 for (va = 0; va < 0x00040000; va += 0x00001000) { 440 __asm __volatile("tlbie %0" :: "r"(va)); 441 powerpc_sync(); 442 } 443 __asm __volatile("tlbsync"); 444 powerpc_sync(); 445 } 446 447 static __inline int 448 va_to_sr(u_int *sr, vm_offset_t va) 449 { 450 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 451 } 452 453 static __inline u_int 454 va_to_pteg(u_int sr, vm_offset_t addr) 455 { 456 u_int hash; 457 458 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 459 ADDR_PIDX_SHFT); 460 return (hash & moea_pteg_mask); 461 } 462 463 static __inline struct pvo_head * 464 vm_page_to_pvoh(vm_page_t m) 465 { 466 467 return (&m->md.mdpg_pvoh); 468 } 469 470 static __inline void 471 moea_attr_clear(vm_page_t m, int ptebit) 472 { 473 474 rw_assert(&pvh_global_lock, RA_WLOCKED); 475 m->md.mdpg_attrs &= ~ptebit; 476 } 477 478 static __inline int 479 moea_attr_fetch(vm_page_t m) 480 { 481 482 return (m->md.mdpg_attrs); 483 } 484 485 static __inline void 486 moea_attr_save(vm_page_t m, int ptebit) 487 { 488 489 rw_assert(&pvh_global_lock, RA_WLOCKED); 490 m->md.mdpg_attrs |= ptebit; 491 } 492 493 static __inline int 494 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 495 { 496 if (pt->pte_hi == pvo_pt->pte_hi) 497 return (1); 498 499 return (0); 500 } 501 502 static __inline int 503 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 504 { 505 return (pt->pte_hi & ~PTE_VALID) == 506 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 507 ((va >> ADDR_API_SHFT) & PTE_API) | which); 508 } 509 510 static __inline void 511 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 512 { 513 514 mtx_assert(&moea_table_mutex, MA_OWNED); 515 516 /* 517 * Construct a PTE. Default to IMB initially. Valid bit only gets 518 * set when the real pte is set in memory. 519 * 520 * Note: Don't set the valid bit for correct operation of tlb update. 521 */ 522 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 523 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 524 pt->pte_lo = pte_lo; 525 } 526 527 static __inline void 528 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 529 { 530 531 mtx_assert(&moea_table_mutex, MA_OWNED); 532 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 533 } 534 535 static __inline void 536 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 537 { 538 539 mtx_assert(&moea_table_mutex, MA_OWNED); 540 541 /* 542 * As shown in Section 7.6.3.2.3 543 */ 544 pt->pte_lo &= ~ptebit; 545 tlbie(va); 546 } 547 548 static __inline void 549 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 550 { 551 552 mtx_assert(&moea_table_mutex, MA_OWNED); 553 pvo_pt->pte_hi |= PTE_VALID; 554 555 /* 556 * Update the PTE as defined in section 7.6.3.1. 557 * Note that the REF/CHG bits are from pvo_pt and thus should have 558 * been saved so this routine can restore them (if desired). 559 */ 560 pt->pte_lo = pvo_pt->pte_lo; 561 powerpc_sync(); 562 pt->pte_hi = pvo_pt->pte_hi; 563 powerpc_sync(); 564 moea_pte_valid++; 565 } 566 567 static __inline void 568 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 569 { 570 571 mtx_assert(&moea_table_mutex, MA_OWNED); 572 pvo_pt->pte_hi &= ~PTE_VALID; 573 574 /* 575 * Force the reg & chg bits back into the PTEs. 576 */ 577 powerpc_sync(); 578 579 /* 580 * Invalidate the pte. 581 */ 582 pt->pte_hi &= ~PTE_VALID; 583 584 tlbie(va); 585 586 /* 587 * Save the reg & chg bits. 588 */ 589 moea_pte_synch(pt, pvo_pt); 590 moea_pte_valid--; 591 } 592 593 static __inline void 594 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 595 { 596 597 /* 598 * Invalidate the PTE 599 */ 600 moea_pte_unset(pt, pvo_pt, va); 601 moea_pte_set(pt, pvo_pt); 602 } 603 604 /* 605 * Quick sort callout for comparing memory regions. 606 */ 607 static int om_cmp(const void *a, const void *b); 608 609 static int 610 om_cmp(const void *a, const void *b) 611 { 612 const struct ofw_map *mapa; 613 const struct ofw_map *mapb; 614 615 mapa = a; 616 mapb = b; 617 if (mapa->om_pa < mapb->om_pa) 618 return (-1); 619 else if (mapa->om_pa > mapb->om_pa) 620 return (1); 621 else 622 return (0); 623 } 624 625 void 626 moea_cpu_bootstrap(int ap) 627 { 628 u_int sdr; 629 int i; 630 631 if (ap) { 632 powerpc_sync(); 633 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 634 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 635 isync(); 636 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 637 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 638 isync(); 639 } 640 641 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 642 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 643 isync(); 644 645 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 646 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 647 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 648 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 649 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 650 isync(); 651 652 for (i = 0; i < 16; i++) 653 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 654 powerpc_sync(); 655 656 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 657 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 658 isync(); 659 660 tlbia(); 661 } 662 663 void 664 moea_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 665 { 666 ihandle_t mmui; 667 phandle_t chosen, mmu; 668 int sz; 669 int i, j; 670 vm_size_t size, physsz, hwphyssz; 671 vm_offset_t pa, va, off; 672 void *dpcpu; 673 register_t msr; 674 675 /* 676 * Set up BAT0 to map the lowest 256 MB area 677 */ 678 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 679 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 680 681 /* 682 * Map PCI memory space. 683 */ 684 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 685 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 686 687 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 688 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 689 690 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 691 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 692 693 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 694 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 695 696 /* 697 * Map obio devices. 698 */ 699 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 700 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 701 702 /* 703 * Use an IBAT and a DBAT to map the bottom segment of memory 704 * where we are. Turn off instruction relocation temporarily 705 * to prevent faults while reprogramming the IBAT. 706 */ 707 msr = mfmsr(); 708 mtmsr(msr & ~PSL_IR); 709 __asm (".balign 32; \n" 710 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 711 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 712 :: "r"(battable[0].batu), "r"(battable[0].batl)); 713 mtmsr(msr); 714 715 /* map pci space */ 716 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 717 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 718 isync(); 719 720 /* set global direct map flag */ 721 hw_direct_map = 1; 722 723 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 724 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 725 726 for (i = 0; i < pregions_sz; i++) { 727 vm_offset_t pa; 728 vm_offset_t end; 729 730 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 731 pregions[i].mr_start, 732 pregions[i].mr_start + pregions[i].mr_size, 733 pregions[i].mr_size); 734 /* 735 * Install entries into the BAT table to allow all 736 * of physmem to be convered by on-demand BAT entries. 737 * The loop will sometimes set the same battable element 738 * twice, but that's fine since they won't be used for 739 * a while yet. 740 */ 741 pa = pregions[i].mr_start & 0xf0000000; 742 end = pregions[i].mr_start + pregions[i].mr_size; 743 do { 744 u_int n = pa >> ADDR_SR_SHFT; 745 746 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 747 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 748 pa += SEGMENT_LENGTH; 749 } while (pa < end); 750 } 751 752 if (PHYS_AVAIL_ENTRIES < regions_sz) 753 panic("moea_bootstrap: phys_avail too small"); 754 755 phys_avail_count = 0; 756 physsz = 0; 757 hwphyssz = 0; 758 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 759 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 760 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 761 regions[i].mr_start + regions[i].mr_size, 762 regions[i].mr_size); 763 if (hwphyssz != 0 && 764 (physsz + regions[i].mr_size) >= hwphyssz) { 765 if (physsz < hwphyssz) { 766 phys_avail[j] = regions[i].mr_start; 767 phys_avail[j + 1] = regions[i].mr_start + 768 hwphyssz - physsz; 769 physsz = hwphyssz; 770 phys_avail_count++; 771 } 772 break; 773 } 774 phys_avail[j] = regions[i].mr_start; 775 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 776 phys_avail_count++; 777 physsz += regions[i].mr_size; 778 } 779 780 /* Check for overlap with the kernel and exception vectors */ 781 for (j = 0; j < 2*phys_avail_count; j+=2) { 782 if (phys_avail[j] < EXC_LAST) 783 phys_avail[j] += EXC_LAST; 784 785 if (kernelstart >= phys_avail[j] && 786 kernelstart < phys_avail[j+1]) { 787 if (kernelend < phys_avail[j+1]) { 788 phys_avail[2*phys_avail_count] = 789 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 790 phys_avail[2*phys_avail_count + 1] = 791 phys_avail[j+1]; 792 phys_avail_count++; 793 } 794 795 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 796 } 797 798 if (kernelend >= phys_avail[j] && 799 kernelend < phys_avail[j+1]) { 800 if (kernelstart > phys_avail[j]) { 801 phys_avail[2*phys_avail_count] = phys_avail[j]; 802 phys_avail[2*phys_avail_count + 1] = 803 kernelstart & ~PAGE_MASK; 804 phys_avail_count++; 805 } 806 807 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 808 } 809 } 810 811 physmem = btoc(physsz); 812 813 /* 814 * Allocate PTEG table. 815 */ 816 #ifdef PTEGCOUNT 817 moea_pteg_count = PTEGCOUNT; 818 #else 819 moea_pteg_count = 0x1000; 820 821 while (moea_pteg_count < physmem) 822 moea_pteg_count <<= 1; 823 824 moea_pteg_count >>= 1; 825 #endif /* PTEGCOUNT */ 826 827 size = moea_pteg_count * sizeof(struct pteg); 828 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 829 size); 830 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 831 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 832 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 833 moea_pteg_mask = moea_pteg_count - 1; 834 835 /* 836 * Allocate pv/overflow lists. 837 */ 838 size = sizeof(struct pvo_head) * moea_pteg_count; 839 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 840 PAGE_SIZE); 841 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 842 for (i = 0; i < moea_pteg_count; i++) 843 LIST_INIT(&moea_pvo_table[i]); 844 845 /* 846 * Initialize the lock that synchronizes access to the pteg and pvo 847 * tables. 848 */ 849 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 850 MTX_RECURSE); 851 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 852 853 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 854 855 /* 856 * Initialise the unmanaged pvo pool. 857 */ 858 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 859 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 860 moea_bpvo_pool_index = 0; 861 862 /* 863 * Make sure kernel vsid is allocated as well as VSID 0. 864 */ 865 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 866 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 867 moea_vsid_bitmap[0] |= 1; 868 869 /* 870 * Initialize the kernel pmap (which is statically allocated). 871 */ 872 PMAP_LOCK_INIT(kernel_pmap); 873 for (i = 0; i < 16; i++) 874 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 875 CPU_FILL(&kernel_pmap->pm_active); 876 RB_INIT(&kernel_pmap->pmap_pvo); 877 878 /* 879 * Initialize the global pv list lock. 880 */ 881 rw_init(&pvh_global_lock, "pmap pv global"); 882 883 /* 884 * Set up the Open Firmware mappings 885 */ 886 chosen = OF_finddevice("/chosen"); 887 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 && 888 (mmu = OF_instance_to_package(mmui)) != -1 && 889 (sz = OF_getproplen(mmu, "translations")) != -1) { 890 translations = NULL; 891 for (i = 0; phys_avail[i] != 0; i += 2) { 892 if (phys_avail[i + 1] >= sz) { 893 translations = (struct ofw_map *)phys_avail[i]; 894 break; 895 } 896 } 897 if (translations == NULL) 898 panic("moea_bootstrap: no space to copy translations"); 899 bzero(translations, sz); 900 if (OF_getprop(mmu, "translations", translations, sz) == -1) 901 panic("moea_bootstrap: can't get ofw translations"); 902 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 903 sz /= sizeof(*translations); 904 qsort(translations, sz, sizeof (*translations), om_cmp); 905 for (i = 0; i < sz; i++) { 906 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 907 translations[i].om_pa, translations[i].om_va, 908 translations[i].om_len); 909 910 /* 911 * If the mapping is 1:1, let the RAM and device 912 * on-demand BAT tables take care of the translation. 913 */ 914 if (translations[i].om_va == translations[i].om_pa) 915 continue; 916 917 /* Enter the pages */ 918 for (off = 0; off < translations[i].om_len; 919 off += PAGE_SIZE) 920 moea_kenter(translations[i].om_va + off, 921 translations[i].om_pa + off); 922 } 923 } 924 925 /* 926 * Calculate the last available physical address. 927 */ 928 for (i = 0; phys_avail[i + 2] != 0; i += 2) 929 ; 930 Maxmem = powerpc_btop(phys_avail[i + 1]); 931 932 moea_cpu_bootstrap(0); 933 mtmsr(mfmsr() | PSL_DR | PSL_IR); 934 pmap_bootstrapped++; 935 936 /* 937 * Set the start and end of kva. 938 */ 939 virtual_avail = VM_MIN_KERNEL_ADDRESS; 940 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 941 942 /* 943 * Allocate a kernel stack with a guard page for thread0 and map it 944 * into the kernel page map. 945 */ 946 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 947 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 948 virtual_avail = va + kstack_pages * PAGE_SIZE; 949 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 950 thread0.td_kstack = va; 951 thread0.td_kstack_pages = kstack_pages; 952 for (i = 0; i < kstack_pages; i++) { 953 moea_kenter(va, pa); 954 pa += PAGE_SIZE; 955 va += PAGE_SIZE; 956 } 957 958 /* 959 * Allocate virtual address space for the message buffer. 960 */ 961 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 962 msgbufp = (struct msgbuf *)virtual_avail; 963 va = virtual_avail; 964 virtual_avail += round_page(msgbufsize); 965 while (va < virtual_avail) { 966 moea_kenter(va, pa); 967 pa += PAGE_SIZE; 968 va += PAGE_SIZE; 969 } 970 971 /* 972 * Allocate virtual address space for the dynamic percpu area. 973 */ 974 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 975 dpcpu = (void *)virtual_avail; 976 va = virtual_avail; 977 virtual_avail += DPCPU_SIZE; 978 while (va < virtual_avail) { 979 moea_kenter(va, pa); 980 pa += PAGE_SIZE; 981 va += PAGE_SIZE; 982 } 983 dpcpu_init(dpcpu, 0); 984 } 985 986 /* 987 * Activate a user pmap. The pmap must be activated before it's address 988 * space can be accessed in any way. 989 */ 990 void 991 moea_activate(struct thread *td) 992 { 993 pmap_t pm, pmr; 994 995 /* 996 * Load all the data we need up front to encourage the compiler to 997 * not issue any loads while we have interrupts disabled below. 998 */ 999 pm = &td->td_proc->p_vmspace->vm_pmap; 1000 pmr = pm->pmap_phys; 1001 1002 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1003 PCPU_SET(curpmap, pmr); 1004 1005 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1006 } 1007 1008 void 1009 moea_deactivate(struct thread *td) 1010 { 1011 pmap_t pm; 1012 1013 pm = &td->td_proc->p_vmspace->vm_pmap; 1014 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1015 PCPU_SET(curpmap, NULL); 1016 } 1017 1018 void 1019 moea_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1020 { 1021 struct pvo_entry key, *pvo; 1022 1023 PMAP_LOCK(pm); 1024 key.pvo_vaddr = sva; 1025 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1026 pvo != NULL && PVO_VADDR(pvo) < eva; 1027 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1028 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1029 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo); 1030 pvo->pvo_vaddr &= ~PVO_WIRED; 1031 pm->pm_stats.wired_count--; 1032 } 1033 PMAP_UNLOCK(pm); 1034 } 1035 1036 void 1037 moea_copy_page(vm_page_t msrc, vm_page_t mdst) 1038 { 1039 vm_offset_t dst; 1040 vm_offset_t src; 1041 1042 dst = VM_PAGE_TO_PHYS(mdst); 1043 src = VM_PAGE_TO_PHYS(msrc); 1044 1045 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1046 } 1047 1048 void 1049 moea_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1050 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1051 { 1052 void *a_cp, *b_cp; 1053 vm_offset_t a_pg_offset, b_pg_offset; 1054 int cnt; 1055 1056 while (xfersize > 0) { 1057 a_pg_offset = a_offset & PAGE_MASK; 1058 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1059 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1060 a_pg_offset; 1061 b_pg_offset = b_offset & PAGE_MASK; 1062 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1063 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1064 b_pg_offset; 1065 bcopy(a_cp, b_cp, cnt); 1066 a_offset += cnt; 1067 b_offset += cnt; 1068 xfersize -= cnt; 1069 } 1070 } 1071 1072 /* 1073 * Zero a page of physical memory by temporarily mapping it into the tlb. 1074 */ 1075 void 1076 moea_zero_page(vm_page_t m) 1077 { 1078 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m); 1079 1080 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1081 __asm __volatile("dcbz 0,%0" :: "r"(pa + off)); 1082 } 1083 1084 void 1085 moea_zero_page_area(vm_page_t m, int off, int size) 1086 { 1087 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1088 void *va = (void *)(pa + off); 1089 1090 bzero(va, size); 1091 } 1092 1093 vm_offset_t 1094 moea_quick_enter_page(vm_page_t m) 1095 { 1096 1097 return (VM_PAGE_TO_PHYS(m)); 1098 } 1099 1100 void 1101 moea_quick_remove_page(vm_offset_t addr) 1102 { 1103 } 1104 1105 boolean_t 1106 moea_page_is_mapped(vm_page_t m) 1107 { 1108 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1109 } 1110 1111 /* 1112 * Map the given physical page at the specified virtual address in the 1113 * target pmap with the protection requested. If specified the page 1114 * will be wired down. 1115 */ 1116 int 1117 moea_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1118 u_int flags, int8_t psind) 1119 { 1120 int error; 1121 1122 for (;;) { 1123 rw_wlock(&pvh_global_lock); 1124 PMAP_LOCK(pmap); 1125 error = moea_enter_locked(pmap, va, m, prot, flags, psind); 1126 rw_wunlock(&pvh_global_lock); 1127 PMAP_UNLOCK(pmap); 1128 if (error != ENOMEM) 1129 return (KERN_SUCCESS); 1130 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1131 return (KERN_RESOURCE_SHORTAGE); 1132 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1133 vm_wait(NULL); 1134 } 1135 } 1136 1137 /* 1138 * Map the given physical page at the specified virtual address in the 1139 * target pmap with the protection requested. If specified the page 1140 * will be wired down. 1141 * 1142 * The global pvh and pmap must be locked. 1143 */ 1144 static int 1145 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1146 u_int flags, int8_t psind __unused) 1147 { 1148 struct pvo_head *pvo_head; 1149 uma_zone_t zone; 1150 u_int pte_lo, pvo_flags; 1151 int error; 1152 1153 if (pmap_bootstrapped) 1154 rw_assert(&pvh_global_lock, RA_WLOCKED); 1155 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1156 if ((m->oflags & VPO_UNMANAGED) == 0) { 1157 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1158 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1159 else 1160 VM_OBJECT_ASSERT_LOCKED(m->object); 1161 } 1162 1163 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) { 1164 pvo_head = &moea_pvo_kunmanaged; 1165 zone = moea_upvo_zone; 1166 pvo_flags = 0; 1167 } else { 1168 pvo_head = vm_page_to_pvoh(m); 1169 zone = moea_mpvo_zone; 1170 pvo_flags = PVO_MANAGED; 1171 } 1172 1173 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1174 1175 if (prot & VM_PROT_WRITE) { 1176 pte_lo |= PTE_BW; 1177 if (pmap_bootstrapped && 1178 (m->oflags & VPO_UNMANAGED) == 0) 1179 vm_page_aflag_set(m, PGA_WRITEABLE); 1180 } else 1181 pte_lo |= PTE_BR; 1182 1183 if ((flags & PMAP_ENTER_WIRED) != 0) 1184 pvo_flags |= PVO_WIRED; 1185 1186 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1187 pte_lo, pvo_flags); 1188 1189 /* 1190 * Flush the real page from the instruction cache. This has be done 1191 * for all user mappings to prevent information leakage via the 1192 * instruction cache. moea_pvo_enter() returns ENOENT for the first 1193 * mapping for a page. 1194 */ 1195 if (pmap != kernel_pmap && error == ENOENT && 1196 (pte_lo & (PTE_I | PTE_G)) == 0) 1197 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1198 1199 return (error); 1200 } 1201 1202 /* 1203 * Maps a sequence of resident pages belonging to the same object. 1204 * The sequence begins with the given page m_start. This page is 1205 * mapped at the given virtual address start. Each subsequent page is 1206 * mapped at a virtual address that is offset from start by the same 1207 * amount as the page is offset from m_start within the object. The 1208 * last page in the sequence is the page with the largest offset from 1209 * m_start that can be mapped at a virtual address less than the given 1210 * virtual address end. Not every virtual page between start and end 1211 * is mapped; only those for which a resident page exists with the 1212 * corresponding offset from m_start are mapped. 1213 */ 1214 void 1215 moea_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1216 vm_page_t m_start, vm_prot_t prot) 1217 { 1218 vm_page_t m; 1219 vm_pindex_t diff, psize; 1220 1221 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1222 1223 psize = atop(end - start); 1224 m = m_start; 1225 rw_wlock(&pvh_global_lock); 1226 PMAP_LOCK(pm); 1227 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1228 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1229 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_QUICK_LOCKED, 1230 0); 1231 m = TAILQ_NEXT(m, listq); 1232 } 1233 rw_wunlock(&pvh_global_lock); 1234 PMAP_UNLOCK(pm); 1235 } 1236 1237 void 1238 moea_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1239 vm_prot_t prot) 1240 { 1241 1242 rw_wlock(&pvh_global_lock); 1243 PMAP_LOCK(pm); 1244 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1245 PMAP_ENTER_QUICK_LOCKED, 0); 1246 rw_wunlock(&pvh_global_lock); 1247 PMAP_UNLOCK(pm); 1248 } 1249 1250 vm_paddr_t 1251 moea_extract(pmap_t pm, vm_offset_t va) 1252 { 1253 struct pvo_entry *pvo; 1254 vm_paddr_t pa; 1255 1256 PMAP_LOCK(pm); 1257 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1258 if (pvo == NULL) 1259 pa = 0; 1260 else 1261 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1262 PMAP_UNLOCK(pm); 1263 return (pa); 1264 } 1265 1266 /* 1267 * Atomically extract and hold the physical page with the given 1268 * pmap and virtual address pair if that mapping permits the given 1269 * protection. 1270 */ 1271 vm_page_t 1272 moea_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1273 { 1274 struct pvo_entry *pvo; 1275 vm_page_t m; 1276 1277 m = NULL; 1278 PMAP_LOCK(pmap); 1279 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1280 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1281 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1282 (prot & VM_PROT_WRITE) == 0)) { 1283 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1284 if (!vm_page_wire_mapped(m)) 1285 m = NULL; 1286 } 1287 PMAP_UNLOCK(pmap); 1288 return (m); 1289 } 1290 1291 void 1292 moea_init() 1293 { 1294 1295 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1296 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1297 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1298 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1299 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1300 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1301 moea_initialized = TRUE; 1302 } 1303 1304 boolean_t 1305 moea_is_referenced(vm_page_t m) 1306 { 1307 boolean_t rv; 1308 1309 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1310 ("moea_is_referenced: page %p is not managed", m)); 1311 rw_wlock(&pvh_global_lock); 1312 rv = moea_query_bit(m, PTE_REF); 1313 rw_wunlock(&pvh_global_lock); 1314 return (rv); 1315 } 1316 1317 boolean_t 1318 moea_is_modified(vm_page_t m) 1319 { 1320 boolean_t rv; 1321 1322 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1323 ("moea_is_modified: page %p is not managed", m)); 1324 1325 /* 1326 * If the page is not busied then this check is racy. 1327 */ 1328 if (!pmap_page_is_write_mapped(m)) 1329 return (FALSE); 1330 1331 rw_wlock(&pvh_global_lock); 1332 rv = moea_query_bit(m, PTE_CHG); 1333 rw_wunlock(&pvh_global_lock); 1334 return (rv); 1335 } 1336 1337 boolean_t 1338 moea_is_prefaultable(pmap_t pmap, vm_offset_t va) 1339 { 1340 struct pvo_entry *pvo; 1341 boolean_t rv; 1342 1343 PMAP_LOCK(pmap); 1344 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1345 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1346 PMAP_UNLOCK(pmap); 1347 return (rv); 1348 } 1349 1350 void 1351 moea_clear_modify(vm_page_t m) 1352 { 1353 1354 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1355 ("moea_clear_modify: page %p is not managed", m)); 1356 vm_page_assert_busied(m); 1357 1358 if (!pmap_page_is_write_mapped(m)) 1359 return; 1360 rw_wlock(&pvh_global_lock); 1361 moea_clear_bit(m, PTE_CHG); 1362 rw_wunlock(&pvh_global_lock); 1363 } 1364 1365 /* 1366 * Clear the write and modified bits in each of the given page's mappings. 1367 */ 1368 void 1369 moea_remove_write(vm_page_t m) 1370 { 1371 struct pvo_entry *pvo; 1372 struct pte *pt; 1373 pmap_t pmap; 1374 u_int lo; 1375 1376 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1377 ("moea_remove_write: page %p is not managed", m)); 1378 vm_page_assert_busied(m); 1379 1380 if (!pmap_page_is_write_mapped(m)) 1381 return; 1382 rw_wlock(&pvh_global_lock); 1383 lo = moea_attr_fetch(m); 1384 powerpc_sync(); 1385 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1386 pmap = pvo->pvo_pmap; 1387 PMAP_LOCK(pmap); 1388 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1389 pt = moea_pvo_to_pte(pvo, -1); 1390 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1391 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1392 if (pt != NULL) { 1393 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1394 lo |= pvo->pvo_pte.pte.pte_lo; 1395 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1396 moea_pte_change(pt, &pvo->pvo_pte.pte, 1397 pvo->pvo_vaddr); 1398 mtx_unlock(&moea_table_mutex); 1399 } 1400 } 1401 PMAP_UNLOCK(pmap); 1402 } 1403 if ((lo & PTE_CHG) != 0) { 1404 moea_attr_clear(m, PTE_CHG); 1405 vm_page_dirty(m); 1406 } 1407 vm_page_aflag_clear(m, PGA_WRITEABLE); 1408 rw_wunlock(&pvh_global_lock); 1409 } 1410 1411 /* 1412 * moea_ts_referenced: 1413 * 1414 * Return a count of reference bits for a page, clearing those bits. 1415 * It is not necessary for every reference bit to be cleared, but it 1416 * is necessary that 0 only be returned when there are truly no 1417 * reference bits set. 1418 * 1419 * XXX: The exact number of bits to check and clear is a matter that 1420 * should be tested and standardized at some point in the future for 1421 * optimal aging of shared pages. 1422 */ 1423 int 1424 moea_ts_referenced(vm_page_t m) 1425 { 1426 int count; 1427 1428 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1429 ("moea_ts_referenced: page %p is not managed", m)); 1430 rw_wlock(&pvh_global_lock); 1431 count = moea_clear_bit(m, PTE_REF); 1432 rw_wunlock(&pvh_global_lock); 1433 return (count); 1434 } 1435 1436 /* 1437 * Modify the WIMG settings of all mappings for a page. 1438 */ 1439 void 1440 moea_page_set_memattr(vm_page_t m, vm_memattr_t ma) 1441 { 1442 struct pvo_entry *pvo; 1443 struct pvo_head *pvo_head; 1444 struct pte *pt; 1445 pmap_t pmap; 1446 u_int lo; 1447 1448 if ((m->oflags & VPO_UNMANAGED) != 0) { 1449 m->md.mdpg_cache_attrs = ma; 1450 return; 1451 } 1452 1453 rw_wlock(&pvh_global_lock); 1454 pvo_head = vm_page_to_pvoh(m); 1455 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1456 1457 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1458 pmap = pvo->pvo_pmap; 1459 PMAP_LOCK(pmap); 1460 pt = moea_pvo_to_pte(pvo, -1); 1461 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1462 pvo->pvo_pte.pte.pte_lo |= lo; 1463 if (pt != NULL) { 1464 moea_pte_change(pt, &pvo->pvo_pte.pte, 1465 pvo->pvo_vaddr); 1466 if (pvo->pvo_pmap == kernel_pmap) 1467 isync(); 1468 } 1469 mtx_unlock(&moea_table_mutex); 1470 PMAP_UNLOCK(pmap); 1471 } 1472 m->md.mdpg_cache_attrs = ma; 1473 rw_wunlock(&pvh_global_lock); 1474 } 1475 1476 /* 1477 * Map a wired page into kernel virtual address space. 1478 */ 1479 void 1480 moea_kenter(vm_offset_t va, vm_paddr_t pa) 1481 { 1482 1483 moea_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1484 } 1485 1486 void 1487 moea_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1488 { 1489 u_int pte_lo; 1490 int error; 1491 1492 #if 0 1493 if (va < VM_MIN_KERNEL_ADDRESS) 1494 panic("moea_kenter: attempt to enter non-kernel address %#x", 1495 va); 1496 #endif 1497 1498 pte_lo = moea_calc_wimg(pa, ma); 1499 1500 PMAP_LOCK(kernel_pmap); 1501 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1502 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1503 1504 if (error != 0 && error != ENOENT) 1505 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1506 pa, error); 1507 1508 PMAP_UNLOCK(kernel_pmap); 1509 } 1510 1511 /* 1512 * Extract the physical page address associated with the given kernel virtual 1513 * address. 1514 */ 1515 vm_paddr_t 1516 moea_kextract(vm_offset_t va) 1517 { 1518 struct pvo_entry *pvo; 1519 vm_paddr_t pa; 1520 1521 /* 1522 * Allow direct mappings on 32-bit OEA 1523 */ 1524 if (va < VM_MIN_KERNEL_ADDRESS) { 1525 return (va); 1526 } 1527 1528 PMAP_LOCK(kernel_pmap); 1529 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1530 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1531 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1532 PMAP_UNLOCK(kernel_pmap); 1533 return (pa); 1534 } 1535 1536 /* 1537 * Remove a wired page from kernel virtual address space. 1538 */ 1539 void 1540 moea_kremove(vm_offset_t va) 1541 { 1542 1543 moea_remove(kernel_pmap, va, va + PAGE_SIZE); 1544 } 1545 1546 /* 1547 * Provide a kernel pointer corresponding to a given userland pointer. 1548 * The returned pointer is valid until the next time this function is 1549 * called in this thread. This is used internally in copyin/copyout. 1550 */ 1551 int 1552 moea_map_user_ptr(pmap_t pm, volatile const void *uaddr, 1553 void **kaddr, size_t ulen, size_t *klen) 1554 { 1555 size_t l; 1556 register_t vsid; 1557 1558 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1559 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1560 if (l > ulen) 1561 l = ulen; 1562 if (klen) 1563 *klen = l; 1564 else if (l != ulen) 1565 return (EFAULT); 1566 1567 vsid = va_to_vsid(pm, (vm_offset_t)uaddr); 1568 1569 /* Mark segment no-execute */ 1570 vsid |= SR_N; 1571 1572 /* If we have already set this VSID, we can just return */ 1573 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid) 1574 return (0); 1575 1576 __asm __volatile("isync"); 1577 curthread->td_pcb->pcb_cpu.aim.usr_segm = 1578 (uintptr_t)uaddr >> ADDR_SR_SHFT; 1579 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid; 1580 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid)); 1581 1582 return (0); 1583 } 1584 1585 /* 1586 * Figure out where a given kernel pointer (usually in a fault) points 1587 * to from the VM's perspective, potentially remapping into userland's 1588 * address space. 1589 */ 1590 static int 1591 moea_decode_kernel_ptr(vm_offset_t addr, int *is_user, 1592 vm_offset_t *decoded_addr) 1593 { 1594 vm_offset_t user_sr; 1595 1596 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 1597 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 1598 addr &= ADDR_PIDX | ADDR_POFF; 1599 addr |= user_sr << ADDR_SR_SHFT; 1600 *decoded_addr = addr; 1601 *is_user = 1; 1602 } else { 1603 *decoded_addr = addr; 1604 *is_user = 0; 1605 } 1606 1607 return (0); 1608 } 1609 1610 /* 1611 * Map a range of physical addresses into kernel virtual address space. 1612 * 1613 * The value passed in *virt is a suggested virtual address for the mapping. 1614 * Architectures which can support a direct-mapped physical to virtual region 1615 * can return the appropriate address within that region, leaving '*virt' 1616 * unchanged. We cannot and therefore do not; *virt is updated with the 1617 * first usable address after the mapped region. 1618 */ 1619 vm_offset_t 1620 moea_map(vm_offset_t *virt, vm_paddr_t pa_start, 1621 vm_paddr_t pa_end, int prot) 1622 { 1623 vm_offset_t sva, va; 1624 1625 sva = *virt; 1626 va = sva; 1627 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1628 moea_kenter(va, pa_start); 1629 *virt = va; 1630 return (sva); 1631 } 1632 1633 /* 1634 * Returns true if the pmap's pv is one of the first 1635 * 16 pvs linked to from this page. This count may 1636 * be changed upwards or downwards in the future; it 1637 * is only necessary that true be returned for a small 1638 * subset of pmaps for proper page aging. 1639 */ 1640 boolean_t 1641 moea_page_exists_quick(pmap_t pmap, vm_page_t m) 1642 { 1643 int loops; 1644 struct pvo_entry *pvo; 1645 boolean_t rv; 1646 1647 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1648 ("moea_page_exists_quick: page %p is not managed", m)); 1649 loops = 0; 1650 rv = FALSE; 1651 rw_wlock(&pvh_global_lock); 1652 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1653 if (pvo->pvo_pmap == pmap) { 1654 rv = TRUE; 1655 break; 1656 } 1657 if (++loops >= 16) 1658 break; 1659 } 1660 rw_wunlock(&pvh_global_lock); 1661 return (rv); 1662 } 1663 1664 void 1665 moea_page_init(vm_page_t m) 1666 { 1667 1668 m->md.mdpg_attrs = 0; 1669 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 1670 LIST_INIT(&m->md.mdpg_pvoh); 1671 } 1672 1673 /* 1674 * Return the number of managed mappings to the given physical page 1675 * that are wired. 1676 */ 1677 int 1678 moea_page_wired_mappings(vm_page_t m) 1679 { 1680 struct pvo_entry *pvo; 1681 int count; 1682 1683 count = 0; 1684 if ((m->oflags & VPO_UNMANAGED) != 0) 1685 return (count); 1686 rw_wlock(&pvh_global_lock); 1687 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1688 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1689 count++; 1690 rw_wunlock(&pvh_global_lock); 1691 return (count); 1692 } 1693 1694 static u_int moea_vsidcontext; 1695 1696 int 1697 moea_pinit(pmap_t pmap) 1698 { 1699 int i, mask; 1700 u_int entropy; 1701 1702 RB_INIT(&pmap->pmap_pvo); 1703 1704 entropy = 0; 1705 __asm __volatile("mftb %0" : "=r"(entropy)); 1706 1707 if ((pmap->pmap_phys = (pmap_t)moea_kextract((vm_offset_t)pmap)) 1708 == NULL) { 1709 pmap->pmap_phys = pmap; 1710 } 1711 1712 1713 mtx_lock(&moea_vsid_mutex); 1714 /* 1715 * Allocate some segment registers for this pmap. 1716 */ 1717 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1718 u_int hash, n; 1719 1720 /* 1721 * Create a new value by mutiplying by a prime and adding in 1722 * entropy from the timebase register. This is to make the 1723 * VSID more random so that the PT hash function collides 1724 * less often. (Note that the prime casues gcc to do shifts 1725 * instead of a multiply.) 1726 */ 1727 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1728 hash = moea_vsidcontext & (NPMAPS - 1); 1729 if (hash == 0) /* 0 is special, avoid it */ 1730 continue; 1731 n = hash >> 5; 1732 mask = 1 << (hash & (VSID_NBPW - 1)); 1733 hash = (moea_vsidcontext & 0xfffff); 1734 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1735 /* anything free in this bucket? */ 1736 if (moea_vsid_bitmap[n] == 0xffffffff) { 1737 entropy = (moea_vsidcontext >> 20); 1738 continue; 1739 } 1740 i = ffs(~moea_vsid_bitmap[n]) - 1; 1741 mask = 1 << i; 1742 hash &= rounddown2(0xfffff, VSID_NBPW); 1743 hash |= i; 1744 } 1745 KASSERT(!(moea_vsid_bitmap[n] & mask), 1746 ("Allocating in-use VSID group %#x\n", hash)); 1747 moea_vsid_bitmap[n] |= mask; 1748 for (i = 0; i < 16; i++) 1749 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1750 mtx_unlock(&moea_vsid_mutex); 1751 return (1); 1752 } 1753 1754 mtx_unlock(&moea_vsid_mutex); 1755 panic("moea_pinit: out of segments"); 1756 } 1757 1758 /* 1759 * Initialize the pmap associated with process 0. 1760 */ 1761 void 1762 moea_pinit0(pmap_t pm) 1763 { 1764 1765 PMAP_LOCK_INIT(pm); 1766 moea_pinit(pm); 1767 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1768 } 1769 1770 /* 1771 * Set the physical protection on the specified range of this map as requested. 1772 */ 1773 void 1774 moea_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1775 vm_prot_t prot) 1776 { 1777 struct pvo_entry *pvo, *tpvo, key; 1778 struct pte *pt; 1779 1780 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1781 ("moea_protect: non current pmap")); 1782 1783 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1784 moea_remove(pm, sva, eva); 1785 return; 1786 } 1787 1788 rw_wlock(&pvh_global_lock); 1789 PMAP_LOCK(pm); 1790 key.pvo_vaddr = sva; 1791 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1792 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1793 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1794 1795 /* 1796 * Grab the PTE pointer before we diddle with the cached PTE 1797 * copy. 1798 */ 1799 pt = moea_pvo_to_pte(pvo, -1); 1800 /* 1801 * Change the protection of the page. 1802 */ 1803 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1804 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1805 1806 /* 1807 * If the PVO is in the page table, update that pte as well. 1808 */ 1809 if (pt != NULL) { 1810 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1811 mtx_unlock(&moea_table_mutex); 1812 } 1813 } 1814 rw_wunlock(&pvh_global_lock); 1815 PMAP_UNLOCK(pm); 1816 } 1817 1818 /* 1819 * Map a list of wired pages into kernel virtual address space. This is 1820 * intended for temporary mappings which do not need page modification or 1821 * references recorded. Existing mappings in the region are overwritten. 1822 */ 1823 void 1824 moea_qenter(vm_offset_t sva, vm_page_t *m, int count) 1825 { 1826 vm_offset_t va; 1827 1828 va = sva; 1829 while (count-- > 0) { 1830 moea_kenter(va, VM_PAGE_TO_PHYS(*m)); 1831 va += PAGE_SIZE; 1832 m++; 1833 } 1834 } 1835 1836 /* 1837 * Remove page mappings from kernel virtual address space. Intended for 1838 * temporary mappings entered by moea_qenter. 1839 */ 1840 void 1841 moea_qremove(vm_offset_t sva, int count) 1842 { 1843 vm_offset_t va; 1844 1845 va = sva; 1846 while (count-- > 0) { 1847 moea_kremove(va); 1848 va += PAGE_SIZE; 1849 } 1850 } 1851 1852 void 1853 moea_release(pmap_t pmap) 1854 { 1855 int idx, mask; 1856 1857 /* 1858 * Free segment register's VSID 1859 */ 1860 if (pmap->pm_sr[0] == 0) 1861 panic("moea_release"); 1862 1863 mtx_lock(&moea_vsid_mutex); 1864 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1865 mask = 1 << (idx % VSID_NBPW); 1866 idx /= VSID_NBPW; 1867 moea_vsid_bitmap[idx] &= ~mask; 1868 mtx_unlock(&moea_vsid_mutex); 1869 } 1870 1871 /* 1872 * Remove the given range of addresses from the specified map. 1873 */ 1874 void 1875 moea_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1876 { 1877 struct pvo_entry *pvo, *tpvo, key; 1878 1879 rw_wlock(&pvh_global_lock); 1880 PMAP_LOCK(pm); 1881 key.pvo_vaddr = sva; 1882 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1883 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 1884 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 1885 moea_pvo_remove(pvo, -1); 1886 } 1887 PMAP_UNLOCK(pm); 1888 rw_wunlock(&pvh_global_lock); 1889 } 1890 1891 /* 1892 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1893 * will reflect changes in pte's back to the vm_page. 1894 */ 1895 void 1896 moea_remove_all(vm_page_t m) 1897 { 1898 struct pvo_head *pvo_head; 1899 struct pvo_entry *pvo, *next_pvo; 1900 pmap_t pmap; 1901 1902 rw_wlock(&pvh_global_lock); 1903 pvo_head = vm_page_to_pvoh(m); 1904 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1905 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1906 1907 pmap = pvo->pvo_pmap; 1908 PMAP_LOCK(pmap); 1909 moea_pvo_remove(pvo, -1); 1910 PMAP_UNLOCK(pmap); 1911 } 1912 if ((m->a.flags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) { 1913 moea_attr_clear(m, PTE_CHG); 1914 vm_page_dirty(m); 1915 } 1916 vm_page_aflag_clear(m, PGA_WRITEABLE); 1917 rw_wunlock(&pvh_global_lock); 1918 } 1919 1920 /* 1921 * Allocate a physical page of memory directly from the phys_avail map. 1922 * Can only be called from moea_bootstrap before avail start and end are 1923 * calculated. 1924 */ 1925 static vm_offset_t 1926 moea_bootstrap_alloc(vm_size_t size, u_int align) 1927 { 1928 vm_offset_t s, e; 1929 int i, j; 1930 1931 size = round_page(size); 1932 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1933 if (align != 0) 1934 s = roundup2(phys_avail[i], align); 1935 else 1936 s = phys_avail[i]; 1937 e = s + size; 1938 1939 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1940 continue; 1941 1942 if (s == phys_avail[i]) { 1943 phys_avail[i] += size; 1944 } else if (e == phys_avail[i + 1]) { 1945 phys_avail[i + 1] -= size; 1946 } else { 1947 for (j = phys_avail_count * 2; j > i; j -= 2) { 1948 phys_avail[j] = phys_avail[j - 2]; 1949 phys_avail[j + 1] = phys_avail[j - 1]; 1950 } 1951 1952 phys_avail[i + 3] = phys_avail[i + 1]; 1953 phys_avail[i + 1] = s; 1954 phys_avail[i + 2] = e; 1955 phys_avail_count++; 1956 } 1957 1958 return (s); 1959 } 1960 panic("moea_bootstrap_alloc: could not allocate memory"); 1961 } 1962 1963 static void 1964 moea_syncicache(vm_paddr_t pa, vm_size_t len) 1965 { 1966 __syncicache((void *)pa, len); 1967 } 1968 1969 static int 1970 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1971 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags) 1972 { 1973 struct pvo_entry *pvo; 1974 u_int sr; 1975 int first; 1976 u_int ptegidx; 1977 int i; 1978 int bootstrap; 1979 1980 moea_pvo_enter_calls++; 1981 first = 0; 1982 bootstrap = 0; 1983 1984 /* 1985 * Compute the PTE Group index. 1986 */ 1987 va &= ~ADDR_POFF; 1988 sr = va_to_sr(pm->pm_sr, va); 1989 ptegidx = va_to_pteg(sr, va); 1990 1991 /* 1992 * Remove any existing mapping for this page. Reuse the pvo entry if 1993 * there is a mapping. 1994 */ 1995 mtx_lock(&moea_table_mutex); 1996 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1997 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1998 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1999 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 2000 (pte_lo & PTE_PP)) { 2001 /* 2002 * The PTE is not changing. Instead, this may 2003 * be a request to change the mapping's wired 2004 * attribute. 2005 */ 2006 mtx_unlock(&moea_table_mutex); 2007 if ((flags & PVO_WIRED) != 0 && 2008 (pvo->pvo_vaddr & PVO_WIRED) == 0) { 2009 pvo->pvo_vaddr |= PVO_WIRED; 2010 pm->pm_stats.wired_count++; 2011 } else if ((flags & PVO_WIRED) == 0 && 2012 (pvo->pvo_vaddr & PVO_WIRED) != 0) { 2013 pvo->pvo_vaddr &= ~PVO_WIRED; 2014 pm->pm_stats.wired_count--; 2015 } 2016 return (0); 2017 } 2018 moea_pvo_remove(pvo, -1); 2019 break; 2020 } 2021 } 2022 2023 /* 2024 * If we aren't overwriting a mapping, try to allocate. 2025 */ 2026 if (moea_initialized) { 2027 pvo = uma_zalloc(zone, M_NOWAIT); 2028 } else { 2029 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 2030 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 2031 moea_bpvo_pool_index, BPVO_POOL_SIZE, 2032 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 2033 } 2034 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 2035 moea_bpvo_pool_index++; 2036 bootstrap = 1; 2037 } 2038 2039 if (pvo == NULL) { 2040 mtx_unlock(&moea_table_mutex); 2041 return (ENOMEM); 2042 } 2043 2044 moea_pvo_entries++; 2045 pvo->pvo_vaddr = va; 2046 pvo->pvo_pmap = pm; 2047 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 2048 pvo->pvo_vaddr &= ~ADDR_POFF; 2049 if (flags & PVO_WIRED) 2050 pvo->pvo_vaddr |= PVO_WIRED; 2051 if (pvo_head != &moea_pvo_kunmanaged) 2052 pvo->pvo_vaddr |= PVO_MANAGED; 2053 if (bootstrap) 2054 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 2055 2056 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 2057 2058 /* 2059 * Add to pmap list 2060 */ 2061 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo); 2062 2063 /* 2064 * Remember if the list was empty and therefore will be the first 2065 * item. 2066 */ 2067 if (LIST_FIRST(pvo_head) == NULL) 2068 first = 1; 2069 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2070 2071 if (pvo->pvo_vaddr & PVO_WIRED) 2072 pm->pm_stats.wired_count++; 2073 pm->pm_stats.resident_count++; 2074 2075 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2076 KASSERT(i < 8, ("Invalid PTE index")); 2077 if (i >= 0) { 2078 PVO_PTEGIDX_SET(pvo, i); 2079 } else { 2080 panic("moea_pvo_enter: overflow"); 2081 moea_pte_overflow++; 2082 } 2083 mtx_unlock(&moea_table_mutex); 2084 2085 return (first ? ENOENT : 0); 2086 } 2087 2088 static void 2089 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 2090 { 2091 struct pte *pt; 2092 2093 /* 2094 * If there is an active pte entry, we need to deactivate it (and 2095 * save the ref & cfg bits). 2096 */ 2097 pt = moea_pvo_to_pte(pvo, pteidx); 2098 if (pt != NULL) { 2099 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 2100 mtx_unlock(&moea_table_mutex); 2101 PVO_PTEGIDX_CLR(pvo); 2102 } else { 2103 moea_pte_overflow--; 2104 } 2105 2106 /* 2107 * Update our statistics. 2108 */ 2109 pvo->pvo_pmap->pm_stats.resident_count--; 2110 if (pvo->pvo_vaddr & PVO_WIRED) 2111 pvo->pvo_pmap->pm_stats.wired_count--; 2112 2113 /* 2114 * Remove this PVO from the PV and pmap lists. 2115 */ 2116 LIST_REMOVE(pvo, pvo_vlink); 2117 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2118 2119 /* 2120 * Save the REF/CHG bits into their cache if the page is managed. 2121 * Clear PGA_WRITEABLE if all mappings of the page have been removed. 2122 */ 2123 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) { 2124 struct vm_page *pg; 2125 2126 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2127 if (pg != NULL) { 2128 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2129 (PTE_REF | PTE_CHG)); 2130 if (LIST_EMPTY(&pg->md.mdpg_pvoh)) 2131 vm_page_aflag_clear(pg, PGA_WRITEABLE); 2132 } 2133 } 2134 2135 /* 2136 * Remove this from the overflow list and return it to the pool 2137 * if we aren't going to reuse it. 2138 */ 2139 LIST_REMOVE(pvo, pvo_olink); 2140 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2141 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2142 moea_upvo_zone, pvo); 2143 moea_pvo_entries--; 2144 moea_pvo_remove_calls++; 2145 } 2146 2147 static __inline int 2148 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2149 { 2150 int pteidx; 2151 2152 /* 2153 * We can find the actual pte entry without searching by grabbing 2154 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2155 * noticing the HID bit. 2156 */ 2157 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2158 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2159 pteidx ^= moea_pteg_mask * 8; 2160 2161 return (pteidx); 2162 } 2163 2164 static struct pvo_entry * 2165 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2166 { 2167 struct pvo_entry *pvo; 2168 int ptegidx; 2169 u_int sr; 2170 2171 va &= ~ADDR_POFF; 2172 sr = va_to_sr(pm->pm_sr, va); 2173 ptegidx = va_to_pteg(sr, va); 2174 2175 mtx_lock(&moea_table_mutex); 2176 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2177 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2178 if (pteidx_p) 2179 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2180 break; 2181 } 2182 } 2183 mtx_unlock(&moea_table_mutex); 2184 2185 return (pvo); 2186 } 2187 2188 static struct pte * 2189 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2190 { 2191 struct pte *pt; 2192 2193 /* 2194 * If we haven't been supplied the ptegidx, calculate it. 2195 */ 2196 if (pteidx == -1) { 2197 int ptegidx; 2198 u_int sr; 2199 2200 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2201 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2202 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2203 } 2204 2205 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2206 mtx_lock(&moea_table_mutex); 2207 2208 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2209 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2210 "valid pte index", pvo); 2211 } 2212 2213 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2214 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2215 "pvo but no valid pte", pvo); 2216 } 2217 2218 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2219 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2220 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2221 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2222 } 2223 2224 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2225 != 0) { 2226 panic("moea_pvo_to_pte: pvo %p pte does not match " 2227 "pte %p in moea_pteg_table", pvo, pt); 2228 } 2229 2230 mtx_assert(&moea_table_mutex, MA_OWNED); 2231 return (pt); 2232 } 2233 2234 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2235 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2236 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2237 } 2238 2239 mtx_unlock(&moea_table_mutex); 2240 return (NULL); 2241 } 2242 2243 /* 2244 * XXX: THIS STUFF SHOULD BE IN pte.c? 2245 */ 2246 int 2247 moea_pte_spill(vm_offset_t addr) 2248 { 2249 struct pvo_entry *source_pvo, *victim_pvo; 2250 struct pvo_entry *pvo; 2251 int ptegidx, i, j; 2252 u_int sr; 2253 struct pteg *pteg; 2254 struct pte *pt; 2255 2256 moea_pte_spills++; 2257 2258 sr = mfsrin(addr); 2259 ptegidx = va_to_pteg(sr, addr); 2260 2261 /* 2262 * Have to substitute some entry. Use the primary hash for this. 2263 * Use low bits of timebase as random generator. 2264 */ 2265 pteg = &moea_pteg_table[ptegidx]; 2266 mtx_lock(&moea_table_mutex); 2267 __asm __volatile("mftb %0" : "=r"(i)); 2268 i &= 7; 2269 pt = &pteg->pt[i]; 2270 2271 source_pvo = NULL; 2272 victim_pvo = NULL; 2273 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2274 /* 2275 * We need to find a pvo entry for this address. 2276 */ 2277 if (source_pvo == NULL && 2278 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2279 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2280 /* 2281 * Now found an entry to be spilled into the pteg. 2282 * The PTE is now valid, so we know it's active. 2283 */ 2284 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2285 2286 if (j >= 0) { 2287 PVO_PTEGIDX_SET(pvo, j); 2288 moea_pte_overflow--; 2289 mtx_unlock(&moea_table_mutex); 2290 return (1); 2291 } 2292 2293 source_pvo = pvo; 2294 2295 if (victim_pvo != NULL) 2296 break; 2297 } 2298 2299 /* 2300 * We also need the pvo entry of the victim we are replacing 2301 * so save the R & C bits of the PTE. 2302 */ 2303 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2304 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2305 victim_pvo = pvo; 2306 if (source_pvo != NULL) 2307 break; 2308 } 2309 } 2310 2311 if (source_pvo == NULL) { 2312 mtx_unlock(&moea_table_mutex); 2313 return (0); 2314 } 2315 2316 if (victim_pvo == NULL) { 2317 if ((pt->pte_hi & PTE_HID) == 0) 2318 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2319 "entry", pt); 2320 2321 /* 2322 * If this is a secondary PTE, we need to search it's primary 2323 * pvo bucket for the matching PVO. 2324 */ 2325 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2326 pvo_olink) { 2327 /* 2328 * We also need the pvo entry of the victim we are 2329 * replacing so save the R & C bits of the PTE. 2330 */ 2331 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2332 victim_pvo = pvo; 2333 break; 2334 } 2335 } 2336 2337 if (victim_pvo == NULL) 2338 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2339 "entry", pt); 2340 } 2341 2342 /* 2343 * We are invalidating the TLB entry for the EA we are replacing even 2344 * though it's valid. If we don't, we lose any ref/chg bit changes 2345 * contained in the TLB entry. 2346 */ 2347 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2348 2349 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2350 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2351 2352 PVO_PTEGIDX_CLR(victim_pvo); 2353 PVO_PTEGIDX_SET(source_pvo, i); 2354 moea_pte_replacements++; 2355 2356 mtx_unlock(&moea_table_mutex); 2357 return (1); 2358 } 2359 2360 static __inline struct pvo_entry * 2361 moea_pte_spillable_ident(u_int ptegidx) 2362 { 2363 struct pte *pt; 2364 struct pvo_entry *pvo_walk, *pvo = NULL; 2365 2366 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) { 2367 if (pvo_walk->pvo_vaddr & PVO_WIRED) 2368 continue; 2369 2370 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID)) 2371 continue; 2372 2373 pt = moea_pvo_to_pte(pvo_walk, -1); 2374 2375 if (pt == NULL) 2376 continue; 2377 2378 pvo = pvo_walk; 2379 2380 mtx_unlock(&moea_table_mutex); 2381 if (!(pt->pte_lo & PTE_REF)) 2382 return (pvo_walk); 2383 } 2384 2385 return (pvo); 2386 } 2387 2388 static int 2389 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2390 { 2391 struct pte *pt; 2392 struct pvo_entry *victim_pvo; 2393 int i; 2394 int victim_idx; 2395 u_int pteg_bkpidx = ptegidx; 2396 2397 mtx_assert(&moea_table_mutex, MA_OWNED); 2398 2399 /* 2400 * First try primary hash. 2401 */ 2402 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2403 if ((pt->pte_hi & PTE_VALID) == 0) { 2404 pvo_pt->pte_hi &= ~PTE_HID; 2405 moea_pte_set(pt, pvo_pt); 2406 return (i); 2407 } 2408 } 2409 2410 /* 2411 * Now try secondary hash. 2412 */ 2413 ptegidx ^= moea_pteg_mask; 2414 2415 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2416 if ((pt->pte_hi & PTE_VALID) == 0) { 2417 pvo_pt->pte_hi |= PTE_HID; 2418 moea_pte_set(pt, pvo_pt); 2419 return (i); 2420 } 2421 } 2422 2423 /* Try again, but this time try to force a PTE out. */ 2424 ptegidx = pteg_bkpidx; 2425 2426 victim_pvo = moea_pte_spillable_ident(ptegidx); 2427 if (victim_pvo == NULL) { 2428 ptegidx ^= moea_pteg_mask; 2429 victim_pvo = moea_pte_spillable_ident(ptegidx); 2430 } 2431 2432 if (victim_pvo == NULL) { 2433 panic("moea_pte_insert: overflow"); 2434 return (-1); 2435 } 2436 2437 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx); 2438 2439 if (pteg_bkpidx == ptegidx) 2440 pvo_pt->pte_hi &= ~PTE_HID; 2441 else 2442 pvo_pt->pte_hi |= PTE_HID; 2443 2444 /* 2445 * Synchronize the sacrifice PTE with its PVO, then mark both 2446 * invalid. The PVO will be reused when/if the VM system comes 2447 * here after a fault. 2448 */ 2449 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7]; 2450 2451 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi) 2452 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi); 2453 2454 /* 2455 * Set the new PTE. 2456 */ 2457 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2458 PVO_PTEGIDX_CLR(victim_pvo); 2459 moea_pte_overflow++; 2460 moea_pte_set(pt, pvo_pt); 2461 2462 return (victim_idx & 7); 2463 } 2464 2465 static boolean_t 2466 moea_query_bit(vm_page_t m, int ptebit) 2467 { 2468 struct pvo_entry *pvo; 2469 struct pte *pt; 2470 2471 rw_assert(&pvh_global_lock, RA_WLOCKED); 2472 if (moea_attr_fetch(m) & ptebit) 2473 return (TRUE); 2474 2475 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2476 2477 /* 2478 * See if we saved the bit off. If so, cache it and return 2479 * success. 2480 */ 2481 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2482 moea_attr_save(m, ptebit); 2483 return (TRUE); 2484 } 2485 } 2486 2487 /* 2488 * No luck, now go through the hard part of looking at the PTEs 2489 * themselves. Sync so that any pending REF/CHG bits are flushed to 2490 * the PTEs. 2491 */ 2492 powerpc_sync(); 2493 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2494 2495 /* 2496 * See if this pvo has a valid PTE. if so, fetch the 2497 * REF/CHG bits from the valid PTE. If the appropriate 2498 * ptebit is set, cache it and return success. 2499 */ 2500 pt = moea_pvo_to_pte(pvo, -1); 2501 if (pt != NULL) { 2502 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2503 mtx_unlock(&moea_table_mutex); 2504 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2505 moea_attr_save(m, ptebit); 2506 return (TRUE); 2507 } 2508 } 2509 } 2510 2511 return (FALSE); 2512 } 2513 2514 static u_int 2515 moea_clear_bit(vm_page_t m, int ptebit) 2516 { 2517 u_int count; 2518 struct pvo_entry *pvo; 2519 struct pte *pt; 2520 2521 rw_assert(&pvh_global_lock, RA_WLOCKED); 2522 2523 /* 2524 * Clear the cached value. 2525 */ 2526 moea_attr_clear(m, ptebit); 2527 2528 /* 2529 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2530 * we can reset the right ones). note that since the pvo entries and 2531 * list heads are accessed via BAT0 and are never placed in the page 2532 * table, we don't have to worry about further accesses setting the 2533 * REF/CHG bits. 2534 */ 2535 powerpc_sync(); 2536 2537 /* 2538 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2539 * valid pte clear the ptebit from the valid pte. 2540 */ 2541 count = 0; 2542 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2543 pt = moea_pvo_to_pte(pvo, -1); 2544 if (pt != NULL) { 2545 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2546 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2547 count++; 2548 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2549 } 2550 mtx_unlock(&moea_table_mutex); 2551 } 2552 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2553 } 2554 2555 return (count); 2556 } 2557 2558 /* 2559 * Return true if the physical range is encompassed by the battable[idx] 2560 */ 2561 static int 2562 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size) 2563 { 2564 u_int prot; 2565 u_int32_t start; 2566 u_int32_t end; 2567 u_int32_t bat_ble; 2568 2569 /* 2570 * Return immediately if not a valid mapping 2571 */ 2572 if (!(battable[idx].batu & BAT_Vs)) 2573 return (EINVAL); 2574 2575 /* 2576 * The BAT entry must be cache-inhibited, guarded, and r/w 2577 * so it can function as an i/o page 2578 */ 2579 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2580 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2581 return (EPERM); 2582 2583 /* 2584 * The address should be within the BAT range. Assume that the 2585 * start address in the BAT has the correct alignment (thus 2586 * not requiring masking) 2587 */ 2588 start = battable[idx].batl & BAT_PBS; 2589 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2590 end = start | (bat_ble << 15) | 0x7fff; 2591 2592 if ((pa < start) || ((pa + size) > end)) 2593 return (ERANGE); 2594 2595 return (0); 2596 } 2597 2598 boolean_t 2599 moea_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2600 { 2601 int i; 2602 2603 /* 2604 * This currently does not work for entries that 2605 * overlap 256M BAT segments. 2606 */ 2607 2608 for(i = 0; i < 16; i++) 2609 if (moea_bat_mapped(i, pa, size) == 0) 2610 return (0); 2611 2612 return (EFAULT); 2613 } 2614 2615 /* 2616 * Map a set of physical memory pages into the kernel virtual 2617 * address space. Return a pointer to where it is mapped. This 2618 * routine is intended to be used for mapping device memory, 2619 * NOT real memory. 2620 */ 2621 void * 2622 moea_mapdev(vm_paddr_t pa, vm_size_t size) 2623 { 2624 2625 return (moea_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT)); 2626 } 2627 2628 void * 2629 moea_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2630 { 2631 vm_offset_t va, tmpva, ppa, offset; 2632 int i; 2633 2634 ppa = trunc_page(pa); 2635 offset = pa & PAGE_MASK; 2636 size = roundup(offset + size, PAGE_SIZE); 2637 2638 /* 2639 * If the physical address lies within a valid BAT table entry, 2640 * return the 1:1 mapping. This currently doesn't work 2641 * for regions that overlap 256M BAT segments. 2642 */ 2643 for (i = 0; i < 16; i++) { 2644 if (moea_bat_mapped(i, pa, size) == 0) 2645 return ((void *) pa); 2646 } 2647 2648 va = kva_alloc(size); 2649 if (!va) 2650 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2651 2652 for (tmpva = va; size > 0;) { 2653 moea_kenter_attr(tmpva, ppa, ma); 2654 tlbie(tmpva); 2655 size -= PAGE_SIZE; 2656 tmpva += PAGE_SIZE; 2657 ppa += PAGE_SIZE; 2658 } 2659 2660 return ((void *)(va + offset)); 2661 } 2662 2663 void 2664 moea_unmapdev(vm_offset_t va, vm_size_t size) 2665 { 2666 vm_offset_t base, offset; 2667 2668 /* 2669 * If this is outside kernel virtual space, then it's a 2670 * battable entry and doesn't require unmapping 2671 */ 2672 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2673 base = trunc_page(va); 2674 offset = va & PAGE_MASK; 2675 size = roundup(offset + size, PAGE_SIZE); 2676 kva_free(base, size); 2677 } 2678 } 2679 2680 static void 2681 moea_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2682 { 2683 struct pvo_entry *pvo; 2684 vm_offset_t lim; 2685 vm_paddr_t pa; 2686 vm_size_t len; 2687 2688 PMAP_LOCK(pm); 2689 while (sz > 0) { 2690 lim = round_page(va + 1); 2691 len = MIN(lim - va, sz); 2692 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2693 if (pvo != NULL) { 2694 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2695 (va & ADDR_POFF); 2696 moea_syncicache(pa, len); 2697 } 2698 va += len; 2699 sz -= len; 2700 } 2701 PMAP_UNLOCK(pm); 2702 } 2703 2704 void 2705 moea_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2706 { 2707 2708 *va = (void *)pa; 2709 } 2710 2711 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2712 2713 void 2714 moea_scan_init() 2715 { 2716 struct pvo_entry *pvo; 2717 vm_offset_t va; 2718 int i; 2719 2720 if (!do_minidump) { 2721 /* Initialize phys. segments for dumpsys(). */ 2722 memset(&dump_map, 0, sizeof(dump_map)); 2723 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2724 for (i = 0; i < pregions_sz; i++) { 2725 dump_map[i].pa_start = pregions[i].mr_start; 2726 dump_map[i].pa_size = pregions[i].mr_size; 2727 } 2728 return; 2729 } 2730 2731 /* Virtual segments for minidumps: */ 2732 memset(&dump_map, 0, sizeof(dump_map)); 2733 2734 /* 1st: kernel .data and .bss. */ 2735 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2736 dump_map[0].pa_size = 2737 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2738 2739 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2740 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2741 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2742 2743 /* 3rd: kernel VM. */ 2744 va = dump_map[1].pa_start + dump_map[1].pa_size; 2745 /* Find start of next chunk (from va). */ 2746 while (va < virtual_end) { 2747 /* Don't dump the buffer cache. */ 2748 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2749 va = kmi.buffer_eva; 2750 continue; 2751 } 2752 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 2753 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2754 break; 2755 va += PAGE_SIZE; 2756 } 2757 if (va < virtual_end) { 2758 dump_map[2].pa_start = va; 2759 va += PAGE_SIZE; 2760 /* Find last page in chunk. */ 2761 while (va < virtual_end) { 2762 /* Don't run into the buffer cache. */ 2763 if (va == kmi.buffer_sva) 2764 break; 2765 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, 2766 NULL); 2767 if (pvo == NULL || 2768 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID)) 2769 break; 2770 va += PAGE_SIZE; 2771 } 2772 dump_map[2].pa_size = va - dump_map[2].pa_start; 2773 } 2774 } 2775