1 /*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 38 * Copyright (C) 1995, 1996 TooLs GmbH. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by TooLs GmbH. 52 * 4. The name of TooLs GmbH may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $ 67 */ 68 /*- 69 * Copyright (C) 2001 Benno Rice. 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 /* 97 * Manages physical address maps. 98 * 99 * In addition to hardware address maps, this module is called upon to 100 * provide software-use-only maps which may or may not be stored in the 101 * same form as hardware maps. These pseudo-maps are used to store 102 * intermediate results from copy operations to and from address spaces. 103 * 104 * Since the information managed by this module is also stored by the 105 * logical address mapping module, this module may throw away valid virtual 106 * to physical mappings at almost any time. However, invalidations of 107 * mappings must be done as requested. 108 * 109 * In order to cope with hardware architectures which make virtual to 110 * physical map invalidates expensive, this module may delay invalidate 111 * reduced protection operations until such time as they are actually 112 * necessary. This module is given full information as to which processors 113 * are currently using which maps, and to when physical maps must be made 114 * correct. 115 */ 116 117 #include "opt_kstack_pages.h" 118 119 #include <sys/param.h> 120 #include <sys/kernel.h> 121 #include <sys/ktr.h> 122 #include <sys/lock.h> 123 #include <sys/msgbuf.h> 124 #include <sys/mutex.h> 125 #include <sys/proc.h> 126 #include <sys/sysctl.h> 127 #include <sys/systm.h> 128 #include <sys/vmmeter.h> 129 130 #include <dev/ofw/openfirm.h> 131 132 #include <vm/vm.h> 133 #include <vm/vm_param.h> 134 #include <vm/vm_kern.h> 135 #include <vm/vm_page.h> 136 #include <vm/vm_map.h> 137 #include <vm/vm_object.h> 138 #include <vm/vm_extern.h> 139 #include <vm/vm_pageout.h> 140 #include <vm/vm_pager.h> 141 #include <vm/uma.h> 142 143 #include <machine/cpu.h> 144 #include <machine/platform.h> 145 #include <machine/bat.h> 146 #include <machine/frame.h> 147 #include <machine/md_var.h> 148 #include <machine/psl.h> 149 #include <machine/pte.h> 150 #include <machine/smp.h> 151 #include <machine/sr.h> 152 #include <machine/mmuvar.h> 153 154 #include "mmu_if.h" 155 156 #define MOEA_DEBUG 157 158 #define TODO panic("%s: not implemented", __func__); 159 160 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 161 #define VSID_TO_SR(vsid) ((vsid) & 0xf) 162 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 163 164 #define MOEA_PVO_CHECK(pvo) 165 166 struct ofw_map { 167 vm_offset_t om_va; 168 vm_size_t om_len; 169 vm_offset_t om_pa; 170 u_int om_mode; 171 }; 172 173 /* 174 * Map of physical memory regions. 175 */ 176 static struct mem_region *regions; 177 static struct mem_region *pregions; 178 static u_int phys_avail_count; 179 static int regions_sz, pregions_sz; 180 static struct ofw_map *translations; 181 182 /* 183 * Lock for the pteg and pvo tables. 184 */ 185 struct mtx moea_table_mutex; 186 struct mtx moea_vsid_mutex; 187 188 /* tlbie instruction synchronization */ 189 static struct mtx tlbie_mtx; 190 191 /* 192 * PTEG data. 193 */ 194 static struct pteg *moea_pteg_table; 195 u_int moea_pteg_count; 196 u_int moea_pteg_mask; 197 198 /* 199 * PVO data. 200 */ 201 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */ 202 struct pvo_head moea_pvo_kunmanaged = 203 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */ 204 205 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */ 206 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */ 207 208 #define BPVO_POOL_SIZE 32768 209 static struct pvo_entry *moea_bpvo_pool; 210 static int moea_bpvo_pool_index = 0; 211 212 #define VSID_NBPW (sizeof(u_int32_t) * 8) 213 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW]; 214 215 static boolean_t moea_initialized = FALSE; 216 217 /* 218 * Statistics. 219 */ 220 u_int moea_pte_valid = 0; 221 u_int moea_pte_overflow = 0; 222 u_int moea_pte_replacements = 0; 223 u_int moea_pvo_entries = 0; 224 u_int moea_pvo_enter_calls = 0; 225 u_int moea_pvo_remove_calls = 0; 226 u_int moea_pte_spills = 0; 227 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid, 228 0, ""); 229 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD, 230 &moea_pte_overflow, 0, ""); 231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD, 232 &moea_pte_replacements, 0, ""); 233 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries, 234 0, ""); 235 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD, 236 &moea_pvo_enter_calls, 0, ""); 237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD, 238 &moea_pvo_remove_calls, 0, ""); 239 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD, 240 &moea_pte_spills, 0, ""); 241 242 /* 243 * Allocate physical memory for use in moea_bootstrap. 244 */ 245 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int); 246 247 /* 248 * PTE calls. 249 */ 250 static int moea_pte_insert(u_int, struct pte *); 251 252 /* 253 * PVO calls. 254 */ 255 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *, 256 vm_offset_t, vm_offset_t, u_int, int); 257 static void moea_pvo_remove(struct pvo_entry *, int); 258 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *); 259 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int); 260 261 /* 262 * Utility routines. 263 */ 264 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t, 265 vm_prot_t, boolean_t); 266 static void moea_syncicache(vm_offset_t, vm_size_t); 267 static boolean_t moea_query_bit(vm_page_t, int); 268 static u_int moea_clear_bit(vm_page_t, int); 269 static void moea_kremove(mmu_t, vm_offset_t); 270 int moea_pte_spill(vm_offset_t); 271 272 /* 273 * Kernel MMU interface 274 */ 275 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 276 void moea_clear_modify(mmu_t, vm_page_t); 277 void moea_clear_reference(mmu_t, vm_page_t); 278 void moea_copy_page(mmu_t, vm_page_t, vm_page_t); 279 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t); 280 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 283 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t); 284 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 285 void moea_init(mmu_t); 286 boolean_t moea_is_modified(mmu_t, vm_page_t); 287 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288 boolean_t moea_is_referenced(mmu_t, vm_page_t); 289 boolean_t moea_ts_referenced(mmu_t, vm_page_t); 290 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int); 291 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t); 292 int moea_page_wired_mappings(mmu_t, vm_page_t); 293 void moea_pinit(mmu_t, pmap_t); 294 void moea_pinit0(mmu_t, pmap_t); 295 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 296 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 297 void moea_qremove(mmu_t, vm_offset_t, int); 298 void moea_release(mmu_t, pmap_t); 299 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 300 void moea_remove_all(mmu_t, vm_page_t); 301 void moea_remove_write(mmu_t, vm_page_t); 302 void moea_zero_page(mmu_t, vm_page_t); 303 void moea_zero_page_area(mmu_t, vm_page_t, int, int); 304 void moea_zero_page_idle(mmu_t, vm_page_t); 305 void moea_activate(mmu_t, struct thread *); 306 void moea_deactivate(mmu_t, struct thread *); 307 void moea_cpu_bootstrap(mmu_t, int); 308 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 309 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t); 310 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t); 311 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t); 312 vm_offset_t moea_kextract(mmu_t, vm_offset_t); 313 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t); 314 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t); 315 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma); 316 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 317 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 318 319 static mmu_method_t moea_methods[] = { 320 MMUMETHOD(mmu_change_wiring, moea_change_wiring), 321 MMUMETHOD(mmu_clear_modify, moea_clear_modify), 322 MMUMETHOD(mmu_clear_reference, moea_clear_reference), 323 MMUMETHOD(mmu_copy_page, moea_copy_page), 324 MMUMETHOD(mmu_enter, moea_enter), 325 MMUMETHOD(mmu_enter_object, moea_enter_object), 326 MMUMETHOD(mmu_enter_quick, moea_enter_quick), 327 MMUMETHOD(mmu_extract, moea_extract), 328 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold), 329 MMUMETHOD(mmu_init, moea_init), 330 MMUMETHOD(mmu_is_modified, moea_is_modified), 331 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable), 332 MMUMETHOD(mmu_is_referenced, moea_is_referenced), 333 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced), 334 MMUMETHOD(mmu_map, moea_map), 335 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick), 336 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings), 337 MMUMETHOD(mmu_pinit, moea_pinit), 338 MMUMETHOD(mmu_pinit0, moea_pinit0), 339 MMUMETHOD(mmu_protect, moea_protect), 340 MMUMETHOD(mmu_qenter, moea_qenter), 341 MMUMETHOD(mmu_qremove, moea_qremove), 342 MMUMETHOD(mmu_release, moea_release), 343 MMUMETHOD(mmu_remove, moea_remove), 344 MMUMETHOD(mmu_remove_all, moea_remove_all), 345 MMUMETHOD(mmu_remove_write, moea_remove_write), 346 MMUMETHOD(mmu_sync_icache, moea_sync_icache), 347 MMUMETHOD(mmu_zero_page, moea_zero_page), 348 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area), 349 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle), 350 MMUMETHOD(mmu_activate, moea_activate), 351 MMUMETHOD(mmu_deactivate, moea_deactivate), 352 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr), 353 354 /* Internal interfaces */ 355 MMUMETHOD(mmu_bootstrap, moea_bootstrap), 356 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap), 357 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr), 358 MMUMETHOD(mmu_mapdev, moea_mapdev), 359 MMUMETHOD(mmu_unmapdev, moea_unmapdev), 360 MMUMETHOD(mmu_kextract, moea_kextract), 361 MMUMETHOD(mmu_kenter, moea_kenter), 362 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr), 363 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped), 364 365 { 0, 0 } 366 }; 367 368 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0); 369 370 static __inline uint32_t 371 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma) 372 { 373 uint32_t pte_lo; 374 int i; 375 376 if (ma != VM_MEMATTR_DEFAULT) { 377 switch (ma) { 378 case VM_MEMATTR_UNCACHEABLE: 379 return (PTE_I | PTE_G); 380 case VM_MEMATTR_WRITE_COMBINING: 381 case VM_MEMATTR_WRITE_BACK: 382 case VM_MEMATTR_PREFETCHABLE: 383 return (PTE_I); 384 case VM_MEMATTR_WRITE_THROUGH: 385 return (PTE_W | PTE_M); 386 } 387 } 388 389 /* 390 * Assume the page is cache inhibited and access is guarded unless 391 * it's in our available memory array. 392 */ 393 pte_lo = PTE_I | PTE_G; 394 for (i = 0; i < pregions_sz; i++) { 395 if ((pa >= pregions[i].mr_start) && 396 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 397 pte_lo = PTE_M; 398 break; 399 } 400 } 401 402 return pte_lo; 403 } 404 405 static void 406 tlbie(vm_offset_t va) 407 { 408 409 mtx_lock_spin(&tlbie_mtx); 410 __asm __volatile("ptesync"); 411 __asm __volatile("tlbie %0" :: "r"(va)); 412 __asm __volatile("eieio; tlbsync; ptesync"); 413 mtx_unlock_spin(&tlbie_mtx); 414 } 415 416 static void 417 tlbia(void) 418 { 419 vm_offset_t va; 420 421 for (va = 0; va < 0x00040000; va += 0x00001000) { 422 __asm __volatile("tlbie %0" :: "r"(va)); 423 powerpc_sync(); 424 } 425 __asm __volatile("tlbsync"); 426 powerpc_sync(); 427 } 428 429 static __inline int 430 va_to_sr(u_int *sr, vm_offset_t va) 431 { 432 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]); 433 } 434 435 static __inline u_int 436 va_to_pteg(u_int sr, vm_offset_t addr) 437 { 438 u_int hash; 439 440 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >> 441 ADDR_PIDX_SHFT); 442 return (hash & moea_pteg_mask); 443 } 444 445 static __inline struct pvo_head * 446 vm_page_to_pvoh(vm_page_t m) 447 { 448 449 return (&m->md.mdpg_pvoh); 450 } 451 452 static __inline void 453 moea_attr_clear(vm_page_t m, int ptebit) 454 { 455 456 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 457 m->md.mdpg_attrs &= ~ptebit; 458 } 459 460 static __inline int 461 moea_attr_fetch(vm_page_t m) 462 { 463 464 return (m->md.mdpg_attrs); 465 } 466 467 static __inline void 468 moea_attr_save(vm_page_t m, int ptebit) 469 { 470 471 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 472 m->md.mdpg_attrs |= ptebit; 473 } 474 475 static __inline int 476 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt) 477 { 478 if (pt->pte_hi == pvo_pt->pte_hi) 479 return (1); 480 481 return (0); 482 } 483 484 static __inline int 485 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which) 486 { 487 return (pt->pte_hi & ~PTE_VALID) == 488 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 489 ((va >> ADDR_API_SHFT) & PTE_API) | which); 490 } 491 492 static __inline void 493 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo) 494 { 495 496 mtx_assert(&moea_table_mutex, MA_OWNED); 497 498 /* 499 * Construct a PTE. Default to IMB initially. Valid bit only gets 500 * set when the real pte is set in memory. 501 * 502 * Note: Don't set the valid bit for correct operation of tlb update. 503 */ 504 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) | 505 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API); 506 pt->pte_lo = pte_lo; 507 } 508 509 static __inline void 510 moea_pte_synch(struct pte *pt, struct pte *pvo_pt) 511 { 512 513 mtx_assert(&moea_table_mutex, MA_OWNED); 514 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG); 515 } 516 517 static __inline void 518 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit) 519 { 520 521 mtx_assert(&moea_table_mutex, MA_OWNED); 522 523 /* 524 * As shown in Section 7.6.3.2.3 525 */ 526 pt->pte_lo &= ~ptebit; 527 tlbie(va); 528 } 529 530 static __inline void 531 moea_pte_set(struct pte *pt, struct pte *pvo_pt) 532 { 533 534 mtx_assert(&moea_table_mutex, MA_OWNED); 535 pvo_pt->pte_hi |= PTE_VALID; 536 537 /* 538 * Update the PTE as defined in section 7.6.3.1. 539 * Note that the REF/CHG bits are from pvo_pt and thus should havce 540 * been saved so this routine can restore them (if desired). 541 */ 542 pt->pte_lo = pvo_pt->pte_lo; 543 powerpc_sync(); 544 pt->pte_hi = pvo_pt->pte_hi; 545 powerpc_sync(); 546 moea_pte_valid++; 547 } 548 549 static __inline void 550 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 551 { 552 553 mtx_assert(&moea_table_mutex, MA_OWNED); 554 pvo_pt->pte_hi &= ~PTE_VALID; 555 556 /* 557 * Force the reg & chg bits back into the PTEs. 558 */ 559 powerpc_sync(); 560 561 /* 562 * Invalidate the pte. 563 */ 564 pt->pte_hi &= ~PTE_VALID; 565 566 tlbie(va); 567 568 /* 569 * Save the reg & chg bits. 570 */ 571 moea_pte_synch(pt, pvo_pt); 572 moea_pte_valid--; 573 } 574 575 static __inline void 576 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va) 577 { 578 579 /* 580 * Invalidate the PTE 581 */ 582 moea_pte_unset(pt, pvo_pt, va); 583 moea_pte_set(pt, pvo_pt); 584 } 585 586 /* 587 * Quick sort callout for comparing memory regions. 588 */ 589 static int mr_cmp(const void *a, const void *b); 590 static int om_cmp(const void *a, const void *b); 591 592 static int 593 mr_cmp(const void *a, const void *b) 594 { 595 const struct mem_region *regiona; 596 const struct mem_region *regionb; 597 598 regiona = a; 599 regionb = b; 600 if (regiona->mr_start < regionb->mr_start) 601 return (-1); 602 else if (regiona->mr_start > regionb->mr_start) 603 return (1); 604 else 605 return (0); 606 } 607 608 static int 609 om_cmp(const void *a, const void *b) 610 { 611 const struct ofw_map *mapa; 612 const struct ofw_map *mapb; 613 614 mapa = a; 615 mapb = b; 616 if (mapa->om_pa < mapb->om_pa) 617 return (-1); 618 else if (mapa->om_pa > mapb->om_pa) 619 return (1); 620 else 621 return (0); 622 } 623 624 void 625 moea_cpu_bootstrap(mmu_t mmup, int ap) 626 { 627 u_int sdr; 628 int i; 629 630 if (ap) { 631 powerpc_sync(); 632 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu)); 633 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl)); 634 isync(); 635 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu)); 636 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl)); 637 isync(); 638 } 639 640 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 641 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 642 isync(); 643 644 __asm __volatile("mtibatu 1,%0" :: "r"(0)); 645 __asm __volatile("mtdbatu 2,%0" :: "r"(0)); 646 __asm __volatile("mtibatu 2,%0" :: "r"(0)); 647 __asm __volatile("mtdbatu 3,%0" :: "r"(0)); 648 __asm __volatile("mtibatu 3,%0" :: "r"(0)); 649 isync(); 650 651 for (i = 0; i < 16; i++) 652 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]); 653 powerpc_sync(); 654 655 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10); 656 __asm __volatile("mtsdr1 %0" :: "r"(sdr)); 657 isync(); 658 659 tlbia(); 660 } 661 662 void 663 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 664 { 665 ihandle_t mmui; 666 phandle_t chosen, mmu; 667 int sz; 668 int i, j; 669 vm_size_t size, physsz, hwphyssz; 670 vm_offset_t pa, va, off; 671 void *dpcpu; 672 register_t msr; 673 674 /* 675 * Set up BAT0 to map the lowest 256 MB area 676 */ 677 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); 678 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); 679 680 /* 681 * Map PCI memory space. 682 */ 683 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW); 684 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs); 685 686 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW); 687 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs); 688 689 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW); 690 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs); 691 692 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); 693 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); 694 695 /* 696 * Map obio devices. 697 */ 698 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); 699 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); 700 701 /* 702 * Use an IBAT and a DBAT to map the bottom segment of memory 703 * where we are. Turn off instruction relocation temporarily 704 * to prevent faults while reprogramming the IBAT. 705 */ 706 msr = mfmsr(); 707 mtmsr(msr & ~PSL_IR); 708 __asm (".balign 32; \n" 709 "mtibatu 0,%0; mtibatl 0,%1; isync; \n" 710 "mtdbatu 0,%0; mtdbatl 0,%1; isync" 711 :: "r"(battable[0].batu), "r"(battable[0].batl)); 712 mtmsr(msr); 713 714 /* map pci space */ 715 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); 716 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl)); 717 isync(); 718 719 /* set global direct map flag */ 720 hw_direct_map = 1; 721 722 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 723 CTR0(KTR_PMAP, "moea_bootstrap: physical memory"); 724 725 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp); 726 for (i = 0; i < pregions_sz; i++) { 727 vm_offset_t pa; 728 vm_offset_t end; 729 730 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)", 731 pregions[i].mr_start, 732 pregions[i].mr_start + pregions[i].mr_size, 733 pregions[i].mr_size); 734 /* 735 * Install entries into the BAT table to allow all 736 * of physmem to be convered by on-demand BAT entries. 737 * The loop will sometimes set the same battable element 738 * twice, but that's fine since they won't be used for 739 * a while yet. 740 */ 741 pa = pregions[i].mr_start & 0xf0000000; 742 end = pregions[i].mr_start + pregions[i].mr_size; 743 do { 744 u_int n = pa >> ADDR_SR_SHFT; 745 746 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW); 747 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs); 748 pa += SEGMENT_LENGTH; 749 } while (pa < end); 750 } 751 752 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 753 panic("moea_bootstrap: phys_avail too small"); 754 qsort(regions, regions_sz, sizeof(*regions), mr_cmp); 755 phys_avail_count = 0; 756 physsz = 0; 757 hwphyssz = 0; 758 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 759 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 760 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start, 761 regions[i].mr_start + regions[i].mr_size, 762 regions[i].mr_size); 763 if (hwphyssz != 0 && 764 (physsz + regions[i].mr_size) >= hwphyssz) { 765 if (physsz < hwphyssz) { 766 phys_avail[j] = regions[i].mr_start; 767 phys_avail[j + 1] = regions[i].mr_start + 768 hwphyssz - physsz; 769 physsz = hwphyssz; 770 phys_avail_count++; 771 } 772 break; 773 } 774 phys_avail[j] = regions[i].mr_start; 775 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 776 phys_avail_count++; 777 physsz += regions[i].mr_size; 778 } 779 physmem = btoc(physsz); 780 781 /* 782 * Allocate PTEG table. 783 */ 784 #ifdef PTEGCOUNT 785 moea_pteg_count = PTEGCOUNT; 786 #else 787 moea_pteg_count = 0x1000; 788 789 while (moea_pteg_count < physmem) 790 moea_pteg_count <<= 1; 791 792 moea_pteg_count >>= 1; 793 #endif /* PTEGCOUNT */ 794 795 size = moea_pteg_count * sizeof(struct pteg); 796 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count, 797 size); 798 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size); 799 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table); 800 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg)); 801 moea_pteg_mask = moea_pteg_count - 1; 802 803 /* 804 * Allocate pv/overflow lists. 805 */ 806 size = sizeof(struct pvo_head) * moea_pteg_count; 807 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size, 808 PAGE_SIZE); 809 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table); 810 for (i = 0; i < moea_pteg_count; i++) 811 LIST_INIT(&moea_pvo_table[i]); 812 813 /* 814 * Initialize the lock that synchronizes access to the pteg and pvo 815 * tables. 816 */ 817 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF | 818 MTX_RECURSE); 819 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF); 820 821 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN); 822 823 /* 824 * Initialise the unmanaged pvo pool. 825 */ 826 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc( 827 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0); 828 moea_bpvo_pool_index = 0; 829 830 /* 831 * Make sure kernel vsid is allocated as well as VSID 0. 832 */ 833 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW] 834 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 835 moea_vsid_bitmap[0] |= 1; 836 837 /* 838 * Initialize the kernel pmap (which is statically allocated). 839 */ 840 PMAP_LOCK_INIT(kernel_pmap); 841 for (i = 0; i < 16; i++) 842 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 843 kernel_pmap->pm_active = ~0; 844 845 /* 846 * Set up the Open Firmware mappings 847 */ 848 if ((chosen = OF_finddevice("/chosen")) == -1) 849 panic("moea_bootstrap: can't find /chosen"); 850 OF_getprop(chosen, "mmu", &mmui, 4); 851 if ((mmu = OF_instance_to_package(mmui)) == -1) 852 panic("moea_bootstrap: can't get mmu package"); 853 if ((sz = OF_getproplen(mmu, "translations")) == -1) 854 panic("moea_bootstrap: can't get ofw translation count"); 855 translations = NULL; 856 for (i = 0; phys_avail[i] != 0; i += 2) { 857 if (phys_avail[i + 1] >= sz) { 858 translations = (struct ofw_map *)phys_avail[i]; 859 break; 860 } 861 } 862 if (translations == NULL) 863 panic("moea_bootstrap: no space to copy translations"); 864 bzero(translations, sz); 865 if (OF_getprop(mmu, "translations", translations, sz) == -1) 866 panic("moea_bootstrap: can't get ofw translations"); 867 CTR0(KTR_PMAP, "moea_bootstrap: translations"); 868 sz /= sizeof(*translations); 869 qsort(translations, sz, sizeof (*translations), om_cmp); 870 for (i = 0; i < sz; i++) { 871 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x", 872 translations[i].om_pa, translations[i].om_va, 873 translations[i].om_len); 874 875 /* 876 * If the mapping is 1:1, let the RAM and device on-demand 877 * BAT tables take care of the translation. 878 */ 879 if (translations[i].om_va == translations[i].om_pa) 880 continue; 881 882 /* Enter the pages */ 883 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) 884 moea_kenter(mmup, translations[i].om_va + off, 885 translations[i].om_pa + off); 886 } 887 888 /* 889 * Calculate the last available physical address. 890 */ 891 for (i = 0; phys_avail[i + 2] != 0; i += 2) 892 ; 893 Maxmem = powerpc_btop(phys_avail[i + 1]); 894 895 moea_cpu_bootstrap(mmup,0); 896 897 pmap_bootstrapped++; 898 899 /* 900 * Set the start and end of kva. 901 */ 902 virtual_avail = VM_MIN_KERNEL_ADDRESS; 903 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 904 905 /* 906 * Allocate a kernel stack with a guard page for thread0 and map it 907 * into the kernel page map. 908 */ 909 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE); 910 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 911 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE; 912 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va); 913 thread0.td_kstack = va; 914 thread0.td_kstack_pages = KSTACK_PAGES; 915 for (i = 0; i < KSTACK_PAGES; i++) { 916 moea_kenter(mmup, va, pa); 917 pa += PAGE_SIZE; 918 va += PAGE_SIZE; 919 } 920 921 /* 922 * Allocate virtual address space for the message buffer. 923 */ 924 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE); 925 msgbufp = (struct msgbuf *)virtual_avail; 926 va = virtual_avail; 927 virtual_avail += round_page(msgbufsize); 928 while (va < virtual_avail) { 929 moea_kenter(mmup, va, pa); 930 pa += PAGE_SIZE; 931 va += PAGE_SIZE; 932 } 933 934 /* 935 * Allocate virtual address space for the dynamic percpu area. 936 */ 937 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 938 dpcpu = (void *)virtual_avail; 939 va = virtual_avail; 940 virtual_avail += DPCPU_SIZE; 941 while (va < virtual_avail) { 942 moea_kenter(mmup, va, pa); 943 pa += PAGE_SIZE; 944 va += PAGE_SIZE; 945 } 946 dpcpu_init(dpcpu, 0); 947 } 948 949 /* 950 * Activate a user pmap. The pmap must be activated before it's address 951 * space can be accessed in any way. 952 */ 953 void 954 moea_activate(mmu_t mmu, struct thread *td) 955 { 956 pmap_t pm, pmr; 957 958 /* 959 * Load all the data we need up front to encourage the compiler to 960 * not issue any loads while we have interrupts disabled below. 961 */ 962 pm = &td->td_proc->p_vmspace->vm_pmap; 963 pmr = pm->pmap_phys; 964 965 pm->pm_active |= PCPU_GET(cpumask); 966 PCPU_SET(curpmap, pmr); 967 } 968 969 void 970 moea_deactivate(mmu_t mmu, struct thread *td) 971 { 972 pmap_t pm; 973 974 pm = &td->td_proc->p_vmspace->vm_pmap; 975 pm->pm_active &= ~PCPU_GET(cpumask); 976 PCPU_SET(curpmap, NULL); 977 } 978 979 void 980 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired) 981 { 982 struct pvo_entry *pvo; 983 984 PMAP_LOCK(pm); 985 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 986 987 if (pvo != NULL) { 988 if (wired) { 989 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 990 pm->pm_stats.wired_count++; 991 pvo->pvo_vaddr |= PVO_WIRED; 992 } else { 993 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 994 pm->pm_stats.wired_count--; 995 pvo->pvo_vaddr &= ~PVO_WIRED; 996 } 997 } 998 PMAP_UNLOCK(pm); 999 } 1000 1001 void 1002 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1003 { 1004 vm_offset_t dst; 1005 vm_offset_t src; 1006 1007 dst = VM_PAGE_TO_PHYS(mdst); 1008 src = VM_PAGE_TO_PHYS(msrc); 1009 1010 kcopy((void *)src, (void *)dst, PAGE_SIZE); 1011 } 1012 1013 /* 1014 * Zero a page of physical memory by temporarily mapping it into the tlb. 1015 */ 1016 void 1017 moea_zero_page(mmu_t mmu, vm_page_t m) 1018 { 1019 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1020 void *va = (void *)pa; 1021 1022 bzero(va, PAGE_SIZE); 1023 } 1024 1025 void 1026 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1027 { 1028 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1029 void *va = (void *)(pa + off); 1030 1031 bzero(va, size); 1032 } 1033 1034 void 1035 moea_zero_page_idle(mmu_t mmu, vm_page_t m) 1036 { 1037 vm_offset_t pa = VM_PAGE_TO_PHYS(m); 1038 void *va = (void *)pa; 1039 1040 bzero(va, PAGE_SIZE); 1041 } 1042 1043 /* 1044 * Map the given physical page at the specified virtual address in the 1045 * target pmap with the protection requested. If specified the page 1046 * will be wired down. 1047 */ 1048 void 1049 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1050 boolean_t wired) 1051 { 1052 1053 vm_page_lock_queues(); 1054 PMAP_LOCK(pmap); 1055 moea_enter_locked(pmap, va, m, prot, wired); 1056 vm_page_unlock_queues(); 1057 PMAP_UNLOCK(pmap); 1058 } 1059 1060 /* 1061 * Map the given physical page at the specified virtual address in the 1062 * target pmap with the protection requested. If specified the page 1063 * will be wired down. 1064 * 1065 * The page queues and pmap must be locked. 1066 */ 1067 static void 1068 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1069 boolean_t wired) 1070 { 1071 struct pvo_head *pvo_head; 1072 uma_zone_t zone; 1073 vm_page_t pg; 1074 u_int pte_lo, pvo_flags, was_exec; 1075 int error; 1076 1077 if (!moea_initialized) { 1078 pvo_head = &moea_pvo_kunmanaged; 1079 zone = moea_upvo_zone; 1080 pvo_flags = 0; 1081 pg = NULL; 1082 was_exec = PTE_EXEC; 1083 } else { 1084 pvo_head = vm_page_to_pvoh(m); 1085 pg = m; 1086 zone = moea_mpvo_zone; 1087 pvo_flags = PVO_MANAGED; 1088 was_exec = 0; 1089 } 1090 if (pmap_bootstrapped) 1091 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1092 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1093 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1094 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1095 ("moea_enter_locked: page %p is not busy", m)); 1096 1097 /* XXX change the pvo head for fake pages */ 1098 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) { 1099 pvo_flags &= ~PVO_MANAGED; 1100 pvo_head = &moea_pvo_kunmanaged; 1101 zone = moea_upvo_zone; 1102 } 1103 1104 /* 1105 * If this is a managed page, and it's the first reference to the page, 1106 * clear the execness of the page. Otherwise fetch the execness. 1107 */ 1108 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) { 1109 if (LIST_EMPTY(pvo_head)) { 1110 moea_attr_clear(pg, PTE_EXEC); 1111 } else { 1112 was_exec = moea_attr_fetch(pg) & PTE_EXEC; 1113 } 1114 } 1115 1116 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1117 1118 if (prot & VM_PROT_WRITE) { 1119 pte_lo |= PTE_BW; 1120 if (pmap_bootstrapped && 1121 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1122 vm_page_flag_set(m, PG_WRITEABLE); 1123 } else 1124 pte_lo |= PTE_BR; 1125 1126 if (prot & VM_PROT_EXECUTE) 1127 pvo_flags |= PVO_EXECUTABLE; 1128 1129 if (wired) 1130 pvo_flags |= PVO_WIRED; 1131 1132 if ((m->flags & PG_FICTITIOUS) != 0) 1133 pvo_flags |= PVO_FAKE; 1134 1135 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m), 1136 pte_lo, pvo_flags); 1137 1138 /* 1139 * Flush the real page from the instruction cache if this page is 1140 * mapped executable and cacheable and was not previously mapped (or 1141 * was not mapped executable). 1142 */ 1143 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) && 1144 (pte_lo & PTE_I) == 0 && was_exec == 0) { 1145 /* 1146 * Flush the real memory from the cache. 1147 */ 1148 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1149 if (pg != NULL) 1150 moea_attr_save(pg, PTE_EXEC); 1151 } 1152 1153 /* XXX syncicache always until problems are sorted */ 1154 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1155 } 1156 1157 /* 1158 * Maps a sequence of resident pages belonging to the same object. 1159 * The sequence begins with the given page m_start. This page is 1160 * mapped at the given virtual address start. Each subsequent page is 1161 * mapped at a virtual address that is offset from start by the same 1162 * amount as the page is offset from m_start within the object. The 1163 * last page in the sequence is the page with the largest offset from 1164 * m_start that can be mapped at a virtual address less than the given 1165 * virtual address end. Not every virtual page between start and end 1166 * is mapped; only those for which a resident page exists with the 1167 * corresponding offset from m_start are mapped. 1168 */ 1169 void 1170 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1171 vm_page_t m_start, vm_prot_t prot) 1172 { 1173 vm_page_t m; 1174 vm_pindex_t diff, psize; 1175 1176 psize = atop(end - start); 1177 m = m_start; 1178 vm_page_lock_queues(); 1179 PMAP_LOCK(pm); 1180 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1181 moea_enter_locked(pm, start + ptoa(diff), m, prot & 1182 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1183 m = TAILQ_NEXT(m, listq); 1184 } 1185 vm_page_unlock_queues(); 1186 PMAP_UNLOCK(pm); 1187 } 1188 1189 void 1190 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1191 vm_prot_t prot) 1192 { 1193 1194 vm_page_lock_queues(); 1195 PMAP_LOCK(pm); 1196 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1197 FALSE); 1198 vm_page_unlock_queues(); 1199 PMAP_UNLOCK(pm); 1200 } 1201 1202 vm_paddr_t 1203 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1204 { 1205 struct pvo_entry *pvo; 1206 vm_paddr_t pa; 1207 1208 PMAP_LOCK(pm); 1209 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 1210 if (pvo == NULL) 1211 pa = 0; 1212 else 1213 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1214 PMAP_UNLOCK(pm); 1215 return (pa); 1216 } 1217 1218 /* 1219 * Atomically extract and hold the physical page with the given 1220 * pmap and virtual address pair if that mapping permits the given 1221 * protection. 1222 */ 1223 vm_page_t 1224 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1225 { 1226 struct pvo_entry *pvo; 1227 vm_page_t m; 1228 vm_paddr_t pa; 1229 1230 m = NULL; 1231 pa = 0; 1232 PMAP_LOCK(pmap); 1233 retry: 1234 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1235 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) && 1236 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW || 1237 (prot & VM_PROT_WRITE) == 0)) { 1238 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa)) 1239 goto retry; 1240 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 1241 vm_page_hold(m); 1242 } 1243 PA_UNLOCK_COND(pa); 1244 PMAP_UNLOCK(pmap); 1245 return (m); 1246 } 1247 1248 void 1249 moea_init(mmu_t mmu) 1250 { 1251 1252 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1253 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1254 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1255 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry), 1256 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1257 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1258 moea_initialized = TRUE; 1259 } 1260 1261 boolean_t 1262 moea_is_referenced(mmu_t mmu, vm_page_t m) 1263 { 1264 1265 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1266 ("moea_is_referenced: page %p is not managed", m)); 1267 return (moea_query_bit(m, PTE_REF)); 1268 } 1269 1270 boolean_t 1271 moea_is_modified(mmu_t mmu, vm_page_t m) 1272 { 1273 1274 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1275 ("moea_is_modified: page %p is not managed", m)); 1276 1277 /* 1278 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 1279 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 1280 * is clear, no PTEs can have PTE_CHG set. 1281 */ 1282 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1283 if ((m->oflags & VPO_BUSY) == 0 && 1284 (m->flags & PG_WRITEABLE) == 0) 1285 return (FALSE); 1286 return (moea_query_bit(m, PTE_CHG)); 1287 } 1288 1289 boolean_t 1290 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1291 { 1292 struct pvo_entry *pvo; 1293 boolean_t rv; 1294 1295 PMAP_LOCK(pmap); 1296 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL); 1297 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0; 1298 PMAP_UNLOCK(pmap); 1299 return (rv); 1300 } 1301 1302 void 1303 moea_clear_reference(mmu_t mmu, vm_page_t m) 1304 { 1305 1306 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1307 ("moea_clear_reference: page %p is not managed", m)); 1308 moea_clear_bit(m, PTE_REF); 1309 } 1310 1311 void 1312 moea_clear_modify(mmu_t mmu, vm_page_t m) 1313 { 1314 1315 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1316 ("moea_clear_modify: page %p is not managed", m)); 1317 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1318 KASSERT((m->oflags & VPO_BUSY) == 0, 1319 ("moea_clear_modify: page %p is busy", m)); 1320 1321 /* 1322 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_CHG 1323 * set. If the object containing the page is locked and the page is 1324 * not VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 1325 */ 1326 if ((m->flags & PG_WRITEABLE) == 0) 1327 return; 1328 moea_clear_bit(m, PTE_CHG); 1329 } 1330 1331 /* 1332 * Clear the write and modified bits in each of the given page's mappings. 1333 */ 1334 void 1335 moea_remove_write(mmu_t mmu, vm_page_t m) 1336 { 1337 struct pvo_entry *pvo; 1338 struct pte *pt; 1339 pmap_t pmap; 1340 u_int lo; 1341 1342 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1343 ("moea_remove_write: page %p is not managed", m)); 1344 1345 /* 1346 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1347 * another thread while the object is locked. Thus, if PG_WRITEABLE 1348 * is clear, no page table entries need updating. 1349 */ 1350 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1351 if ((m->oflags & VPO_BUSY) == 0 && 1352 (m->flags & PG_WRITEABLE) == 0) 1353 return; 1354 vm_page_lock_queues(); 1355 lo = moea_attr_fetch(m); 1356 powerpc_sync(); 1357 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1358 pmap = pvo->pvo_pmap; 1359 PMAP_LOCK(pmap); 1360 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) { 1361 pt = moea_pvo_to_pte(pvo, -1); 1362 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1363 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1364 if (pt != NULL) { 1365 moea_pte_synch(pt, &pvo->pvo_pte.pte); 1366 lo |= pvo->pvo_pte.pte.pte_lo; 1367 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG; 1368 moea_pte_change(pt, &pvo->pvo_pte.pte, 1369 pvo->pvo_vaddr); 1370 mtx_unlock(&moea_table_mutex); 1371 } 1372 } 1373 PMAP_UNLOCK(pmap); 1374 } 1375 if ((lo & PTE_CHG) != 0) { 1376 moea_attr_clear(m, PTE_CHG); 1377 vm_page_dirty(m); 1378 } 1379 vm_page_flag_clear(m, PG_WRITEABLE); 1380 vm_page_unlock_queues(); 1381 } 1382 1383 /* 1384 * moea_ts_referenced: 1385 * 1386 * Return a count of reference bits for a page, clearing those bits. 1387 * It is not necessary for every reference bit to be cleared, but it 1388 * is necessary that 0 only be returned when there are truly no 1389 * reference bits set. 1390 * 1391 * XXX: The exact number of bits to check and clear is a matter that 1392 * should be tested and standardized at some point in the future for 1393 * optimal aging of shared pages. 1394 */ 1395 boolean_t 1396 moea_ts_referenced(mmu_t mmu, vm_page_t m) 1397 { 1398 1399 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1400 ("moea_ts_referenced: page %p is not managed", m)); 1401 return (moea_clear_bit(m, PTE_REF)); 1402 } 1403 1404 /* 1405 * Modify the WIMG settings of all mappings for a page. 1406 */ 1407 void 1408 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1409 { 1410 struct pvo_entry *pvo; 1411 struct pvo_head *pvo_head; 1412 struct pte *pt; 1413 pmap_t pmap; 1414 u_int lo; 1415 1416 if (m->flags & PG_FICTITIOUS) { 1417 m->md.mdpg_cache_attrs = ma; 1418 return; 1419 } 1420 1421 vm_page_lock_queues(); 1422 pvo_head = vm_page_to_pvoh(m); 1423 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1424 1425 LIST_FOREACH(pvo, pvo_head, pvo_vlink) { 1426 pmap = pvo->pvo_pmap; 1427 PMAP_LOCK(pmap); 1428 pt = moea_pvo_to_pte(pvo, -1); 1429 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG; 1430 pvo->pvo_pte.pte.pte_lo |= lo; 1431 if (pt != NULL) { 1432 moea_pte_change(pt, &pvo->pvo_pte.pte, 1433 pvo->pvo_vaddr); 1434 if (pvo->pvo_pmap == kernel_pmap) 1435 isync(); 1436 } 1437 mtx_unlock(&moea_table_mutex); 1438 PMAP_UNLOCK(pmap); 1439 } 1440 m->md.mdpg_cache_attrs = ma; 1441 vm_page_unlock_queues(); 1442 } 1443 1444 /* 1445 * Map a wired page into kernel virtual address space. 1446 */ 1447 void 1448 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1449 { 1450 1451 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1452 } 1453 1454 void 1455 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma) 1456 { 1457 u_int pte_lo; 1458 int error; 1459 1460 #if 0 1461 if (va < VM_MIN_KERNEL_ADDRESS) 1462 panic("moea_kenter: attempt to enter non-kernel address %#x", 1463 va); 1464 #endif 1465 1466 pte_lo = moea_calc_wimg(pa, ma); 1467 1468 PMAP_LOCK(kernel_pmap); 1469 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone, 1470 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED); 1471 1472 if (error != 0 && error != ENOENT) 1473 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va, 1474 pa, error); 1475 1476 /* 1477 * Flush the real memory from the instruction cache. 1478 */ 1479 if ((pte_lo & (PTE_I | PTE_G)) == 0) { 1480 moea_syncicache(pa, PAGE_SIZE); 1481 } 1482 PMAP_UNLOCK(kernel_pmap); 1483 } 1484 1485 /* 1486 * Extract the physical page address associated with the given kernel virtual 1487 * address. 1488 */ 1489 vm_offset_t 1490 moea_kextract(mmu_t mmu, vm_offset_t va) 1491 { 1492 struct pvo_entry *pvo; 1493 vm_paddr_t pa; 1494 1495 /* 1496 * Allow direct mappings on 32-bit OEA 1497 */ 1498 if (va < VM_MIN_KERNEL_ADDRESS) { 1499 return (va); 1500 } 1501 1502 PMAP_LOCK(kernel_pmap); 1503 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL); 1504 KASSERT(pvo != NULL, ("moea_kextract: no addr found")); 1505 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF); 1506 PMAP_UNLOCK(kernel_pmap); 1507 return (pa); 1508 } 1509 1510 /* 1511 * Remove a wired page from kernel virtual address space. 1512 */ 1513 void 1514 moea_kremove(mmu_t mmu, vm_offset_t va) 1515 { 1516 1517 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1518 } 1519 1520 /* 1521 * Map a range of physical addresses into kernel virtual address space. 1522 * 1523 * The value passed in *virt is a suggested virtual address for the mapping. 1524 * Architectures which can support a direct-mapped physical to virtual region 1525 * can return the appropriate address within that region, leaving '*virt' 1526 * unchanged. We cannot and therefore do not; *virt is updated with the 1527 * first usable address after the mapped region. 1528 */ 1529 vm_offset_t 1530 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1531 vm_offset_t pa_end, int prot) 1532 { 1533 vm_offset_t sva, va; 1534 1535 sva = *virt; 1536 va = sva; 1537 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1538 moea_kenter(mmu, va, pa_start); 1539 *virt = va; 1540 return (sva); 1541 } 1542 1543 /* 1544 * Returns true if the pmap's pv is one of the first 1545 * 16 pvs linked to from this page. This count may 1546 * be changed upwards or downwards in the future; it 1547 * is only necessary that true be returned for a small 1548 * subset of pmaps for proper page aging. 1549 */ 1550 boolean_t 1551 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1552 { 1553 int loops; 1554 struct pvo_entry *pvo; 1555 boolean_t rv; 1556 1557 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1558 ("moea_page_exists_quick: page %p is not managed", m)); 1559 loops = 0; 1560 rv = FALSE; 1561 vm_page_lock_queues(); 1562 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1563 if (pvo->pvo_pmap == pmap) { 1564 rv = TRUE; 1565 break; 1566 } 1567 if (++loops >= 16) 1568 break; 1569 } 1570 vm_page_unlock_queues(); 1571 return (rv); 1572 } 1573 1574 /* 1575 * Return the number of managed mappings to the given physical page 1576 * that are wired. 1577 */ 1578 int 1579 moea_page_wired_mappings(mmu_t mmu, vm_page_t m) 1580 { 1581 struct pvo_entry *pvo; 1582 int count; 1583 1584 count = 0; 1585 if ((m->flags & PG_FICTITIOUS) != 0) 1586 return (count); 1587 vm_page_lock_queues(); 1588 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1589 if ((pvo->pvo_vaddr & PVO_WIRED) != 0) 1590 count++; 1591 vm_page_unlock_queues(); 1592 return (count); 1593 } 1594 1595 static u_int moea_vsidcontext; 1596 1597 void 1598 moea_pinit(mmu_t mmu, pmap_t pmap) 1599 { 1600 int i, mask; 1601 u_int entropy; 1602 1603 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap")); 1604 PMAP_LOCK_INIT(pmap); 1605 1606 entropy = 0; 1607 __asm __volatile("mftb %0" : "=r"(entropy)); 1608 1609 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap)) 1610 == NULL) { 1611 pmap->pmap_phys = pmap; 1612 } 1613 1614 1615 mtx_lock(&moea_vsid_mutex); 1616 /* 1617 * Allocate some segment registers for this pmap. 1618 */ 1619 for (i = 0; i < NPMAPS; i += VSID_NBPW) { 1620 u_int hash, n; 1621 1622 /* 1623 * Create a new value by mutiplying by a prime and adding in 1624 * entropy from the timebase register. This is to make the 1625 * VSID more random so that the PT hash function collides 1626 * less often. (Note that the prime casues gcc to do shifts 1627 * instead of a multiply.) 1628 */ 1629 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy; 1630 hash = moea_vsidcontext & (NPMAPS - 1); 1631 if (hash == 0) /* 0 is special, avoid it */ 1632 continue; 1633 n = hash >> 5; 1634 mask = 1 << (hash & (VSID_NBPW - 1)); 1635 hash = (moea_vsidcontext & 0xfffff); 1636 if (moea_vsid_bitmap[n] & mask) { /* collision? */ 1637 /* anything free in this bucket? */ 1638 if (moea_vsid_bitmap[n] == 0xffffffff) { 1639 entropy = (moea_vsidcontext >> 20); 1640 continue; 1641 } 1642 i = ffs(~moea_vsid_bitmap[n]) - 1; 1643 mask = 1 << i; 1644 hash &= 0xfffff & ~(VSID_NBPW - 1); 1645 hash |= i; 1646 } 1647 moea_vsid_bitmap[n] |= mask; 1648 for (i = 0; i < 16; i++) 1649 pmap->pm_sr[i] = VSID_MAKE(i, hash); 1650 mtx_unlock(&moea_vsid_mutex); 1651 return; 1652 } 1653 1654 mtx_unlock(&moea_vsid_mutex); 1655 panic("moea_pinit: out of segments"); 1656 } 1657 1658 /* 1659 * Initialize the pmap associated with process 0. 1660 */ 1661 void 1662 moea_pinit0(mmu_t mmu, pmap_t pm) 1663 { 1664 1665 moea_pinit(mmu, pm); 1666 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1667 } 1668 1669 /* 1670 * Set the physical protection on the specified range of this map as requested. 1671 */ 1672 void 1673 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 1674 vm_prot_t prot) 1675 { 1676 struct pvo_entry *pvo; 1677 struct pte *pt; 1678 int pteidx; 1679 1680 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 1681 ("moea_protect: non current pmap")); 1682 1683 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1684 moea_remove(mmu, pm, sva, eva); 1685 return; 1686 } 1687 1688 vm_page_lock_queues(); 1689 PMAP_LOCK(pm); 1690 for (; sva < eva; sva += PAGE_SIZE) { 1691 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1692 if (pvo == NULL) 1693 continue; 1694 1695 if ((prot & VM_PROT_EXECUTE) == 0) 1696 pvo->pvo_vaddr &= ~PVO_EXECUTABLE; 1697 1698 /* 1699 * Grab the PTE pointer before we diddle with the cached PTE 1700 * copy. 1701 */ 1702 pt = moea_pvo_to_pte(pvo, pteidx); 1703 /* 1704 * Change the protection of the page. 1705 */ 1706 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP; 1707 pvo->pvo_pte.pte.pte_lo |= PTE_BR; 1708 1709 /* 1710 * If the PVO is in the page table, update that pte as well. 1711 */ 1712 if (pt != NULL) { 1713 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1714 mtx_unlock(&moea_table_mutex); 1715 } 1716 } 1717 vm_page_unlock_queues(); 1718 PMAP_UNLOCK(pm); 1719 } 1720 1721 /* 1722 * Map a list of wired pages into kernel virtual address space. This is 1723 * intended for temporary mappings which do not need page modification or 1724 * references recorded. Existing mappings in the region are overwritten. 1725 */ 1726 void 1727 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1728 { 1729 vm_offset_t va; 1730 1731 va = sva; 1732 while (count-- > 0) { 1733 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1734 va += PAGE_SIZE; 1735 m++; 1736 } 1737 } 1738 1739 /* 1740 * Remove page mappings from kernel virtual address space. Intended for 1741 * temporary mappings entered by moea_qenter. 1742 */ 1743 void 1744 moea_qremove(mmu_t mmu, vm_offset_t sva, int count) 1745 { 1746 vm_offset_t va; 1747 1748 va = sva; 1749 while (count-- > 0) { 1750 moea_kremove(mmu, va); 1751 va += PAGE_SIZE; 1752 } 1753 } 1754 1755 void 1756 moea_release(mmu_t mmu, pmap_t pmap) 1757 { 1758 int idx, mask; 1759 1760 /* 1761 * Free segment register's VSID 1762 */ 1763 if (pmap->pm_sr[0] == 0) 1764 panic("moea_release"); 1765 1766 mtx_lock(&moea_vsid_mutex); 1767 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1); 1768 mask = 1 << (idx % VSID_NBPW); 1769 idx /= VSID_NBPW; 1770 moea_vsid_bitmap[idx] &= ~mask; 1771 mtx_unlock(&moea_vsid_mutex); 1772 PMAP_LOCK_DESTROY(pmap); 1773 } 1774 1775 /* 1776 * Remove the given range of addresses from the specified map. 1777 */ 1778 void 1779 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1780 { 1781 struct pvo_entry *pvo; 1782 int pteidx; 1783 1784 vm_page_lock_queues(); 1785 PMAP_LOCK(pm); 1786 for (; sva < eva; sva += PAGE_SIZE) { 1787 pvo = moea_pvo_find_va(pm, sva, &pteidx); 1788 if (pvo != NULL) { 1789 moea_pvo_remove(pvo, pteidx); 1790 } 1791 } 1792 PMAP_UNLOCK(pm); 1793 vm_page_unlock_queues(); 1794 } 1795 1796 /* 1797 * Remove physical page from all pmaps in which it resides. moea_pvo_remove() 1798 * will reflect changes in pte's back to the vm_page. 1799 */ 1800 void 1801 moea_remove_all(mmu_t mmu, vm_page_t m) 1802 { 1803 struct pvo_head *pvo_head; 1804 struct pvo_entry *pvo, *next_pvo; 1805 pmap_t pmap; 1806 1807 vm_page_lock_queues(); 1808 pvo_head = vm_page_to_pvoh(m); 1809 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) { 1810 next_pvo = LIST_NEXT(pvo, pvo_vlink); 1811 1812 MOEA_PVO_CHECK(pvo); /* sanity check */ 1813 pmap = pvo->pvo_pmap; 1814 PMAP_LOCK(pmap); 1815 moea_pvo_remove(pvo, -1); 1816 PMAP_UNLOCK(pmap); 1817 } 1818 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) { 1819 moea_attr_clear(m, PTE_CHG); 1820 vm_page_dirty(m); 1821 } 1822 vm_page_flag_clear(m, PG_WRITEABLE); 1823 vm_page_unlock_queues(); 1824 } 1825 1826 /* 1827 * Allocate a physical page of memory directly from the phys_avail map. 1828 * Can only be called from moea_bootstrap before avail start and end are 1829 * calculated. 1830 */ 1831 static vm_offset_t 1832 moea_bootstrap_alloc(vm_size_t size, u_int align) 1833 { 1834 vm_offset_t s, e; 1835 int i, j; 1836 1837 size = round_page(size); 1838 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 1839 if (align != 0) 1840 s = (phys_avail[i] + align - 1) & ~(align - 1); 1841 else 1842 s = phys_avail[i]; 1843 e = s + size; 1844 1845 if (s < phys_avail[i] || e > phys_avail[i + 1]) 1846 continue; 1847 1848 if (s == phys_avail[i]) { 1849 phys_avail[i] += size; 1850 } else if (e == phys_avail[i + 1]) { 1851 phys_avail[i + 1] -= size; 1852 } else { 1853 for (j = phys_avail_count * 2; j > i; j -= 2) { 1854 phys_avail[j] = phys_avail[j - 2]; 1855 phys_avail[j + 1] = phys_avail[j - 1]; 1856 } 1857 1858 phys_avail[i + 3] = phys_avail[i + 1]; 1859 phys_avail[i + 1] = s; 1860 phys_avail[i + 2] = e; 1861 phys_avail_count++; 1862 } 1863 1864 return (s); 1865 } 1866 panic("moea_bootstrap_alloc: could not allocate memory"); 1867 } 1868 1869 static void 1870 moea_syncicache(vm_offset_t pa, vm_size_t len) 1871 { 1872 __syncicache((void *)pa, len); 1873 } 1874 1875 static int 1876 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head, 1877 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags) 1878 { 1879 struct pvo_entry *pvo; 1880 u_int sr; 1881 int first; 1882 u_int ptegidx; 1883 int i; 1884 int bootstrap; 1885 1886 moea_pvo_enter_calls++; 1887 first = 0; 1888 bootstrap = 0; 1889 1890 /* 1891 * Compute the PTE Group index. 1892 */ 1893 va &= ~ADDR_POFF; 1894 sr = va_to_sr(pm->pm_sr, va); 1895 ptegidx = va_to_pteg(sr, va); 1896 1897 /* 1898 * Remove any existing mapping for this page. Reuse the pvo entry if 1899 * there is a mapping. 1900 */ 1901 mtx_lock(&moea_table_mutex); 1902 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 1903 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 1904 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa && 1905 (pvo->pvo_pte.pte.pte_lo & PTE_PP) == 1906 (pte_lo & PTE_PP)) { 1907 mtx_unlock(&moea_table_mutex); 1908 return (0); 1909 } 1910 moea_pvo_remove(pvo, -1); 1911 break; 1912 } 1913 } 1914 1915 /* 1916 * If we aren't overwriting a mapping, try to allocate. 1917 */ 1918 if (moea_initialized) { 1919 pvo = uma_zalloc(zone, M_NOWAIT); 1920 } else { 1921 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) { 1922 panic("moea_enter: bpvo pool exhausted, %d, %d, %d", 1923 moea_bpvo_pool_index, BPVO_POOL_SIZE, 1924 BPVO_POOL_SIZE * sizeof(struct pvo_entry)); 1925 } 1926 pvo = &moea_bpvo_pool[moea_bpvo_pool_index]; 1927 moea_bpvo_pool_index++; 1928 bootstrap = 1; 1929 } 1930 1931 if (pvo == NULL) { 1932 mtx_unlock(&moea_table_mutex); 1933 return (ENOMEM); 1934 } 1935 1936 moea_pvo_entries++; 1937 pvo->pvo_vaddr = va; 1938 pvo->pvo_pmap = pm; 1939 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink); 1940 pvo->pvo_vaddr &= ~ADDR_POFF; 1941 if (flags & VM_PROT_EXECUTE) 1942 pvo->pvo_vaddr |= PVO_EXECUTABLE; 1943 if (flags & PVO_WIRED) 1944 pvo->pvo_vaddr |= PVO_WIRED; 1945 if (pvo_head != &moea_pvo_kunmanaged) 1946 pvo->pvo_vaddr |= PVO_MANAGED; 1947 if (bootstrap) 1948 pvo->pvo_vaddr |= PVO_BOOTSTRAP; 1949 if (flags & PVO_FAKE) 1950 pvo->pvo_vaddr |= PVO_FAKE; 1951 1952 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo); 1953 1954 /* 1955 * Remember if the list was empty and therefore will be the first 1956 * item. 1957 */ 1958 if (LIST_FIRST(pvo_head) == NULL) 1959 first = 1; 1960 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 1961 1962 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 1963 pm->pm_stats.wired_count++; 1964 pm->pm_stats.resident_count++; 1965 1966 /* 1967 * We hope this succeeds but it isn't required. 1968 */ 1969 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 1970 if (i >= 0) { 1971 PVO_PTEGIDX_SET(pvo, i); 1972 } else { 1973 panic("moea_pvo_enter: overflow"); 1974 moea_pte_overflow++; 1975 } 1976 mtx_unlock(&moea_table_mutex); 1977 1978 return (first ? ENOENT : 0); 1979 } 1980 1981 static void 1982 moea_pvo_remove(struct pvo_entry *pvo, int pteidx) 1983 { 1984 struct pte *pt; 1985 1986 /* 1987 * If there is an active pte entry, we need to deactivate it (and 1988 * save the ref & cfg bits). 1989 */ 1990 pt = moea_pvo_to_pte(pvo, pteidx); 1991 if (pt != NULL) { 1992 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr); 1993 mtx_unlock(&moea_table_mutex); 1994 PVO_PTEGIDX_CLR(pvo); 1995 } else { 1996 moea_pte_overflow--; 1997 } 1998 1999 /* 2000 * Update our statistics. 2001 */ 2002 pvo->pvo_pmap->pm_stats.resident_count--; 2003 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED) 2004 pvo->pvo_pmap->pm_stats.wired_count--; 2005 2006 /* 2007 * Save the REF/CHG bits into their cache if the page is managed. 2008 */ 2009 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) { 2010 struct vm_page *pg; 2011 2012 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN); 2013 if (pg != NULL) { 2014 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo & 2015 (PTE_REF | PTE_CHG)); 2016 } 2017 } 2018 2019 /* 2020 * Remove this PVO from the PV list. 2021 */ 2022 LIST_REMOVE(pvo, pvo_vlink); 2023 2024 /* 2025 * Remove this from the overflow list and return it to the pool 2026 * if we aren't going to reuse it. 2027 */ 2028 LIST_REMOVE(pvo, pvo_olink); 2029 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 2030 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone : 2031 moea_upvo_zone, pvo); 2032 moea_pvo_entries--; 2033 moea_pvo_remove_calls++; 2034 } 2035 2036 static __inline int 2037 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx) 2038 { 2039 int pteidx; 2040 2041 /* 2042 * We can find the actual pte entry without searching by grabbing 2043 * the PTEG index from 3 unused bits in pte_lo[11:9] and by 2044 * noticing the HID bit. 2045 */ 2046 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo); 2047 if (pvo->pvo_pte.pte.pte_hi & PTE_HID) 2048 pteidx ^= moea_pteg_mask * 8; 2049 2050 return (pteidx); 2051 } 2052 2053 static struct pvo_entry * 2054 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p) 2055 { 2056 struct pvo_entry *pvo; 2057 int ptegidx; 2058 u_int sr; 2059 2060 va &= ~ADDR_POFF; 2061 sr = va_to_sr(pm->pm_sr, va); 2062 ptegidx = va_to_pteg(sr, va); 2063 2064 mtx_lock(&moea_table_mutex); 2065 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2066 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) { 2067 if (pteidx_p) 2068 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx); 2069 break; 2070 } 2071 } 2072 mtx_unlock(&moea_table_mutex); 2073 2074 return (pvo); 2075 } 2076 2077 static struct pte * 2078 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx) 2079 { 2080 struct pte *pt; 2081 2082 /* 2083 * If we haven't been supplied the ptegidx, calculate it. 2084 */ 2085 if (pteidx == -1) { 2086 int ptegidx; 2087 u_int sr; 2088 2089 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr); 2090 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr); 2091 pteidx = moea_pvo_pte_index(pvo, ptegidx); 2092 } 2093 2094 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7]; 2095 mtx_lock(&moea_table_mutex); 2096 2097 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) { 2098 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no " 2099 "valid pte index", pvo); 2100 } 2101 2102 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) { 2103 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo " 2104 "pvo but no valid pte", pvo); 2105 } 2106 2107 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) { 2108 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) { 2109 panic("moea_pvo_to_pte: pvo %p has valid pte in " 2110 "moea_pteg_table %p but invalid in pvo", pvo, pt); 2111 } 2112 2113 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF)) 2114 != 0) { 2115 panic("moea_pvo_to_pte: pvo %p pte does not match " 2116 "pte %p in moea_pteg_table", pvo, pt); 2117 } 2118 2119 mtx_assert(&moea_table_mutex, MA_OWNED); 2120 return (pt); 2121 } 2122 2123 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) { 2124 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in " 2125 "moea_pteg_table but valid in pvo", pvo, pt); 2126 } 2127 2128 mtx_unlock(&moea_table_mutex); 2129 return (NULL); 2130 } 2131 2132 /* 2133 * XXX: THIS STUFF SHOULD BE IN pte.c? 2134 */ 2135 int 2136 moea_pte_spill(vm_offset_t addr) 2137 { 2138 struct pvo_entry *source_pvo, *victim_pvo; 2139 struct pvo_entry *pvo; 2140 int ptegidx, i, j; 2141 u_int sr; 2142 struct pteg *pteg; 2143 struct pte *pt; 2144 2145 moea_pte_spills++; 2146 2147 sr = mfsrin(addr); 2148 ptegidx = va_to_pteg(sr, addr); 2149 2150 /* 2151 * Have to substitute some entry. Use the primary hash for this. 2152 * Use low bits of timebase as random generator. 2153 */ 2154 pteg = &moea_pteg_table[ptegidx]; 2155 mtx_lock(&moea_table_mutex); 2156 __asm __volatile("mftb %0" : "=r"(i)); 2157 i &= 7; 2158 pt = &pteg->pt[i]; 2159 2160 source_pvo = NULL; 2161 victim_pvo = NULL; 2162 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) { 2163 /* 2164 * We need to find a pvo entry for this address. 2165 */ 2166 MOEA_PVO_CHECK(pvo); 2167 if (source_pvo == NULL && 2168 moea_pte_match(&pvo->pvo_pte.pte, sr, addr, 2169 pvo->pvo_pte.pte.pte_hi & PTE_HID)) { 2170 /* 2171 * Now found an entry to be spilled into the pteg. 2172 * The PTE is now valid, so we know it's active. 2173 */ 2174 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte); 2175 2176 if (j >= 0) { 2177 PVO_PTEGIDX_SET(pvo, j); 2178 moea_pte_overflow--; 2179 MOEA_PVO_CHECK(pvo); 2180 mtx_unlock(&moea_table_mutex); 2181 return (1); 2182 } 2183 2184 source_pvo = pvo; 2185 2186 if (victim_pvo != NULL) 2187 break; 2188 } 2189 2190 /* 2191 * We also need the pvo entry of the victim we are replacing 2192 * so save the R & C bits of the PTE. 2193 */ 2194 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL && 2195 moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2196 victim_pvo = pvo; 2197 if (source_pvo != NULL) 2198 break; 2199 } 2200 } 2201 2202 if (source_pvo == NULL) { 2203 mtx_unlock(&moea_table_mutex); 2204 return (0); 2205 } 2206 2207 if (victim_pvo == NULL) { 2208 if ((pt->pte_hi & PTE_HID) == 0) 2209 panic("moea_pte_spill: victim p-pte (%p) has no pvo" 2210 "entry", pt); 2211 2212 /* 2213 * If this is a secondary PTE, we need to search it's primary 2214 * pvo bucket for the matching PVO. 2215 */ 2216 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask], 2217 pvo_olink) { 2218 MOEA_PVO_CHECK(pvo); 2219 /* 2220 * We also need the pvo entry of the victim we are 2221 * replacing so save the R & C bits of the PTE. 2222 */ 2223 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) { 2224 victim_pvo = pvo; 2225 break; 2226 } 2227 } 2228 2229 if (victim_pvo == NULL) 2230 panic("moea_pte_spill: victim s-pte (%p) has no pvo" 2231 "entry", pt); 2232 } 2233 2234 /* 2235 * We are invalidating the TLB entry for the EA we are replacing even 2236 * though it's valid. If we don't, we lose any ref/chg bit changes 2237 * contained in the TLB entry. 2238 */ 2239 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID; 2240 2241 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr); 2242 moea_pte_set(pt, &source_pvo->pvo_pte.pte); 2243 2244 PVO_PTEGIDX_CLR(victim_pvo); 2245 PVO_PTEGIDX_SET(source_pvo, i); 2246 moea_pte_replacements++; 2247 2248 MOEA_PVO_CHECK(victim_pvo); 2249 MOEA_PVO_CHECK(source_pvo); 2250 2251 mtx_unlock(&moea_table_mutex); 2252 return (1); 2253 } 2254 2255 static int 2256 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt) 2257 { 2258 struct pte *pt; 2259 int i; 2260 2261 mtx_assert(&moea_table_mutex, MA_OWNED); 2262 2263 /* 2264 * First try primary hash. 2265 */ 2266 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2267 if ((pt->pte_hi & PTE_VALID) == 0) { 2268 pvo_pt->pte_hi &= ~PTE_HID; 2269 moea_pte_set(pt, pvo_pt); 2270 return (i); 2271 } 2272 } 2273 2274 /* 2275 * Now try secondary hash. 2276 */ 2277 ptegidx ^= moea_pteg_mask; 2278 2279 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) { 2280 if ((pt->pte_hi & PTE_VALID) == 0) { 2281 pvo_pt->pte_hi |= PTE_HID; 2282 moea_pte_set(pt, pvo_pt); 2283 return (i); 2284 } 2285 } 2286 2287 panic("moea_pte_insert: overflow"); 2288 return (-1); 2289 } 2290 2291 static boolean_t 2292 moea_query_bit(vm_page_t m, int ptebit) 2293 { 2294 struct pvo_entry *pvo; 2295 struct pte *pt; 2296 2297 if (moea_attr_fetch(m) & ptebit) 2298 return (TRUE); 2299 2300 vm_page_lock_queues(); 2301 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2302 MOEA_PVO_CHECK(pvo); /* sanity check */ 2303 2304 /* 2305 * See if we saved the bit off. If so, cache it and return 2306 * success. 2307 */ 2308 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2309 moea_attr_save(m, ptebit); 2310 MOEA_PVO_CHECK(pvo); /* sanity check */ 2311 vm_page_unlock_queues(); 2312 return (TRUE); 2313 } 2314 } 2315 2316 /* 2317 * No luck, now go through the hard part of looking at the PTEs 2318 * themselves. Sync so that any pending REF/CHG bits are flushed to 2319 * the PTEs. 2320 */ 2321 powerpc_sync(); 2322 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2323 MOEA_PVO_CHECK(pvo); /* sanity check */ 2324 2325 /* 2326 * See if this pvo has a valid PTE. if so, fetch the 2327 * REF/CHG bits from the valid PTE. If the appropriate 2328 * ptebit is set, cache it and return success. 2329 */ 2330 pt = moea_pvo_to_pte(pvo, -1); 2331 if (pt != NULL) { 2332 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2333 mtx_unlock(&moea_table_mutex); 2334 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2335 moea_attr_save(m, ptebit); 2336 MOEA_PVO_CHECK(pvo); /* sanity check */ 2337 vm_page_unlock_queues(); 2338 return (TRUE); 2339 } 2340 } 2341 } 2342 2343 vm_page_unlock_queues(); 2344 return (FALSE); 2345 } 2346 2347 static u_int 2348 moea_clear_bit(vm_page_t m, int ptebit) 2349 { 2350 u_int count; 2351 struct pvo_entry *pvo; 2352 struct pte *pt; 2353 2354 vm_page_lock_queues(); 2355 2356 /* 2357 * Clear the cached value. 2358 */ 2359 moea_attr_clear(m, ptebit); 2360 2361 /* 2362 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2363 * we can reset the right ones). note that since the pvo entries and 2364 * list heads are accessed via BAT0 and are never placed in the page 2365 * table, we don't have to worry about further accesses setting the 2366 * REF/CHG bits. 2367 */ 2368 powerpc_sync(); 2369 2370 /* 2371 * For each pvo entry, clear the pvo's ptebit. If this pvo has a 2372 * valid pte clear the ptebit from the valid pte. 2373 */ 2374 count = 0; 2375 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2376 MOEA_PVO_CHECK(pvo); /* sanity check */ 2377 pt = moea_pvo_to_pte(pvo, -1); 2378 if (pt != NULL) { 2379 moea_pte_synch(pt, &pvo->pvo_pte.pte); 2380 if (pvo->pvo_pte.pte.pte_lo & ptebit) { 2381 count++; 2382 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit); 2383 } 2384 mtx_unlock(&moea_table_mutex); 2385 } 2386 pvo->pvo_pte.pte.pte_lo &= ~ptebit; 2387 MOEA_PVO_CHECK(pvo); /* sanity check */ 2388 } 2389 2390 vm_page_unlock_queues(); 2391 return (count); 2392 } 2393 2394 /* 2395 * Return true if the physical range is encompassed by the battable[idx] 2396 */ 2397 static int 2398 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size) 2399 { 2400 u_int prot; 2401 u_int32_t start; 2402 u_int32_t end; 2403 u_int32_t bat_ble; 2404 2405 /* 2406 * Return immediately if not a valid mapping 2407 */ 2408 if (!(battable[idx].batu & BAT_Vs)) 2409 return (EINVAL); 2410 2411 /* 2412 * The BAT entry must be cache-inhibited, guarded, and r/w 2413 * so it can function as an i/o page 2414 */ 2415 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW); 2416 if (prot != (BAT_I|BAT_G|BAT_PP_RW)) 2417 return (EPERM); 2418 2419 /* 2420 * The address should be within the BAT range. Assume that the 2421 * start address in the BAT has the correct alignment (thus 2422 * not requiring masking) 2423 */ 2424 start = battable[idx].batl & BAT_PBS; 2425 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03; 2426 end = start | (bat_ble << 15) | 0x7fff; 2427 2428 if ((pa < start) || ((pa + size) > end)) 2429 return (ERANGE); 2430 2431 return (0); 2432 } 2433 2434 boolean_t 2435 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2436 { 2437 int i; 2438 2439 /* 2440 * This currently does not work for entries that 2441 * overlap 256M BAT segments. 2442 */ 2443 2444 for(i = 0; i < 16; i++) 2445 if (moea_bat_mapped(i, pa, size) == 0) 2446 return (0); 2447 2448 return (EFAULT); 2449 } 2450 2451 /* 2452 * Map a set of physical memory pages into the kernel virtual 2453 * address space. Return a pointer to where it is mapped. This 2454 * routine is intended to be used for mapping device memory, 2455 * NOT real memory. 2456 */ 2457 void * 2458 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2459 { 2460 2461 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2462 } 2463 2464 void * 2465 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma) 2466 { 2467 vm_offset_t va, tmpva, ppa, offset; 2468 int i; 2469 2470 ppa = trunc_page(pa); 2471 offset = pa & PAGE_MASK; 2472 size = roundup(offset + size, PAGE_SIZE); 2473 2474 /* 2475 * If the physical address lies within a valid BAT table entry, 2476 * return the 1:1 mapping. This currently doesn't work 2477 * for regions that overlap 256M BAT segments. 2478 */ 2479 for (i = 0; i < 16; i++) { 2480 if (moea_bat_mapped(i, pa, size) == 0) 2481 return ((void *) pa); 2482 } 2483 2484 va = kmem_alloc_nofault(kernel_map, size); 2485 if (!va) 2486 panic("moea_mapdev: Couldn't alloc kernel virtual memory"); 2487 2488 for (tmpva = va; size > 0;) { 2489 moea_kenter_attr(mmu, tmpva, ppa, ma); 2490 tlbie(tmpva); 2491 size -= PAGE_SIZE; 2492 tmpva += PAGE_SIZE; 2493 ppa += PAGE_SIZE; 2494 } 2495 2496 return ((void *)(va + offset)); 2497 } 2498 2499 void 2500 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2501 { 2502 vm_offset_t base, offset; 2503 2504 /* 2505 * If this is outside kernel virtual space, then it's a 2506 * battable entry and doesn't require unmapping 2507 */ 2508 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) { 2509 base = trunc_page(va); 2510 offset = va & PAGE_MASK; 2511 size = roundup(offset + size, PAGE_SIZE); 2512 kmem_free(kernel_map, base, size); 2513 } 2514 } 2515 2516 static void 2517 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2518 { 2519 struct pvo_entry *pvo; 2520 vm_offset_t lim; 2521 vm_paddr_t pa; 2522 vm_size_t len; 2523 2524 PMAP_LOCK(pm); 2525 while (sz > 0) { 2526 lim = round_page(va); 2527 len = MIN(lim - va, sz); 2528 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL); 2529 if (pvo != NULL) { 2530 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | 2531 (va & ADDR_POFF); 2532 moea_syncicache(pa, len); 2533 } 2534 va += len; 2535 sz -= len; 2536 } 2537 PMAP_UNLOCK(pm); 2538 } 2539