1 /*- 2 * Copyright (c) 2008-2015 Nathan Whitehorn 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 /* 31 * Manages physical address maps. 32 * 33 * Since the information managed by this module is also stored by the 34 * logical address mapping module, this module may throw away valid virtual 35 * to physical mappings at almost any time. However, invalidations of 36 * mappings must be done as requested. 37 * 38 * In order to cope with hardware architectures which make virtual to 39 * physical map invalidates expensive, this module may delay invalidate 40 * reduced protection operations until such time as they are actually 41 * necessary. This module is given full information as to which processors 42 * are currently using which maps, and to when physical maps must be made 43 * correct. 44 */ 45 46 #include "opt_compat.h" 47 #include "opt_kstack_pages.h" 48 49 #include <sys/param.h> 50 #include <sys/kernel.h> 51 #include <sys/conf.h> 52 #include <sys/queue.h> 53 #include <sys/cpuset.h> 54 #include <sys/kerneldump.h> 55 #include <sys/ktr.h> 56 #include <sys/lock.h> 57 #include <sys/msgbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/mutex.h> 60 #include <sys/proc.h> 61 #include <sys/rwlock.h> 62 #include <sys/sched.h> 63 #include <sys/sysctl.h> 64 #include <sys/systm.h> 65 #include <sys/vmmeter.h> 66 #include <sys/smp.h> 67 68 #include <sys/kdb.h> 69 70 #include <dev/ofw/openfirm.h> 71 72 #include <vm/vm.h> 73 #include <vm/vm_param.h> 74 #include <vm/vm_kern.h> 75 #include <vm/vm_page.h> 76 #include <vm/vm_map.h> 77 #include <vm/vm_object.h> 78 #include <vm/vm_extern.h> 79 #include <vm/vm_pageout.h> 80 #include <vm/uma.h> 81 82 #include <machine/_inttypes.h> 83 #include <machine/cpu.h> 84 #include <machine/platform.h> 85 #include <machine/frame.h> 86 #include <machine/md_var.h> 87 #include <machine/psl.h> 88 #include <machine/bat.h> 89 #include <machine/hid.h> 90 #include <machine/pte.h> 91 #include <machine/sr.h> 92 #include <machine/trap.h> 93 #include <machine/mmuvar.h> 94 95 #include "mmu_oea64.h" 96 #include "mmu_if.h" 97 #include "moea64_if.h" 98 99 void moea64_release_vsid(uint64_t vsid); 100 uintptr_t moea64_get_unique_vsid(void); 101 102 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 103 #define ENABLE_TRANS(msr) mtmsr(msr) 104 105 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 106 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 107 #define VSID_HASH_MASK 0x0000007fffffffffULL 108 109 /* 110 * Locking semantics: 111 * 112 * There are two locks of interest: the page locks and the pmap locks, which 113 * protect their individual PVO lists and are locked in that order. The contents 114 * of all PVO entries are protected by the locks of their respective pmaps. 115 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 116 * into any list. 117 * 118 */ 119 120 #define PV_LOCK_COUNT PA_LOCK_COUNT*3 121 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 122 123 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT])) 124 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 125 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 126 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 127 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 128 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 129 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 130 131 struct ofw_map { 132 cell_t om_va; 133 cell_t om_len; 134 uint64_t om_pa; 135 cell_t om_mode; 136 }; 137 138 extern unsigned char _etext[]; 139 extern unsigned char _end[]; 140 141 /* 142 * Map of physical memory regions. 143 */ 144 static struct mem_region *regions; 145 static struct mem_region *pregions; 146 static u_int phys_avail_count; 147 static int regions_sz, pregions_sz; 148 149 extern void bs_remap_earlyboot(void); 150 151 /* 152 * Lock for the SLB tables. 153 */ 154 struct mtx moea64_slb_mutex; 155 156 /* 157 * PTEG data. 158 */ 159 u_int moea64_pteg_count; 160 u_int moea64_pteg_mask; 161 162 /* 163 * PVO data. 164 */ 165 166 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 167 168 static struct pvo_entry *moea64_bpvo_pool; 169 static int moea64_bpvo_pool_index = 0; 170 static int moea64_bpvo_pool_size = 327680; 171 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 172 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 173 &moea64_bpvo_pool_index, 0, ""); 174 175 #define VSID_NBPW (sizeof(u_int32_t) * 8) 176 #ifdef __powerpc64__ 177 #define NVSIDS (NPMAPS * 16) 178 #define VSID_HASHMASK 0xffffffffUL 179 #else 180 #define NVSIDS NPMAPS 181 #define VSID_HASHMASK 0xfffffUL 182 #endif 183 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 184 185 static boolean_t moea64_initialized = FALSE; 186 187 /* 188 * Statistics. 189 */ 190 u_int moea64_pte_valid = 0; 191 u_int moea64_pte_overflow = 0; 192 u_int moea64_pvo_entries = 0; 193 u_int moea64_pvo_enter_calls = 0; 194 u_int moea64_pvo_remove_calls = 0; 195 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 196 &moea64_pte_valid, 0, ""); 197 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 198 &moea64_pte_overflow, 0, ""); 199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 200 &moea64_pvo_entries, 0, ""); 201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 202 &moea64_pvo_enter_calls, 0, ""); 203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 204 &moea64_pvo_remove_calls, 0, ""); 205 206 vm_offset_t moea64_scratchpage_va[2]; 207 struct pvo_entry *moea64_scratchpage_pvo[2]; 208 struct mtx moea64_scratchpage_mtx; 209 210 uint64_t moea64_large_page_mask = 0; 211 uint64_t moea64_large_page_size = 0; 212 int moea64_large_page_shift = 0; 213 214 /* 215 * PVO calls. 216 */ 217 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, 218 struct pvo_head *pvo_head); 219 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo); 220 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo); 221 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 222 223 /* 224 * Utility routines. 225 */ 226 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t); 227 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t); 228 static void moea64_kremove(mmu_t, vm_offset_t); 229 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va, 230 vm_paddr_t pa, vm_size_t sz); 231 static void moea64_pmap_init_qpages(void); 232 233 /* 234 * Kernel MMU interface 235 */ 236 void moea64_clear_modify(mmu_t, vm_page_t); 237 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t); 238 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 239 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 240 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 241 u_int flags, int8_t psind); 242 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 243 vm_prot_t); 244 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 245 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t); 246 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t); 247 void moea64_init(mmu_t); 248 boolean_t moea64_is_modified(mmu_t, vm_page_t); 249 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 250 boolean_t moea64_is_referenced(mmu_t, vm_page_t); 251 int moea64_ts_referenced(mmu_t, vm_page_t); 252 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 253 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t); 254 int moea64_page_wired_mappings(mmu_t, vm_page_t); 255 void moea64_pinit(mmu_t, pmap_t); 256 void moea64_pinit0(mmu_t, pmap_t); 257 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 258 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 259 void moea64_qremove(mmu_t, vm_offset_t, int); 260 void moea64_release(mmu_t, pmap_t); 261 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 262 void moea64_remove_pages(mmu_t, pmap_t); 263 void moea64_remove_all(mmu_t, vm_page_t); 264 void moea64_remove_write(mmu_t, vm_page_t); 265 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 266 void moea64_zero_page(mmu_t, vm_page_t); 267 void moea64_zero_page_area(mmu_t, vm_page_t, int, int); 268 void moea64_activate(mmu_t, struct thread *); 269 void moea64_deactivate(mmu_t, struct thread *); 270 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t); 271 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 272 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t); 273 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t); 274 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma); 275 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma); 276 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t); 277 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 278 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t); 279 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, 280 void **va); 281 void moea64_scan_init(mmu_t mmu); 282 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m); 283 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr); 284 285 static mmu_method_t moea64_methods[] = { 286 MMUMETHOD(mmu_clear_modify, moea64_clear_modify), 287 MMUMETHOD(mmu_copy_page, moea64_copy_page), 288 MMUMETHOD(mmu_copy_pages, moea64_copy_pages), 289 MMUMETHOD(mmu_enter, moea64_enter), 290 MMUMETHOD(mmu_enter_object, moea64_enter_object), 291 MMUMETHOD(mmu_enter_quick, moea64_enter_quick), 292 MMUMETHOD(mmu_extract, moea64_extract), 293 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold), 294 MMUMETHOD(mmu_init, moea64_init), 295 MMUMETHOD(mmu_is_modified, moea64_is_modified), 296 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable), 297 MMUMETHOD(mmu_is_referenced, moea64_is_referenced), 298 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced), 299 MMUMETHOD(mmu_map, moea64_map), 300 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick), 301 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings), 302 MMUMETHOD(mmu_pinit, moea64_pinit), 303 MMUMETHOD(mmu_pinit0, moea64_pinit0), 304 MMUMETHOD(mmu_protect, moea64_protect), 305 MMUMETHOD(mmu_qenter, moea64_qenter), 306 MMUMETHOD(mmu_qremove, moea64_qremove), 307 MMUMETHOD(mmu_release, moea64_release), 308 MMUMETHOD(mmu_remove, moea64_remove), 309 MMUMETHOD(mmu_remove_pages, moea64_remove_pages), 310 MMUMETHOD(mmu_remove_all, moea64_remove_all), 311 MMUMETHOD(mmu_remove_write, moea64_remove_write), 312 MMUMETHOD(mmu_sync_icache, moea64_sync_icache), 313 MMUMETHOD(mmu_unwire, moea64_unwire), 314 MMUMETHOD(mmu_zero_page, moea64_zero_page), 315 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area), 316 MMUMETHOD(mmu_activate, moea64_activate), 317 MMUMETHOD(mmu_deactivate, moea64_deactivate), 318 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr), 319 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page), 320 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page), 321 322 /* Internal interfaces */ 323 MMUMETHOD(mmu_mapdev, moea64_mapdev), 324 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr), 325 MMUMETHOD(mmu_unmapdev, moea64_unmapdev), 326 MMUMETHOD(mmu_kextract, moea64_kextract), 327 MMUMETHOD(mmu_kenter, moea64_kenter), 328 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr), 329 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped), 330 MMUMETHOD(mmu_scan_init, moea64_scan_init), 331 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map), 332 333 { 0, 0 } 334 }; 335 336 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0); 337 338 static struct pvo_head * 339 vm_page_to_pvoh(vm_page_t m) 340 { 341 342 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 343 return (&m->md.mdpg_pvoh); 344 } 345 346 static struct pvo_entry * 347 alloc_pvo_entry(int bootstrap) 348 { 349 struct pvo_entry *pvo; 350 351 if (!moea64_initialized || bootstrap) { 352 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 353 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd", 354 moea64_bpvo_pool_index, moea64_bpvo_pool_size, 355 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 356 } 357 pvo = &moea64_bpvo_pool[ 358 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 359 bzero(pvo, sizeof(*pvo)); 360 pvo->pvo_vaddr = PVO_BOOTSTRAP; 361 } else { 362 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT); 363 bzero(pvo, sizeof(*pvo)); 364 } 365 366 return (pvo); 367 } 368 369 370 static void 371 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 372 { 373 uint64_t vsid; 374 uint64_t hash; 375 int shift; 376 377 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 378 379 pvo->pvo_pmap = pmap; 380 va &= ~ADDR_POFF; 381 pvo->pvo_vaddr |= va; 382 vsid = va_to_vsid(pmap, va); 383 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 384 | (vsid << 16); 385 386 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 387 ADDR_PIDX_SHFT; 388 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 389 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 390 } 391 392 static void 393 free_pvo_entry(struct pvo_entry *pvo) 394 { 395 396 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 397 uma_zfree(moea64_pvo_zone, pvo); 398 } 399 400 void 401 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 402 { 403 404 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) & 405 LPTE_AVPN_MASK; 406 lpte->pte_hi |= LPTE_VALID; 407 408 if (pvo->pvo_vaddr & PVO_LARGE) 409 lpte->pte_hi |= LPTE_BIG; 410 if (pvo->pvo_vaddr & PVO_WIRED) 411 lpte->pte_hi |= LPTE_WIRED; 412 if (pvo->pvo_vaddr & PVO_HID) 413 lpte->pte_hi |= LPTE_HID; 414 415 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 416 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 417 lpte->pte_lo |= LPTE_BW; 418 else 419 lpte->pte_lo |= LPTE_BR; 420 421 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 422 lpte->pte_lo |= LPTE_NOEXEC; 423 } 424 425 static __inline uint64_t 426 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 427 { 428 uint64_t pte_lo; 429 int i; 430 431 if (ma != VM_MEMATTR_DEFAULT) { 432 switch (ma) { 433 case VM_MEMATTR_UNCACHEABLE: 434 return (LPTE_I | LPTE_G); 435 case VM_MEMATTR_CACHEABLE: 436 return (LPTE_M); 437 case VM_MEMATTR_WRITE_COMBINING: 438 case VM_MEMATTR_WRITE_BACK: 439 case VM_MEMATTR_PREFETCHABLE: 440 return (LPTE_I); 441 case VM_MEMATTR_WRITE_THROUGH: 442 return (LPTE_W | LPTE_M); 443 } 444 } 445 446 /* 447 * Assume the page is cache inhibited and access is guarded unless 448 * it's in our available memory array. 449 */ 450 pte_lo = LPTE_I | LPTE_G; 451 for (i = 0; i < pregions_sz; i++) { 452 if ((pa >= pregions[i].mr_start) && 453 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 454 pte_lo &= ~(LPTE_I | LPTE_G); 455 pte_lo |= LPTE_M; 456 break; 457 } 458 } 459 460 return pte_lo; 461 } 462 463 /* 464 * Quick sort callout for comparing memory regions. 465 */ 466 static int om_cmp(const void *a, const void *b); 467 468 static int 469 om_cmp(const void *a, const void *b) 470 { 471 const struct ofw_map *mapa; 472 const struct ofw_map *mapb; 473 474 mapa = a; 475 mapb = b; 476 if (mapa->om_pa < mapb->om_pa) 477 return (-1); 478 else if (mapa->om_pa > mapb->om_pa) 479 return (1); 480 else 481 return (0); 482 } 483 484 static void 485 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz) 486 { 487 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 488 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 489 struct pvo_entry *pvo; 490 register_t msr; 491 vm_offset_t off; 492 vm_paddr_t pa_base; 493 int i, j; 494 495 bzero(translations, sz); 496 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 497 sizeof(acells)); 498 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 499 panic("moea64_bootstrap: can't get ofw translations"); 500 501 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 502 sz /= sizeof(cell_t); 503 for (i = 0, j = 0; i < sz; j++) { 504 translations[j].om_va = trans_cells[i++]; 505 translations[j].om_len = trans_cells[i++]; 506 translations[j].om_pa = trans_cells[i++]; 507 if (acells == 2) { 508 translations[j].om_pa <<= 32; 509 translations[j].om_pa |= trans_cells[i++]; 510 } 511 translations[j].om_mode = trans_cells[i++]; 512 } 513 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 514 i, sz)); 515 516 sz = j; 517 qsort(translations, sz, sizeof (*translations), om_cmp); 518 519 for (i = 0; i < sz; i++) { 520 pa_base = translations[i].om_pa; 521 #ifndef __powerpc64__ 522 if ((translations[i].om_pa >> 32) != 0) 523 panic("OFW translations above 32-bit boundary!"); 524 #endif 525 526 if (pa_base % PAGE_SIZE) 527 panic("OFW translation not page-aligned (phys)!"); 528 if (translations[i].om_va % PAGE_SIZE) 529 panic("OFW translation not page-aligned (virt)!"); 530 531 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 532 pa_base, translations[i].om_va, translations[i].om_len); 533 534 /* Now enter the pages for this mapping */ 535 536 DISABLE_TRANS(msr); 537 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 538 /* If this address is direct-mapped, skip remapping */ 539 if (hw_direct_map && translations[i].om_va == pa_base && 540 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M) 541 continue; 542 543 PMAP_LOCK(kernel_pmap); 544 pvo = moea64_pvo_find_va(kernel_pmap, 545 translations[i].om_va + off); 546 PMAP_UNLOCK(kernel_pmap); 547 if (pvo != NULL) 548 continue; 549 550 moea64_kenter(mmup, translations[i].om_va + off, 551 pa_base + off); 552 } 553 ENABLE_TRANS(msr); 554 } 555 } 556 557 #ifdef __powerpc64__ 558 static void 559 moea64_probe_large_page(void) 560 { 561 uint16_t pvr = mfpvr() >> 16; 562 563 switch (pvr) { 564 case IBM970: 565 case IBM970FX: 566 case IBM970MP: 567 powerpc_sync(); isync(); 568 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 569 powerpc_sync(); isync(); 570 571 /* FALLTHROUGH */ 572 default: 573 moea64_large_page_size = 0x1000000; /* 16 MB */ 574 moea64_large_page_shift = 24; 575 } 576 577 moea64_large_page_mask = moea64_large_page_size - 1; 578 } 579 580 static void 581 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 582 { 583 struct slb *cache; 584 struct slb entry; 585 uint64_t esid, slbe; 586 uint64_t i; 587 588 cache = PCPU_GET(slb); 589 esid = va >> ADDR_SR_SHFT; 590 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 591 592 for (i = 0; i < 64; i++) { 593 if (cache[i].slbe == (slbe | i)) 594 return; 595 } 596 597 entry.slbe = slbe; 598 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 599 if (large) 600 entry.slbv |= SLBV_L; 601 602 slb_insert_kernel(entry.slbe, entry.slbv); 603 } 604 #endif 605 606 static void 607 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart, 608 vm_offset_t kernelend) 609 { 610 struct pvo_entry *pvo; 611 register_t msr; 612 vm_paddr_t pa; 613 vm_offset_t size, off; 614 uint64_t pte_lo; 615 int i; 616 617 if (moea64_large_page_size == 0) 618 hw_direct_map = 0; 619 620 DISABLE_TRANS(msr); 621 if (hw_direct_map) { 622 PMAP_LOCK(kernel_pmap); 623 for (i = 0; i < pregions_sz; i++) { 624 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 625 pregions[i].mr_size; pa += moea64_large_page_size) { 626 pte_lo = LPTE_M; 627 628 pvo = alloc_pvo_entry(1 /* bootstrap */); 629 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 630 init_pvo_entry(pvo, kernel_pmap, pa); 631 632 /* 633 * Set memory access as guarded if prefetch within 634 * the page could exit the available physmem area. 635 */ 636 if (pa & moea64_large_page_mask) { 637 pa &= moea64_large_page_mask; 638 pte_lo |= LPTE_G; 639 } 640 if (pa + moea64_large_page_size > 641 pregions[i].mr_start + pregions[i].mr_size) 642 pte_lo |= LPTE_G; 643 644 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 645 VM_PROT_EXECUTE; 646 pvo->pvo_pte.pa = pa | pte_lo; 647 moea64_pvo_enter(mmup, pvo, NULL); 648 } 649 } 650 PMAP_UNLOCK(kernel_pmap); 651 } else { 652 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 653 off = (vm_offset_t)(moea64_bpvo_pool); 654 for (pa = off; pa < off + size; pa += PAGE_SIZE) 655 moea64_kenter(mmup, pa, pa); 656 657 /* 658 * Map certain important things, like ourselves. 659 * 660 * NOTE: We do not map the exception vector space. That code is 661 * used only in real mode, and leaving it unmapped allows us to 662 * catch NULL pointer deferences, instead of making NULL a valid 663 * address. 664 */ 665 666 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 667 pa += PAGE_SIZE) 668 moea64_kenter(mmup, pa, pa); 669 } 670 ENABLE_TRANS(msr); 671 672 /* 673 * Allow user to override unmapped_buf_allowed for testing. 674 * XXXKIB Only direct map implementation was tested. 675 */ 676 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 677 &unmapped_buf_allowed)) 678 unmapped_buf_allowed = hw_direct_map; 679 } 680 681 void 682 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 683 { 684 int i, j; 685 vm_size_t physsz, hwphyssz; 686 687 #ifndef __powerpc64__ 688 /* We don't have a direct map since there is no BAT */ 689 hw_direct_map = 0; 690 691 /* Make sure battable is zero, since we have no BAT */ 692 for (i = 0; i < 16; i++) { 693 battable[i].batu = 0; 694 battable[i].batl = 0; 695 } 696 #else 697 moea64_probe_large_page(); 698 699 /* Use a direct map if we have large page support */ 700 if (moea64_large_page_size > 0) 701 hw_direct_map = 1; 702 else 703 hw_direct_map = 0; 704 #endif 705 706 /* Get physical memory regions from firmware */ 707 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 708 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 709 710 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz) 711 panic("moea64_bootstrap: phys_avail too small"); 712 713 phys_avail_count = 0; 714 physsz = 0; 715 hwphyssz = 0; 716 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 717 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 718 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 719 regions[i].mr_start, regions[i].mr_start + 720 regions[i].mr_size, regions[i].mr_size); 721 if (hwphyssz != 0 && 722 (physsz + regions[i].mr_size) >= hwphyssz) { 723 if (physsz < hwphyssz) { 724 phys_avail[j] = regions[i].mr_start; 725 phys_avail[j + 1] = regions[i].mr_start + 726 hwphyssz - physsz; 727 physsz = hwphyssz; 728 phys_avail_count++; 729 } 730 break; 731 } 732 phys_avail[j] = regions[i].mr_start; 733 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 734 phys_avail_count++; 735 physsz += regions[i].mr_size; 736 } 737 738 /* Check for overlap with the kernel and exception vectors */ 739 for (j = 0; j < 2*phys_avail_count; j+=2) { 740 if (phys_avail[j] < EXC_LAST) 741 phys_avail[j] += EXC_LAST; 742 743 if (kernelstart >= phys_avail[j] && 744 kernelstart < phys_avail[j+1]) { 745 if (kernelend < phys_avail[j+1]) { 746 phys_avail[2*phys_avail_count] = 747 (kernelend & ~PAGE_MASK) + PAGE_SIZE; 748 phys_avail[2*phys_avail_count + 1] = 749 phys_avail[j+1]; 750 phys_avail_count++; 751 } 752 753 phys_avail[j+1] = kernelstart & ~PAGE_MASK; 754 } 755 756 if (kernelend >= phys_avail[j] && 757 kernelend < phys_avail[j+1]) { 758 if (kernelstart > phys_avail[j]) { 759 phys_avail[2*phys_avail_count] = phys_avail[j]; 760 phys_avail[2*phys_avail_count + 1] = 761 kernelstart & ~PAGE_MASK; 762 phys_avail_count++; 763 } 764 765 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE; 766 } 767 } 768 769 physmem = btoc(physsz); 770 771 #ifdef PTEGCOUNT 772 moea64_pteg_count = PTEGCOUNT; 773 #else 774 moea64_pteg_count = 0x1000; 775 776 while (moea64_pteg_count < physmem) 777 moea64_pteg_count <<= 1; 778 779 moea64_pteg_count >>= 1; 780 #endif /* PTEGCOUNT */ 781 } 782 783 void 784 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 785 { 786 int i; 787 788 /* 789 * Set PTEG mask 790 */ 791 moea64_pteg_mask = moea64_pteg_count - 1; 792 793 /* 794 * Initialize SLB table lock and page locks 795 */ 796 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 797 for (i = 0; i < PV_LOCK_COUNT; i++) 798 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 799 800 /* 801 * Initialise the bootstrap pvo pool. 802 */ 803 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 804 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0); 805 moea64_bpvo_pool_index = 0; 806 807 /* 808 * Make sure kernel vsid is allocated as well as VSID 0. 809 */ 810 #ifndef __powerpc64__ 811 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 812 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 813 moea64_vsid_bitmap[0] |= 1; 814 #endif 815 816 /* 817 * Initialize the kernel pmap (which is statically allocated). 818 */ 819 #ifdef __powerpc64__ 820 for (i = 0; i < 64; i++) { 821 pcpup->pc_slb[i].slbv = 0; 822 pcpup->pc_slb[i].slbe = 0; 823 } 824 #else 825 for (i = 0; i < 16; i++) 826 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 827 #endif 828 829 kernel_pmap->pmap_phys = kernel_pmap; 830 CPU_FILL(&kernel_pmap->pm_active); 831 RB_INIT(&kernel_pmap->pmap_pvo); 832 833 PMAP_LOCK_INIT(kernel_pmap); 834 835 /* 836 * Now map in all the other buffers we allocated earlier 837 */ 838 839 moea64_setup_direct_map(mmup, kernelstart, kernelend); 840 } 841 842 void 843 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) 844 { 845 ihandle_t mmui; 846 phandle_t chosen; 847 phandle_t mmu; 848 ssize_t sz; 849 int i; 850 vm_offset_t pa, va; 851 void *dpcpu; 852 853 /* 854 * Set up the Open Firmware pmap and add its mappings if not in real 855 * mode. 856 */ 857 858 chosen = OF_finddevice("/chosen"); 859 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 860 mmu = OF_instance_to_package(mmui); 861 if (mmu == -1 || 862 (sz = OF_getproplen(mmu, "translations")) == -1) 863 sz = 0; 864 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 865 panic("moea64_bootstrap: too many ofw translations"); 866 867 if (sz > 0) 868 moea64_add_ofw_mappings(mmup, mmu, sz); 869 } 870 871 /* 872 * Calculate the last available physical address. 873 */ 874 for (i = 0; phys_avail[i + 2] != 0; i += 2) 875 ; 876 Maxmem = powerpc_btop(phys_avail[i + 1]); 877 878 /* 879 * Initialize MMU and remap early physical mappings 880 */ 881 MMU_CPU_BOOTSTRAP(mmup,0); 882 mtmsr(mfmsr() | PSL_DR | PSL_IR); 883 pmap_bootstrapped++; 884 bs_remap_earlyboot(); 885 886 /* 887 * Set the start and end of kva. 888 */ 889 virtual_avail = VM_MIN_KERNEL_ADDRESS; 890 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 891 892 /* 893 * Map the entire KVA range into the SLB. We must not fault there. 894 */ 895 #ifdef __powerpc64__ 896 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 897 moea64_bootstrap_slb_prefault(va, 0); 898 #endif 899 900 /* 901 * Figure out how far we can extend virtual_end into segment 16 902 * without running into existing mappings. Segment 16 is guaranteed 903 * to contain neither RAM nor devices (at least on Apple hardware), 904 * but will generally contain some OFW mappings we should not 905 * step on. 906 */ 907 908 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 909 PMAP_LOCK(kernel_pmap); 910 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 911 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 912 virtual_end += PAGE_SIZE; 913 PMAP_UNLOCK(kernel_pmap); 914 #endif 915 916 /* 917 * Allocate a kernel stack with a guard page for thread0 and map it 918 * into the kernel page map. 919 */ 920 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 921 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 922 virtual_avail = va + kstack_pages * PAGE_SIZE; 923 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 924 thread0.td_kstack = va; 925 thread0.td_kstack_pages = kstack_pages; 926 for (i = 0; i < kstack_pages; i++) { 927 moea64_kenter(mmup, va, pa); 928 pa += PAGE_SIZE; 929 va += PAGE_SIZE; 930 } 931 932 /* 933 * Allocate virtual address space for the message buffer. 934 */ 935 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 936 msgbufp = (struct msgbuf *)virtual_avail; 937 va = virtual_avail; 938 virtual_avail += round_page(msgbufsize); 939 while (va < virtual_avail) { 940 moea64_kenter(mmup, va, pa); 941 pa += PAGE_SIZE; 942 va += PAGE_SIZE; 943 } 944 945 /* 946 * Allocate virtual address space for the dynamic percpu area. 947 */ 948 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 949 dpcpu = (void *)virtual_avail; 950 va = virtual_avail; 951 virtual_avail += DPCPU_SIZE; 952 while (va < virtual_avail) { 953 moea64_kenter(mmup, va, pa); 954 pa += PAGE_SIZE; 955 va += PAGE_SIZE; 956 } 957 dpcpu_init(dpcpu, 0); 958 959 /* 960 * Allocate some things for page zeroing. We put this directly 961 * in the page table and use MOEA64_PTE_REPLACE to avoid any 962 * of the PVO book-keeping or other parts of the VM system 963 * from even knowing that this hack exists. 964 */ 965 966 if (!hw_direct_map) { 967 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 968 MTX_DEF); 969 for (i = 0; i < 2; i++) { 970 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 971 virtual_end -= PAGE_SIZE; 972 973 moea64_kenter(mmup, moea64_scratchpage_va[i], 0); 974 975 PMAP_LOCK(kernel_pmap); 976 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 977 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 978 PMAP_UNLOCK(kernel_pmap); 979 } 980 } 981 } 982 983 static void 984 moea64_pmap_init_qpages(void) 985 { 986 struct pcpu *pc; 987 int i; 988 989 if (hw_direct_map) 990 return; 991 992 CPU_FOREACH(i) { 993 pc = pcpu_find(i); 994 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 995 if (pc->pc_qmap_addr == 0) 996 panic("pmap_init_qpages: unable to allocate KVA"); 997 PMAP_LOCK(kernel_pmap); 998 pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 999 PMAP_UNLOCK(kernel_pmap); 1000 mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF); 1001 } 1002 } 1003 1004 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1005 1006 /* 1007 * Activate a user pmap. This mostly involves setting some non-CPU 1008 * state. 1009 */ 1010 void 1011 moea64_activate(mmu_t mmu, struct thread *td) 1012 { 1013 pmap_t pm; 1014 1015 pm = &td->td_proc->p_vmspace->vm_pmap; 1016 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1017 1018 #ifdef __powerpc64__ 1019 PCPU_SET(userslb, pm->pm_slb); 1020 __asm __volatile("slbmte %0, %1; isync" :: 1021 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1022 #else 1023 PCPU_SET(curpmap, pm->pmap_phys); 1024 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1025 #endif 1026 } 1027 1028 void 1029 moea64_deactivate(mmu_t mmu, struct thread *td) 1030 { 1031 pmap_t pm; 1032 1033 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1034 1035 pm = &td->td_proc->p_vmspace->vm_pmap; 1036 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1037 #ifdef __powerpc64__ 1038 PCPU_SET(userslb, NULL); 1039 #else 1040 PCPU_SET(curpmap, NULL); 1041 #endif 1042 } 1043 1044 void 1045 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1046 { 1047 struct pvo_entry key, *pvo; 1048 vm_page_t m; 1049 int64_t refchg; 1050 1051 key.pvo_vaddr = sva; 1052 PMAP_LOCK(pm); 1053 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1054 pvo != NULL && PVO_VADDR(pvo) < eva; 1055 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1056 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1057 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1058 pvo); 1059 pvo->pvo_vaddr &= ~PVO_WIRED; 1060 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */); 1061 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1062 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1063 if (refchg < 0) 1064 refchg = LPTE_CHG; 1065 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1066 1067 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1068 if (refchg & LPTE_CHG) 1069 vm_page_dirty(m); 1070 if (refchg & LPTE_REF) 1071 vm_page_aflag_set(m, PGA_REFERENCED); 1072 } 1073 pm->pm_stats.wired_count--; 1074 } 1075 PMAP_UNLOCK(pm); 1076 } 1077 1078 /* 1079 * This goes through and sets the physical address of our 1080 * special scratch PTE to the PA we want to zero or copy. Because 1081 * of locking issues (this can get called in pvo_enter() by 1082 * the UMA allocator), we can't use most other utility functions here 1083 */ 1084 1085 static __inline 1086 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) { 1087 1088 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1089 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1090 1091 moea64_scratchpage_pvo[which]->pvo_pte.pa = 1092 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1093 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which], 1094 MOEA64_PTE_INVALIDATE); 1095 isync(); 1096 } 1097 1098 void 1099 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst) 1100 { 1101 vm_offset_t dst; 1102 vm_offset_t src; 1103 1104 dst = VM_PAGE_TO_PHYS(mdst); 1105 src = VM_PAGE_TO_PHYS(msrc); 1106 1107 if (hw_direct_map) { 1108 bcopy((void *)src, (void *)dst, PAGE_SIZE); 1109 } else { 1110 mtx_lock(&moea64_scratchpage_mtx); 1111 1112 moea64_set_scratchpage_pa(mmu, 0, src); 1113 moea64_set_scratchpage_pa(mmu, 1, dst); 1114 1115 bcopy((void *)moea64_scratchpage_va[0], 1116 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1117 1118 mtx_unlock(&moea64_scratchpage_mtx); 1119 } 1120 } 1121 1122 static inline void 1123 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1124 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1125 { 1126 void *a_cp, *b_cp; 1127 vm_offset_t a_pg_offset, b_pg_offset; 1128 int cnt; 1129 1130 while (xfersize > 0) { 1131 a_pg_offset = a_offset & PAGE_MASK; 1132 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1133 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) + 1134 a_pg_offset; 1135 b_pg_offset = b_offset & PAGE_MASK; 1136 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1137 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) + 1138 b_pg_offset; 1139 bcopy(a_cp, b_cp, cnt); 1140 a_offset += cnt; 1141 b_offset += cnt; 1142 xfersize -= cnt; 1143 } 1144 } 1145 1146 static inline void 1147 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1148 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1149 { 1150 void *a_cp, *b_cp; 1151 vm_offset_t a_pg_offset, b_pg_offset; 1152 int cnt; 1153 1154 mtx_lock(&moea64_scratchpage_mtx); 1155 while (xfersize > 0) { 1156 a_pg_offset = a_offset & PAGE_MASK; 1157 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1158 moea64_set_scratchpage_pa(mmu, 0, 1159 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1160 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1161 b_pg_offset = b_offset & PAGE_MASK; 1162 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1163 moea64_set_scratchpage_pa(mmu, 1, 1164 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1165 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1166 bcopy(a_cp, b_cp, cnt); 1167 a_offset += cnt; 1168 b_offset += cnt; 1169 xfersize -= cnt; 1170 } 1171 mtx_unlock(&moea64_scratchpage_mtx); 1172 } 1173 1174 void 1175 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 1176 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1177 { 1178 1179 if (hw_direct_map) { 1180 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset, 1181 xfersize); 1182 } else { 1183 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset, 1184 xfersize); 1185 } 1186 } 1187 1188 void 1189 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1190 { 1191 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1192 1193 if (size + off > PAGE_SIZE) 1194 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1195 1196 if (hw_direct_map) { 1197 bzero((caddr_t)pa + off, size); 1198 } else { 1199 mtx_lock(&moea64_scratchpage_mtx); 1200 moea64_set_scratchpage_pa(mmu, 0, pa); 1201 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1202 mtx_unlock(&moea64_scratchpage_mtx); 1203 } 1204 } 1205 1206 /* 1207 * Zero a page of physical memory by temporarily mapping it 1208 */ 1209 void 1210 moea64_zero_page(mmu_t mmu, vm_page_t m) 1211 { 1212 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1213 vm_offset_t va, off; 1214 1215 if (!hw_direct_map) { 1216 mtx_lock(&moea64_scratchpage_mtx); 1217 1218 moea64_set_scratchpage_pa(mmu, 0, pa); 1219 va = moea64_scratchpage_va[0]; 1220 } else { 1221 va = pa; 1222 } 1223 1224 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1225 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1226 1227 if (!hw_direct_map) 1228 mtx_unlock(&moea64_scratchpage_mtx); 1229 } 1230 1231 vm_offset_t 1232 moea64_quick_enter_page(mmu_t mmu, vm_page_t m) 1233 { 1234 struct pvo_entry *pvo; 1235 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1236 1237 if (hw_direct_map) 1238 return (pa); 1239 1240 /* 1241 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1242 * a critical section and access the PCPU data like on i386. 1243 * Instead, pin the thread and grab the PCPU lock to prevent 1244 * a preempting thread from using the same PCPU data. 1245 */ 1246 sched_pin(); 1247 1248 mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED); 1249 pvo = PCPU_GET(qmap_pvo); 1250 1251 mtx_lock(PCPU_PTR(qmap_lock)); 1252 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1253 (uint64_t)pa; 1254 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE); 1255 isync(); 1256 1257 return (PCPU_GET(qmap_addr)); 1258 } 1259 1260 void 1261 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr) 1262 { 1263 if (hw_direct_map) 1264 return; 1265 1266 mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED); 1267 KASSERT(PCPU_GET(qmap_addr) == addr, 1268 ("moea64_quick_remove_page: invalid address")); 1269 mtx_unlock(PCPU_PTR(qmap_lock)); 1270 sched_unpin(); 1271 } 1272 1273 /* 1274 * Map the given physical page at the specified virtual address in the 1275 * target pmap with the protection requested. If specified the page 1276 * will be wired down. 1277 */ 1278 1279 int 1280 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1281 vm_prot_t prot, u_int flags, int8_t psind) 1282 { 1283 struct pvo_entry *pvo, *oldpvo; 1284 struct pvo_head *pvo_head; 1285 uint64_t pte_lo; 1286 int error; 1287 1288 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1289 VM_OBJECT_ASSERT_LOCKED(m->object); 1290 1291 pvo = alloc_pvo_entry(0); 1292 pvo->pvo_pmap = NULL; /* to be filled in later */ 1293 pvo->pvo_pte.prot = prot; 1294 1295 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1296 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1297 1298 if ((flags & PMAP_ENTER_WIRED) != 0) 1299 pvo->pvo_vaddr |= PVO_WIRED; 1300 1301 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1302 pvo_head = NULL; 1303 } else { 1304 pvo_head = &m->md.mdpg_pvoh; 1305 pvo->pvo_vaddr |= PVO_MANAGED; 1306 } 1307 1308 for (;;) { 1309 PV_PAGE_LOCK(m); 1310 PMAP_LOCK(pmap); 1311 if (pvo->pvo_pmap == NULL) 1312 init_pvo_entry(pvo, pmap, va); 1313 if (prot & VM_PROT_WRITE) 1314 if (pmap_bootstrapped && 1315 (m->oflags & VPO_UNMANAGED) == 0) 1316 vm_page_aflag_set(m, PGA_WRITEABLE); 1317 1318 oldpvo = moea64_pvo_find_va(pmap, va); 1319 if (oldpvo != NULL) { 1320 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1321 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1322 oldpvo->pvo_pte.prot == prot) { 1323 /* Identical mapping already exists */ 1324 error = 0; 1325 1326 /* If not in page table, reinsert it */ 1327 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) { 1328 moea64_pte_overflow--; 1329 MOEA64_PTE_INSERT(mmu, oldpvo); 1330 } 1331 1332 /* Then just clean up and go home */ 1333 PV_PAGE_UNLOCK(m); 1334 PMAP_UNLOCK(pmap); 1335 free_pvo_entry(pvo); 1336 break; 1337 } 1338 1339 /* Otherwise, need to kill it first */ 1340 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1341 "mapping does not match new mapping")); 1342 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1343 } 1344 error = moea64_pvo_enter(mmu, pvo, pvo_head); 1345 PV_PAGE_UNLOCK(m); 1346 PMAP_UNLOCK(pmap); 1347 1348 /* Free any dead pages */ 1349 if (oldpvo != NULL) { 1350 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1351 moea64_pvo_remove_from_page(mmu, oldpvo); 1352 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1353 free_pvo_entry(oldpvo); 1354 } 1355 1356 if (error != ENOMEM) 1357 break; 1358 if ((flags & PMAP_ENTER_NOSLEEP) != 0) 1359 return (KERN_RESOURCE_SHORTAGE); 1360 VM_OBJECT_ASSERT_UNLOCKED(m->object); 1361 VM_WAIT; 1362 } 1363 1364 /* 1365 * Flush the page from the instruction cache if this page is 1366 * mapped executable and cacheable. 1367 */ 1368 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) && 1369 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1370 vm_page_aflag_set(m, PGA_EXECUTABLE); 1371 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1372 } 1373 return (KERN_SUCCESS); 1374 } 1375 1376 static void 1377 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1378 vm_size_t sz) 1379 { 1380 1381 /* 1382 * This is much trickier than on older systems because 1383 * we can't sync the icache on physical addresses directly 1384 * without a direct map. Instead we check a couple of cases 1385 * where the memory is already mapped in and, failing that, 1386 * use the same trick we use for page zeroing to create 1387 * a temporary mapping for this physical address. 1388 */ 1389 1390 if (!pmap_bootstrapped) { 1391 /* 1392 * If PMAP is not bootstrapped, we are likely to be 1393 * in real mode. 1394 */ 1395 __syncicache((void *)pa, sz); 1396 } else if (pmap == kernel_pmap) { 1397 __syncicache((void *)va, sz); 1398 } else if (hw_direct_map) { 1399 __syncicache((void *)pa, sz); 1400 } else { 1401 /* Use the scratch page to set up a temp mapping */ 1402 1403 mtx_lock(&moea64_scratchpage_mtx); 1404 1405 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF); 1406 __syncicache((void *)(moea64_scratchpage_va[1] + 1407 (va & ADDR_POFF)), sz); 1408 1409 mtx_unlock(&moea64_scratchpage_mtx); 1410 } 1411 } 1412 1413 /* 1414 * Maps a sequence of resident pages belonging to the same object. 1415 * The sequence begins with the given page m_start. This page is 1416 * mapped at the given virtual address start. Each subsequent page is 1417 * mapped at a virtual address that is offset from start by the same 1418 * amount as the page is offset from m_start within the object. The 1419 * last page in the sequence is the page with the largest offset from 1420 * m_start that can be mapped at a virtual address less than the given 1421 * virtual address end. Not every virtual page between start and end 1422 * is mapped; only those for which a resident page exists with the 1423 * corresponding offset from m_start are mapped. 1424 */ 1425 void 1426 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end, 1427 vm_page_t m_start, vm_prot_t prot) 1428 { 1429 vm_page_t m; 1430 vm_pindex_t diff, psize; 1431 1432 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1433 1434 psize = atop(end - start); 1435 m = m_start; 1436 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1437 moea64_enter(mmu, pm, start + ptoa(diff), m, prot & 1438 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0); 1439 m = TAILQ_NEXT(m, listq); 1440 } 1441 } 1442 1443 void 1444 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m, 1445 vm_prot_t prot) 1446 { 1447 1448 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1449 PMAP_ENTER_NOSLEEP, 0); 1450 } 1451 1452 vm_paddr_t 1453 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va) 1454 { 1455 struct pvo_entry *pvo; 1456 vm_paddr_t pa; 1457 1458 PMAP_LOCK(pm); 1459 pvo = moea64_pvo_find_va(pm, va); 1460 if (pvo == NULL) 1461 pa = 0; 1462 else 1463 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1464 PMAP_UNLOCK(pm); 1465 1466 return (pa); 1467 } 1468 1469 /* 1470 * Atomically extract and hold the physical page with the given 1471 * pmap and virtual address pair if that mapping permits the given 1472 * protection. 1473 */ 1474 vm_page_t 1475 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1476 { 1477 struct pvo_entry *pvo; 1478 vm_page_t m; 1479 vm_paddr_t pa; 1480 1481 m = NULL; 1482 pa = 0; 1483 PMAP_LOCK(pmap); 1484 retry: 1485 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1486 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1487 if (vm_page_pa_tryrelock(pmap, 1488 pvo->pvo_pte.pa & LPTE_RPGN, &pa)) 1489 goto retry; 1490 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 1491 vm_page_hold(m); 1492 } 1493 PA_UNLOCK_COND(pa); 1494 PMAP_UNLOCK(pmap); 1495 return (m); 1496 } 1497 1498 static mmu_t installed_mmu; 1499 1500 static void * 1501 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, 1502 int wait) 1503 { 1504 struct pvo_entry *pvo; 1505 vm_offset_t va; 1506 vm_page_t m; 1507 int pflags, needed_lock; 1508 1509 /* 1510 * This entire routine is a horrible hack to avoid bothering kmem 1511 * for new KVA addresses. Because this can get called from inside 1512 * kmem allocation routines, calling kmem for a new address here 1513 * can lead to multiply locking non-recursive mutexes. 1514 */ 1515 1516 *flags = UMA_SLAB_PRIV; 1517 needed_lock = !PMAP_LOCKED(kernel_pmap); 1518 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED; 1519 1520 for (;;) { 1521 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ); 1522 if (m == NULL) { 1523 if (wait & M_NOWAIT) 1524 return (NULL); 1525 VM_WAIT; 1526 } else 1527 break; 1528 } 1529 1530 va = VM_PAGE_TO_PHYS(m); 1531 1532 pvo = alloc_pvo_entry(1 /* bootstrap */); 1533 1534 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1535 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1536 1537 if (needed_lock) 1538 PMAP_LOCK(kernel_pmap); 1539 1540 init_pvo_entry(pvo, kernel_pmap, va); 1541 pvo->pvo_vaddr |= PVO_WIRED; 1542 1543 moea64_pvo_enter(installed_mmu, pvo, NULL); 1544 1545 if (needed_lock) 1546 PMAP_UNLOCK(kernel_pmap); 1547 1548 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1549 bzero((void *)va, PAGE_SIZE); 1550 1551 return (void *)va; 1552 } 1553 1554 extern int elf32_nxstack; 1555 1556 void 1557 moea64_init(mmu_t mmu) 1558 { 1559 1560 CTR0(KTR_PMAP, "moea64_init"); 1561 1562 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1563 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1564 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1565 1566 if (!hw_direct_map) { 1567 installed_mmu = mmu; 1568 uma_zone_set_allocf(moea64_pvo_zone,moea64_uma_page_alloc); 1569 } 1570 1571 #ifdef COMPAT_FREEBSD32 1572 elf32_nxstack = 1; 1573 #endif 1574 1575 moea64_initialized = TRUE; 1576 } 1577 1578 boolean_t 1579 moea64_is_referenced(mmu_t mmu, vm_page_t m) 1580 { 1581 1582 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1583 ("moea64_is_referenced: page %p is not managed", m)); 1584 1585 return (moea64_query_bit(mmu, m, LPTE_REF)); 1586 } 1587 1588 boolean_t 1589 moea64_is_modified(mmu_t mmu, vm_page_t m) 1590 { 1591 1592 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1593 ("moea64_is_modified: page %p is not managed", m)); 1594 1595 /* 1596 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1597 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 1598 * is clear, no PTEs can have LPTE_CHG set. 1599 */ 1600 VM_OBJECT_ASSERT_LOCKED(m->object); 1601 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1602 return (FALSE); 1603 return (moea64_query_bit(mmu, m, LPTE_CHG)); 1604 } 1605 1606 boolean_t 1607 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1608 { 1609 struct pvo_entry *pvo; 1610 boolean_t rv = TRUE; 1611 1612 PMAP_LOCK(pmap); 1613 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1614 if (pvo != NULL) 1615 rv = FALSE; 1616 PMAP_UNLOCK(pmap); 1617 return (rv); 1618 } 1619 1620 void 1621 moea64_clear_modify(mmu_t mmu, vm_page_t m) 1622 { 1623 1624 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1625 ("moea64_clear_modify: page %p is not managed", m)); 1626 VM_OBJECT_ASSERT_WLOCKED(m->object); 1627 KASSERT(!vm_page_xbusied(m), 1628 ("moea64_clear_modify: page %p is exclusive busied", m)); 1629 1630 /* 1631 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG 1632 * set. If the object containing the page is locked and the page is 1633 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 1634 */ 1635 if ((m->aflags & PGA_WRITEABLE) == 0) 1636 return; 1637 moea64_clear_bit(mmu, m, LPTE_CHG); 1638 } 1639 1640 /* 1641 * Clear the write and modified bits in each of the given page's mappings. 1642 */ 1643 void 1644 moea64_remove_write(mmu_t mmu, vm_page_t m) 1645 { 1646 struct pvo_entry *pvo; 1647 int64_t refchg, ret; 1648 pmap_t pmap; 1649 1650 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1651 ("moea64_remove_write: page %p is not managed", m)); 1652 1653 /* 1654 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1655 * set by another thread while the object is locked. Thus, 1656 * if PGA_WRITEABLE is clear, no page table entries need updating. 1657 */ 1658 VM_OBJECT_ASSERT_WLOCKED(m->object); 1659 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1660 return; 1661 powerpc_sync(); 1662 PV_PAGE_LOCK(m); 1663 refchg = 0; 1664 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1665 pmap = pvo->pvo_pmap; 1666 PMAP_LOCK(pmap); 1667 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1668 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1669 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1670 ret = MOEA64_PTE_REPLACE(mmu, pvo, 1671 MOEA64_PTE_PROT_UPDATE); 1672 if (ret < 0) 1673 ret = LPTE_CHG; 1674 refchg |= ret; 1675 if (pvo->pvo_pmap == kernel_pmap) 1676 isync(); 1677 } 1678 PMAP_UNLOCK(pmap); 1679 } 1680 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1681 vm_page_dirty(m); 1682 vm_page_aflag_clear(m, PGA_WRITEABLE); 1683 PV_PAGE_UNLOCK(m); 1684 } 1685 1686 /* 1687 * moea64_ts_referenced: 1688 * 1689 * Return a count of reference bits for a page, clearing those bits. 1690 * It is not necessary for every reference bit to be cleared, but it 1691 * is necessary that 0 only be returned when there are truly no 1692 * reference bits set. 1693 * 1694 * XXX: The exact number of bits to check and clear is a matter that 1695 * should be tested and standardized at some point in the future for 1696 * optimal aging of shared pages. 1697 */ 1698 int 1699 moea64_ts_referenced(mmu_t mmu, vm_page_t m) 1700 { 1701 1702 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1703 ("moea64_ts_referenced: page %p is not managed", m)); 1704 return (moea64_clear_bit(mmu, m, LPTE_REF)); 1705 } 1706 1707 /* 1708 * Modify the WIMG settings of all mappings for a page. 1709 */ 1710 void 1711 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma) 1712 { 1713 struct pvo_entry *pvo; 1714 int64_t refchg; 1715 pmap_t pmap; 1716 uint64_t lo; 1717 1718 if ((m->oflags & VPO_UNMANAGED) != 0) { 1719 m->md.mdpg_cache_attrs = ma; 1720 return; 1721 } 1722 1723 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1724 1725 PV_PAGE_LOCK(m); 1726 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1727 pmap = pvo->pvo_pmap; 1728 PMAP_LOCK(pmap); 1729 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1730 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1731 pvo->pvo_pte.pa |= lo; 1732 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 1733 MOEA64_PTE_INVALIDATE); 1734 if (refchg < 0) 1735 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1736 LPTE_CHG : 0; 1737 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1738 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1739 refchg |= 1740 atomic_readandclear_32(&m->md.mdpg_attrs); 1741 if (refchg & LPTE_CHG) 1742 vm_page_dirty(m); 1743 if (refchg & LPTE_REF) 1744 vm_page_aflag_set(m, PGA_REFERENCED); 1745 } 1746 if (pvo->pvo_pmap == kernel_pmap) 1747 isync(); 1748 } 1749 PMAP_UNLOCK(pmap); 1750 } 1751 m->md.mdpg_cache_attrs = ma; 1752 PV_PAGE_UNLOCK(m); 1753 } 1754 1755 /* 1756 * Map a wired page into kernel virtual address space. 1757 */ 1758 void 1759 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1760 { 1761 int error; 1762 struct pvo_entry *pvo, *oldpvo; 1763 1764 pvo = alloc_pvo_entry(0); 1765 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1766 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1767 pvo->pvo_vaddr |= PVO_WIRED; 1768 1769 PMAP_LOCK(kernel_pmap); 1770 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1771 if (oldpvo != NULL) 1772 moea64_pvo_remove_from_pmap(mmu, oldpvo); 1773 init_pvo_entry(pvo, kernel_pmap, va); 1774 error = moea64_pvo_enter(mmu, pvo, NULL); 1775 PMAP_UNLOCK(kernel_pmap); 1776 1777 /* Free any dead pages */ 1778 if (oldpvo != NULL) { 1779 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1780 moea64_pvo_remove_from_page(mmu, oldpvo); 1781 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN); 1782 free_pvo_entry(oldpvo); 1783 } 1784 1785 if (error != 0 && error != ENOENT) 1786 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va, 1787 pa, error); 1788 } 1789 1790 void 1791 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1792 { 1793 1794 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1795 } 1796 1797 /* 1798 * Extract the physical page address associated with the given kernel virtual 1799 * address. 1800 */ 1801 vm_paddr_t 1802 moea64_kextract(mmu_t mmu, vm_offset_t va) 1803 { 1804 struct pvo_entry *pvo; 1805 vm_paddr_t pa; 1806 1807 /* 1808 * Shortcut the direct-mapped case when applicable. We never put 1809 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS. 1810 */ 1811 if (va < VM_MIN_KERNEL_ADDRESS) 1812 return (va); 1813 1814 PMAP_LOCK(kernel_pmap); 1815 pvo = moea64_pvo_find_va(kernel_pmap, va); 1816 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1817 va)); 1818 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo)); 1819 PMAP_UNLOCK(kernel_pmap); 1820 return (pa); 1821 } 1822 1823 /* 1824 * Remove a wired page from kernel virtual address space. 1825 */ 1826 void 1827 moea64_kremove(mmu_t mmu, vm_offset_t va) 1828 { 1829 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE); 1830 } 1831 1832 /* 1833 * Map a range of physical addresses into kernel virtual address space. 1834 * 1835 * The value passed in *virt is a suggested virtual address for the mapping. 1836 * Architectures which can support a direct-mapped physical to virtual region 1837 * can return the appropriate address within that region, leaving '*virt' 1838 * unchanged. Other architectures should map the pages starting at '*virt' and 1839 * update '*virt' with the first usable address after the mapped region. 1840 */ 1841 vm_offset_t 1842 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1843 vm_paddr_t pa_end, int prot) 1844 { 1845 vm_offset_t sva, va; 1846 1847 if (hw_direct_map) { 1848 /* 1849 * Check if every page in the region is covered by the direct 1850 * map. The direct map covers all of physical memory. Use 1851 * moea64_calc_wimg() as a shortcut to see if the page is in 1852 * physical memory as a way to see if the direct map covers it. 1853 */ 1854 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 1855 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 1856 break; 1857 if (va == pa_end) 1858 return (pa_start); 1859 } 1860 sva = *virt; 1861 va = sva; 1862 /* XXX respect prot argument */ 1863 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 1864 moea64_kenter(mmu, va, pa_start); 1865 *virt = va; 1866 1867 return (sva); 1868 } 1869 1870 /* 1871 * Returns true if the pmap's pv is one of the first 1872 * 16 pvs linked to from this page. This count may 1873 * be changed upwards or downwards in the future; it 1874 * is only necessary that true be returned for a small 1875 * subset of pmaps for proper page aging. 1876 */ 1877 boolean_t 1878 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 1879 { 1880 int loops; 1881 struct pvo_entry *pvo; 1882 boolean_t rv; 1883 1884 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1885 ("moea64_page_exists_quick: page %p is not managed", m)); 1886 loops = 0; 1887 rv = FALSE; 1888 PV_PAGE_LOCK(m); 1889 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1890 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 1891 rv = TRUE; 1892 break; 1893 } 1894 if (++loops >= 16) 1895 break; 1896 } 1897 PV_PAGE_UNLOCK(m); 1898 return (rv); 1899 } 1900 1901 /* 1902 * Return the number of managed mappings to the given physical page 1903 * that are wired. 1904 */ 1905 int 1906 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m) 1907 { 1908 struct pvo_entry *pvo; 1909 int count; 1910 1911 count = 0; 1912 if ((m->oflags & VPO_UNMANAGED) != 0) 1913 return (count); 1914 PV_PAGE_LOCK(m); 1915 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 1916 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 1917 count++; 1918 PV_PAGE_UNLOCK(m); 1919 return (count); 1920 } 1921 1922 static uintptr_t moea64_vsidcontext; 1923 1924 uintptr_t 1925 moea64_get_unique_vsid(void) { 1926 u_int entropy; 1927 register_t hash; 1928 uint32_t mask; 1929 int i; 1930 1931 entropy = 0; 1932 __asm __volatile("mftb %0" : "=r"(entropy)); 1933 1934 mtx_lock(&moea64_slb_mutex); 1935 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 1936 u_int n; 1937 1938 /* 1939 * Create a new value by mutiplying by a prime and adding in 1940 * entropy from the timebase register. This is to make the 1941 * VSID more random so that the PT hash function collides 1942 * less often. (Note that the prime casues gcc to do shifts 1943 * instead of a multiply.) 1944 */ 1945 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 1946 hash = moea64_vsidcontext & (NVSIDS - 1); 1947 if (hash == 0) /* 0 is special, avoid it */ 1948 continue; 1949 n = hash >> 5; 1950 mask = 1 << (hash & (VSID_NBPW - 1)); 1951 hash = (moea64_vsidcontext & VSID_HASHMASK); 1952 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 1953 /* anything free in this bucket? */ 1954 if (moea64_vsid_bitmap[n] == 0xffffffff) { 1955 entropy = (moea64_vsidcontext >> 20); 1956 continue; 1957 } 1958 i = ffs(~moea64_vsid_bitmap[n]) - 1; 1959 mask = 1 << i; 1960 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 1961 hash |= i; 1962 } 1963 if (hash == VSID_VRMA) /* also special, avoid this too */ 1964 continue; 1965 KASSERT(!(moea64_vsid_bitmap[n] & mask), 1966 ("Allocating in-use VSID %#zx\n", hash)); 1967 moea64_vsid_bitmap[n] |= mask; 1968 mtx_unlock(&moea64_slb_mutex); 1969 return (hash); 1970 } 1971 1972 mtx_unlock(&moea64_slb_mutex); 1973 panic("%s: out of segments",__func__); 1974 } 1975 1976 #ifdef __powerpc64__ 1977 void 1978 moea64_pinit(mmu_t mmu, pmap_t pmap) 1979 { 1980 1981 RB_INIT(&pmap->pmap_pvo); 1982 1983 pmap->pm_slb_tree_root = slb_alloc_tree(); 1984 pmap->pm_slb = slb_alloc_user_cache(); 1985 pmap->pm_slb_len = 0; 1986 } 1987 #else 1988 void 1989 moea64_pinit(mmu_t mmu, pmap_t pmap) 1990 { 1991 int i; 1992 uint32_t hash; 1993 1994 RB_INIT(&pmap->pmap_pvo); 1995 1996 if (pmap_bootstrapped) 1997 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu, 1998 (vm_offset_t)pmap); 1999 else 2000 pmap->pmap_phys = pmap; 2001 2002 /* 2003 * Allocate some segment registers for this pmap. 2004 */ 2005 hash = moea64_get_unique_vsid(); 2006 2007 for (i = 0; i < 16; i++) 2008 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2009 2010 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2011 } 2012 #endif 2013 2014 /* 2015 * Initialize the pmap associated with process 0. 2016 */ 2017 void 2018 moea64_pinit0(mmu_t mmu, pmap_t pm) 2019 { 2020 2021 PMAP_LOCK_INIT(pm); 2022 moea64_pinit(mmu, pm); 2023 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2024 } 2025 2026 /* 2027 * Set the physical protection on the specified range of this map as requested. 2028 */ 2029 static void 2030 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2031 { 2032 struct vm_page *pg; 2033 vm_prot_t oldprot; 2034 int32_t refchg; 2035 2036 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2037 2038 /* 2039 * Change the protection of the page. 2040 */ 2041 oldprot = pvo->pvo_pte.prot; 2042 pvo->pvo_pte.prot = prot; 2043 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2044 2045 /* 2046 * If the PVO is in the page table, update mapping 2047 */ 2048 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE); 2049 if (refchg < 0) 2050 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2051 2052 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) && 2053 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2054 if ((pg->oflags & VPO_UNMANAGED) == 0) 2055 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2056 moea64_syncicache(mmu, pm, PVO_VADDR(pvo), 2057 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE); 2058 } 2059 2060 /* 2061 * Update vm about the REF/CHG bits if the page is managed and we have 2062 * removed write access. 2063 */ 2064 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2065 (oldprot & VM_PROT_WRITE)) { 2066 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2067 if (refchg & LPTE_CHG) 2068 vm_page_dirty(pg); 2069 if (refchg & LPTE_REF) 2070 vm_page_aflag_set(pg, PGA_REFERENCED); 2071 } 2072 } 2073 2074 void 2075 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2076 vm_prot_t prot) 2077 { 2078 struct pvo_entry *pvo, *tpvo, key; 2079 2080 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2081 sva, eva, prot); 2082 2083 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2084 ("moea64_protect: non current pmap")); 2085 2086 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2087 moea64_remove(mmu, pm, sva, eva); 2088 return; 2089 } 2090 2091 PMAP_LOCK(pm); 2092 key.pvo_vaddr = sva; 2093 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2094 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2095 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2096 moea64_pvo_protect(mmu, pm, pvo, prot); 2097 } 2098 PMAP_UNLOCK(pm); 2099 } 2100 2101 /* 2102 * Map a list of wired pages into kernel virtual address space. This is 2103 * intended for temporary mappings which do not need page modification or 2104 * references recorded. Existing mappings in the region are overwritten. 2105 */ 2106 void 2107 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count) 2108 { 2109 while (count-- > 0) { 2110 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 2111 va += PAGE_SIZE; 2112 m++; 2113 } 2114 } 2115 2116 /* 2117 * Remove page mappings from kernel virtual address space. Intended for 2118 * temporary mappings entered by moea64_qenter. 2119 */ 2120 void 2121 moea64_qremove(mmu_t mmu, vm_offset_t va, int count) 2122 { 2123 while (count-- > 0) { 2124 moea64_kremove(mmu, va); 2125 va += PAGE_SIZE; 2126 } 2127 } 2128 2129 void 2130 moea64_release_vsid(uint64_t vsid) 2131 { 2132 int idx, mask; 2133 2134 mtx_lock(&moea64_slb_mutex); 2135 idx = vsid & (NVSIDS-1); 2136 mask = 1 << (idx % VSID_NBPW); 2137 idx /= VSID_NBPW; 2138 KASSERT(moea64_vsid_bitmap[idx] & mask, 2139 ("Freeing unallocated VSID %#jx", vsid)); 2140 moea64_vsid_bitmap[idx] &= ~mask; 2141 mtx_unlock(&moea64_slb_mutex); 2142 } 2143 2144 2145 void 2146 moea64_release(mmu_t mmu, pmap_t pmap) 2147 { 2148 2149 /* 2150 * Free segment registers' VSIDs 2151 */ 2152 #ifdef __powerpc64__ 2153 slb_free_tree(pmap); 2154 slb_free_user_cache(pmap->pm_slb); 2155 #else 2156 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2157 2158 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2159 #endif 2160 } 2161 2162 /* 2163 * Remove all pages mapped by the specified pmap 2164 */ 2165 void 2166 moea64_remove_pages(mmu_t mmu, pmap_t pm) 2167 { 2168 struct pvo_entry *pvo, *tpvo; 2169 struct pvo_tree tofree; 2170 2171 RB_INIT(&tofree); 2172 2173 PMAP_LOCK(pm); 2174 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2175 if (pvo->pvo_vaddr & PVO_WIRED) 2176 continue; 2177 2178 /* 2179 * For locking reasons, remove this from the page table and 2180 * pmap, but save delinking from the vm_page for a second 2181 * pass 2182 */ 2183 moea64_pvo_remove_from_pmap(mmu, pvo); 2184 RB_INSERT(pvo_tree, &tofree, pvo); 2185 } 2186 PMAP_UNLOCK(pm); 2187 2188 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2189 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2190 moea64_pvo_remove_from_page(mmu, pvo); 2191 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2192 RB_REMOVE(pvo_tree, &tofree, pvo); 2193 free_pvo_entry(pvo); 2194 } 2195 } 2196 2197 /* 2198 * Remove the given range of addresses from the specified map. 2199 */ 2200 void 2201 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2202 { 2203 struct pvo_entry *pvo, *tpvo, key; 2204 struct pvo_tree tofree; 2205 2206 /* 2207 * Perform an unsynchronized read. This is, however, safe. 2208 */ 2209 if (pm->pm_stats.resident_count == 0) 2210 return; 2211 2212 key.pvo_vaddr = sva; 2213 2214 RB_INIT(&tofree); 2215 2216 PMAP_LOCK(pm); 2217 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2218 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2219 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2220 2221 /* 2222 * For locking reasons, remove this from the page table and 2223 * pmap, but save delinking from the vm_page for a second 2224 * pass 2225 */ 2226 moea64_pvo_remove_from_pmap(mmu, pvo); 2227 RB_INSERT(pvo_tree, &tofree, pvo); 2228 } 2229 PMAP_UNLOCK(pm); 2230 2231 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) { 2232 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2233 moea64_pvo_remove_from_page(mmu, pvo); 2234 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN); 2235 RB_REMOVE(pvo_tree, &tofree, pvo); 2236 free_pvo_entry(pvo); 2237 } 2238 } 2239 2240 /* 2241 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2242 * will reflect changes in pte's back to the vm_page. 2243 */ 2244 void 2245 moea64_remove_all(mmu_t mmu, vm_page_t m) 2246 { 2247 struct pvo_entry *pvo, *next_pvo; 2248 struct pvo_head freequeue; 2249 int wasdead; 2250 pmap_t pmap; 2251 2252 LIST_INIT(&freequeue); 2253 2254 PV_PAGE_LOCK(m); 2255 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2256 pmap = pvo->pvo_pmap; 2257 PMAP_LOCK(pmap); 2258 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2259 if (!wasdead) 2260 moea64_pvo_remove_from_pmap(mmu, pvo); 2261 moea64_pvo_remove_from_page(mmu, pvo); 2262 if (!wasdead) 2263 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2264 PMAP_UNLOCK(pmap); 2265 2266 } 2267 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2268 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable")); 2269 PV_PAGE_UNLOCK(m); 2270 2271 /* Clean up UMA allocations */ 2272 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2273 free_pvo_entry(pvo); 2274 } 2275 2276 /* 2277 * Allocate a physical page of memory directly from the phys_avail map. 2278 * Can only be called from moea64_bootstrap before avail start and end are 2279 * calculated. 2280 */ 2281 vm_offset_t 2282 moea64_bootstrap_alloc(vm_size_t size, u_int align) 2283 { 2284 vm_offset_t s, e; 2285 int i, j; 2286 2287 size = round_page(size); 2288 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2289 if (align != 0) 2290 s = roundup2(phys_avail[i], align); 2291 else 2292 s = phys_avail[i]; 2293 e = s + size; 2294 2295 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2296 continue; 2297 2298 if (s + size > platform_real_maxaddr()) 2299 continue; 2300 2301 if (s == phys_avail[i]) { 2302 phys_avail[i] += size; 2303 } else if (e == phys_avail[i + 1]) { 2304 phys_avail[i + 1] -= size; 2305 } else { 2306 for (j = phys_avail_count * 2; j > i; j -= 2) { 2307 phys_avail[j] = phys_avail[j - 2]; 2308 phys_avail[j + 1] = phys_avail[j - 1]; 2309 } 2310 2311 phys_avail[i + 3] = phys_avail[i + 1]; 2312 phys_avail[i + 1] = s; 2313 phys_avail[i + 2] = e; 2314 phys_avail_count++; 2315 } 2316 2317 return (s); 2318 } 2319 panic("moea64_bootstrap_alloc: could not allocate memory"); 2320 } 2321 2322 static int 2323 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head) 2324 { 2325 int first, err; 2326 2327 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2328 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL, 2329 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo))); 2330 2331 moea64_pvo_enter_calls++; 2332 2333 /* 2334 * Add to pmap list 2335 */ 2336 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2337 2338 /* 2339 * Remember if the list was empty and therefore will be the first 2340 * item. 2341 */ 2342 if (pvo_head != NULL) { 2343 if (LIST_FIRST(pvo_head) == NULL) 2344 first = 1; 2345 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2346 } 2347 2348 if (pvo->pvo_vaddr & PVO_WIRED) 2349 pvo->pvo_pmap->pm_stats.wired_count++; 2350 pvo->pvo_pmap->pm_stats.resident_count++; 2351 2352 /* 2353 * Insert it into the hardware page table 2354 */ 2355 err = MOEA64_PTE_INSERT(mmu, pvo); 2356 if (err != 0) { 2357 panic("moea64_pvo_enter: overflow"); 2358 } 2359 2360 moea64_pvo_entries++; 2361 2362 if (pvo->pvo_pmap == kernel_pmap) 2363 isync(); 2364 2365 #ifdef __powerpc64__ 2366 /* 2367 * Make sure all our bootstrap mappings are in the SLB as soon 2368 * as virtual memory is switched on. 2369 */ 2370 if (!pmap_bootstrapped) 2371 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2372 pvo->pvo_vaddr & PVO_LARGE); 2373 #endif 2374 2375 return (first ? ENOENT : 0); 2376 } 2377 2378 static void 2379 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo) 2380 { 2381 struct vm_page *pg; 2382 int32_t refchg; 2383 2384 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2385 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2386 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2387 2388 /* 2389 * If there is an active pte entry, we need to deactivate it 2390 */ 2391 refchg = MOEA64_PTE_UNSET(mmu, pvo); 2392 if (refchg < 0) { 2393 /* 2394 * If it was evicted from the page table, be pessimistic and 2395 * dirty the page. 2396 */ 2397 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2398 refchg = LPTE_CHG; 2399 else 2400 refchg = 0; 2401 } 2402 2403 /* 2404 * Update our statistics. 2405 */ 2406 pvo->pvo_pmap->pm_stats.resident_count--; 2407 if (pvo->pvo_vaddr & PVO_WIRED) 2408 pvo->pvo_pmap->pm_stats.wired_count--; 2409 2410 /* 2411 * Remove this PVO from the pmap list. 2412 */ 2413 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2414 2415 /* 2416 * Mark this for the next sweep 2417 */ 2418 pvo->pvo_vaddr |= PVO_DEAD; 2419 2420 /* Send RC bits to VM */ 2421 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2422 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2423 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2424 if (pg != NULL) { 2425 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2426 if (refchg & LPTE_CHG) 2427 vm_page_dirty(pg); 2428 if (refchg & LPTE_REF) 2429 vm_page_aflag_set(pg, PGA_REFERENCED); 2430 } 2431 } 2432 } 2433 2434 static void 2435 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo) 2436 { 2437 struct vm_page *pg; 2438 2439 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2440 2441 /* Use NULL pmaps as a sentinel for races in page deletion */ 2442 if (pvo->pvo_pmap == NULL) 2443 return; 2444 pvo->pvo_pmap = NULL; 2445 2446 /* 2447 * Update vm about page writeability/executability if managed 2448 */ 2449 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN); 2450 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN); 2451 2452 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) { 2453 LIST_REMOVE(pvo, pvo_vlink); 2454 if (LIST_EMPTY(vm_page_to_pvoh(pg))) 2455 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE); 2456 } 2457 2458 moea64_pvo_entries--; 2459 moea64_pvo_remove_calls++; 2460 } 2461 2462 static struct pvo_entry * 2463 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2464 { 2465 struct pvo_entry key; 2466 2467 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2468 2469 key.pvo_vaddr = va & ~ADDR_POFF; 2470 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2471 } 2472 2473 static boolean_t 2474 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit) 2475 { 2476 struct pvo_entry *pvo; 2477 int64_t ret; 2478 boolean_t rv; 2479 2480 /* 2481 * See if this bit is stored in the page already. 2482 */ 2483 if (m->md.mdpg_attrs & ptebit) 2484 return (TRUE); 2485 2486 /* 2487 * Examine each PTE. Sync so that any pending REF/CHG bits are 2488 * flushed to the PTEs. 2489 */ 2490 rv = FALSE; 2491 powerpc_sync(); 2492 PV_PAGE_LOCK(m); 2493 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2494 ret = 0; 2495 2496 /* 2497 * See if this pvo has a valid PTE. if so, fetch the 2498 * REF/CHG bits from the valid PTE. If the appropriate 2499 * ptebit is set, return success. 2500 */ 2501 PMAP_LOCK(pvo->pvo_pmap); 2502 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2503 ret = MOEA64_PTE_SYNCH(mmu, pvo); 2504 PMAP_UNLOCK(pvo->pvo_pmap); 2505 2506 if (ret > 0) { 2507 atomic_set_32(&m->md.mdpg_attrs, 2508 ret & (LPTE_CHG | LPTE_REF)); 2509 if (ret & ptebit) { 2510 rv = TRUE; 2511 break; 2512 } 2513 } 2514 } 2515 PV_PAGE_UNLOCK(m); 2516 2517 return (rv); 2518 } 2519 2520 static u_int 2521 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit) 2522 { 2523 u_int count; 2524 struct pvo_entry *pvo; 2525 int64_t ret; 2526 2527 /* 2528 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2529 * we can reset the right ones). 2530 */ 2531 powerpc_sync(); 2532 2533 /* 2534 * For each pvo entry, clear the pte's ptebit. 2535 */ 2536 count = 0; 2537 PV_PAGE_LOCK(m); 2538 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2539 ret = 0; 2540 2541 PMAP_LOCK(pvo->pvo_pmap); 2542 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2543 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit); 2544 PMAP_UNLOCK(pvo->pvo_pmap); 2545 2546 if (ret > 0 && (ret & ptebit)) 2547 count++; 2548 } 2549 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2550 PV_PAGE_UNLOCK(m); 2551 2552 return (count); 2553 } 2554 2555 boolean_t 2556 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2557 { 2558 struct pvo_entry *pvo, key; 2559 vm_offset_t ppa; 2560 int error = 0; 2561 2562 PMAP_LOCK(kernel_pmap); 2563 key.pvo_vaddr = ppa = pa & ~ADDR_POFF; 2564 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2565 ppa < pa + size; ppa += PAGE_SIZE, 2566 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2567 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) { 2568 error = EFAULT; 2569 break; 2570 } 2571 } 2572 PMAP_UNLOCK(kernel_pmap); 2573 2574 return (error); 2575 } 2576 2577 /* 2578 * Map a set of physical memory pages into the kernel virtual 2579 * address space. Return a pointer to where it is mapped. This 2580 * routine is intended to be used for mapping device memory, 2581 * NOT real memory. 2582 */ 2583 void * 2584 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2585 { 2586 vm_offset_t va, tmpva, ppa, offset; 2587 2588 ppa = trunc_page(pa); 2589 offset = pa & PAGE_MASK; 2590 size = roundup2(offset + size, PAGE_SIZE); 2591 2592 va = kva_alloc(size); 2593 2594 if (!va) 2595 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2596 2597 for (tmpva = va; size > 0;) { 2598 moea64_kenter_attr(mmu, tmpva, ppa, ma); 2599 size -= PAGE_SIZE; 2600 tmpva += PAGE_SIZE; 2601 ppa += PAGE_SIZE; 2602 } 2603 2604 return ((void *)(va + offset)); 2605 } 2606 2607 void * 2608 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2609 { 2610 2611 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT); 2612 } 2613 2614 void 2615 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2616 { 2617 vm_offset_t base, offset; 2618 2619 base = trunc_page(va); 2620 offset = va & PAGE_MASK; 2621 size = roundup2(offset + size, PAGE_SIZE); 2622 2623 kva_free(base, size); 2624 } 2625 2626 void 2627 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2628 { 2629 struct pvo_entry *pvo; 2630 vm_offset_t lim; 2631 vm_paddr_t pa; 2632 vm_size_t len; 2633 2634 PMAP_LOCK(pm); 2635 while (sz > 0) { 2636 lim = round_page(va); 2637 len = MIN(lim - va, sz); 2638 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2639 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2640 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF); 2641 moea64_syncicache(mmu, pm, va, pa, len); 2642 } 2643 va += len; 2644 sz -= len; 2645 } 2646 PMAP_UNLOCK(pm); 2647 } 2648 2649 void 2650 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2651 { 2652 2653 *va = (void *)pa; 2654 } 2655 2656 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2657 2658 void 2659 moea64_scan_init(mmu_t mmu) 2660 { 2661 struct pvo_entry *pvo; 2662 vm_offset_t va; 2663 int i; 2664 2665 if (!do_minidump) { 2666 /* Initialize phys. segments for dumpsys(). */ 2667 memset(&dump_map, 0, sizeof(dump_map)); 2668 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2669 for (i = 0; i < pregions_sz; i++) { 2670 dump_map[i].pa_start = pregions[i].mr_start; 2671 dump_map[i].pa_size = pregions[i].mr_size; 2672 } 2673 return; 2674 } 2675 2676 /* Virtual segments for minidumps: */ 2677 memset(&dump_map, 0, sizeof(dump_map)); 2678 2679 /* 1st: kernel .data and .bss. */ 2680 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2681 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2682 dump_map[0].pa_start; 2683 2684 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2685 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr; 2686 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2687 2688 /* 3rd: kernel VM. */ 2689 va = dump_map[1].pa_start + dump_map[1].pa_size; 2690 /* Find start of next chunk (from va). */ 2691 while (va < virtual_end) { 2692 /* Don't dump the buffer cache. */ 2693 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2694 va = kmi.buffer_eva; 2695 continue; 2696 } 2697 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2698 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2699 break; 2700 va += PAGE_SIZE; 2701 } 2702 if (va < virtual_end) { 2703 dump_map[2].pa_start = va; 2704 va += PAGE_SIZE; 2705 /* Find last page in chunk. */ 2706 while (va < virtual_end) { 2707 /* Don't run into the buffer cache. */ 2708 if (va == kmi.buffer_sva) 2709 break; 2710 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2711 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2712 break; 2713 va += PAGE_SIZE; 2714 } 2715 dump_map[2].pa_size = va - dump_map[2].pa_start; 2716 } 2717 } 2718 2719