1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008-2015 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * Manages physical address maps. 34 * 35 * Since the information managed by this module is also stored by the 36 * logical address mapping module, this module may throw away valid virtual 37 * to physical mappings at almost any time. However, invalidations of 38 * mappings must be done as requested. 39 * 40 * In order to cope with hardware architectures which make virtual to 41 * physical map invalidates expensive, this module may delay invalidate 42 * reduced protection operations until such time as they are actually 43 * necessary. This module is given full information as to which processors 44 * are currently using which maps, and to when physical maps must be made 45 * correct. 46 */ 47 48 #include "opt_kstack_pages.h" 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/conf.h> 53 #include <sys/queue.h> 54 #include <sys/cpuset.h> 55 #include <sys/kerneldump.h> 56 #include <sys/ktr.h> 57 #include <sys/lock.h> 58 #include <sys/msgbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/mutex.h> 61 #include <sys/proc.h> 62 #include <sys/rwlock.h> 63 #include <sys/sched.h> 64 #include <sys/sysctl.h> 65 #include <sys/systm.h> 66 #include <sys/vmmeter.h> 67 #include <sys/smp.h> 68 #include <sys/reboot.h> 69 70 #include <sys/kdb.h> 71 72 #include <dev/ofw/openfirm.h> 73 74 #include <vm/vm.h> 75 #include <vm/vm_param.h> 76 #include <vm/vm_kern.h> 77 #include <vm/vm_page.h> 78 #include <vm/vm_phys.h> 79 #include <vm/vm_map.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_extern.h> 82 #include <vm/vm_pageout.h> 83 #include <vm/uma.h> 84 85 #include <machine/_inttypes.h> 86 #include <machine/cpu.h> 87 #include <machine/ifunc.h> 88 #include <machine/platform.h> 89 #include <machine/frame.h> 90 #include <machine/md_var.h> 91 #include <machine/psl.h> 92 #include <machine/bat.h> 93 #include <machine/hid.h> 94 #include <machine/pte.h> 95 #include <machine/sr.h> 96 #include <machine/trap.h> 97 #include <machine/mmuvar.h> 98 99 #include "mmu_oea64.h" 100 101 void moea64_release_vsid(uint64_t vsid); 102 uintptr_t moea64_get_unique_vsid(void); 103 104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR) 105 #define ENABLE_TRANS(msr) mtmsr(msr) 106 107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4)) 108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff) 109 #define VSID_HASH_MASK 0x0000007fffffffffULL 110 111 /* Get physical address from PVO. */ 112 #define PVO_PADDR(pvo) ((pvo)->pvo_pte.pa & LPTE_RPGN) 113 114 /* 115 * Locking semantics: 116 * 117 * There are two locks of interest: the page locks and the pmap locks, which 118 * protect their individual PVO lists and are locked in that order. The contents 119 * of all PVO entries are protected by the locks of their respective pmaps. 120 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked 121 * into any list. 122 * 123 */ 124 125 #define PV_LOCK_COUNT PA_LOCK_COUNT 126 static struct mtx_padalign pv_lock[PV_LOCK_COUNT]; 127 128 /* 129 * Cheap NUMA-izing of the pv locks, to reduce contention across domains. 130 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the 131 * index at (N << 45). 132 */ 133 #ifdef __powerpc64__ 134 #define PV_LOCK_IDX(pa) ((pa_index(pa) * (((pa) >> 45) + 1)) % PV_LOCK_COUNT) 135 #else 136 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT) 137 #endif 138 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)])) 139 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa)) 140 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa)) 141 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED) 142 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m)) 143 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m)) 144 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m)) 145 146 struct ofw_map { 147 cell_t om_va; 148 cell_t om_len; 149 uint64_t om_pa; 150 cell_t om_mode; 151 }; 152 153 extern unsigned char _etext[]; 154 extern unsigned char _end[]; 155 156 extern void *slbtrap, *slbtrapend; 157 158 /* 159 * Map of physical memory regions. 160 */ 161 static struct mem_region *regions; 162 static struct mem_region *pregions; 163 static struct numa_mem_region *numa_pregions; 164 static u_int phys_avail_count; 165 static int regions_sz, pregions_sz, numapregions_sz; 166 167 extern void bs_remap_earlyboot(void); 168 169 /* 170 * Lock for the SLB tables. 171 */ 172 struct mtx moea64_slb_mutex; 173 174 /* 175 * PTEG data. 176 */ 177 u_long moea64_pteg_count; 178 u_long moea64_pteg_mask; 179 180 /* 181 * PVO data. 182 */ 183 184 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */ 185 186 static struct pvo_entry *moea64_bpvo_pool; 187 static int moea64_bpvo_pool_index = 0; 188 static int moea64_bpvo_pool_size = 0; 189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD, 190 &moea64_bpvo_pool_index, 0, ""); 191 192 #define BPVO_POOL_SIZE 327680 /* Sensible historical default value */ 193 #define BPVO_POOL_EXPANSION_FACTOR 3 194 #define VSID_NBPW (sizeof(u_int32_t) * 8) 195 #ifdef __powerpc64__ 196 #define NVSIDS (NPMAPS * 16) 197 #define VSID_HASHMASK 0xffffffffUL 198 #else 199 #define NVSIDS NPMAPS 200 #define VSID_HASHMASK 0xfffffUL 201 #endif 202 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW]; 203 204 static boolean_t moea64_initialized = FALSE; 205 206 #ifdef MOEA64_STATS 207 /* 208 * Statistics. 209 */ 210 u_int moea64_pte_valid = 0; 211 u_int moea64_pte_overflow = 0; 212 u_int moea64_pvo_entries = 0; 213 u_int moea64_pvo_enter_calls = 0; 214 u_int moea64_pvo_remove_calls = 0; 215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD, 216 &moea64_pte_valid, 0, ""); 217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD, 218 &moea64_pte_overflow, 0, ""); 219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD, 220 &moea64_pvo_entries, 0, ""); 221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD, 222 &moea64_pvo_enter_calls, 0, ""); 223 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD, 224 &moea64_pvo_remove_calls, 0, ""); 225 #endif 226 227 vm_offset_t moea64_scratchpage_va[2]; 228 struct pvo_entry *moea64_scratchpage_pvo[2]; 229 struct mtx moea64_scratchpage_mtx; 230 231 uint64_t moea64_large_page_mask = 0; 232 uint64_t moea64_large_page_size = 0; 233 int moea64_large_page_shift = 0; 234 235 /* 236 * PVO calls. 237 */ 238 static int moea64_pvo_enter(struct pvo_entry *pvo, 239 struct pvo_head *pvo_head, struct pvo_entry **oldpvo); 240 static void moea64_pvo_remove_from_pmap(struct pvo_entry *pvo); 241 static void moea64_pvo_remove_from_page(struct pvo_entry *pvo); 242 static void moea64_pvo_remove_from_page_locked( 243 struct pvo_entry *pvo, vm_page_t m); 244 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t); 245 246 /* 247 * Utility routines. 248 */ 249 static boolean_t moea64_query_bit(vm_page_t, uint64_t); 250 static u_int moea64_clear_bit(vm_page_t, uint64_t); 251 static void moea64_kremove(vm_offset_t); 252 static void moea64_syncicache(pmap_t pmap, vm_offset_t va, 253 vm_paddr_t pa, vm_size_t sz); 254 static void moea64_pmap_init_qpages(void); 255 256 /* 257 * Kernel MMU interface 258 */ 259 void moea64_clear_modify(vm_page_t); 260 void moea64_copy_page(vm_page_t, vm_page_t); 261 void moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 262 vm_page_t *mb, vm_offset_t b_offset, int xfersize); 263 int moea64_enter(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, 264 u_int flags, int8_t psind); 265 void moea64_enter_object(pmap_t, vm_offset_t, vm_offset_t, vm_page_t, 266 vm_prot_t); 267 void moea64_enter_quick(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); 268 vm_paddr_t moea64_extract(pmap_t, vm_offset_t); 269 vm_page_t moea64_extract_and_hold(pmap_t, vm_offset_t, vm_prot_t); 270 void moea64_init(void); 271 boolean_t moea64_is_modified(vm_page_t); 272 boolean_t moea64_is_prefaultable(pmap_t, vm_offset_t); 273 boolean_t moea64_is_referenced(vm_page_t); 274 int moea64_ts_referenced(vm_page_t); 275 vm_offset_t moea64_map(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); 276 boolean_t moea64_page_exists_quick(pmap_t, vm_page_t); 277 void moea64_page_init(vm_page_t); 278 int moea64_page_wired_mappings(vm_page_t); 279 int moea64_pinit(pmap_t); 280 void moea64_pinit0(pmap_t); 281 void moea64_protect(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); 282 void moea64_qenter(vm_offset_t, vm_page_t *, int); 283 void moea64_qremove(vm_offset_t, int); 284 void moea64_release(pmap_t); 285 void moea64_remove(pmap_t, vm_offset_t, vm_offset_t); 286 void moea64_remove_pages(pmap_t); 287 void moea64_remove_all(vm_page_t); 288 void moea64_remove_write(vm_page_t); 289 void moea64_unwire(pmap_t, vm_offset_t, vm_offset_t); 290 void moea64_zero_page(vm_page_t); 291 void moea64_zero_page_area(vm_page_t, int, int); 292 void moea64_activate(struct thread *); 293 void moea64_deactivate(struct thread *); 294 void *moea64_mapdev(vm_paddr_t, vm_size_t); 295 void *moea64_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); 296 void moea64_unmapdev(vm_offset_t, vm_size_t); 297 vm_paddr_t moea64_kextract(vm_offset_t); 298 void moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma); 299 void moea64_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t ma); 300 void moea64_kenter(vm_offset_t, vm_paddr_t); 301 boolean_t moea64_dev_direct_mapped(vm_paddr_t, vm_size_t); 302 static void moea64_sync_icache(pmap_t, vm_offset_t, vm_size_t); 303 void moea64_dumpsys_map(vm_paddr_t pa, size_t sz, 304 void **va); 305 void moea64_scan_init(void); 306 vm_offset_t moea64_quick_enter_page(vm_page_t m); 307 void moea64_quick_remove_page(vm_offset_t addr); 308 boolean_t moea64_page_is_mapped(vm_page_t m); 309 static int moea64_map_user_ptr(pmap_t pm, 310 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen); 311 static int moea64_decode_kernel_ptr(vm_offset_t addr, 312 int *is_user, vm_offset_t *decoded_addr); 313 static size_t moea64_scan_pmap(void); 314 static void *moea64_dump_pmap_init(unsigned blkpgs); 315 #ifdef __powerpc64__ 316 static void moea64_page_array_startup(long); 317 #endif 318 319 320 static struct pmap_funcs moea64_methods = { 321 .clear_modify = moea64_clear_modify, 322 .copy_page = moea64_copy_page, 323 .copy_pages = moea64_copy_pages, 324 .enter = moea64_enter, 325 .enter_object = moea64_enter_object, 326 .enter_quick = moea64_enter_quick, 327 .extract = moea64_extract, 328 .extract_and_hold = moea64_extract_and_hold, 329 .init = moea64_init, 330 .is_modified = moea64_is_modified, 331 .is_prefaultable = moea64_is_prefaultable, 332 .is_referenced = moea64_is_referenced, 333 .ts_referenced = moea64_ts_referenced, 334 .map = moea64_map, 335 .page_exists_quick = moea64_page_exists_quick, 336 .page_init = moea64_page_init, 337 .page_wired_mappings = moea64_page_wired_mappings, 338 .pinit = moea64_pinit, 339 .pinit0 = moea64_pinit0, 340 .protect = moea64_protect, 341 .qenter = moea64_qenter, 342 .qremove = moea64_qremove, 343 .release = moea64_release, 344 .remove = moea64_remove, 345 .remove_pages = moea64_remove_pages, 346 .remove_all = moea64_remove_all, 347 .remove_write = moea64_remove_write, 348 .sync_icache = moea64_sync_icache, 349 .unwire = moea64_unwire, 350 .zero_page = moea64_zero_page, 351 .zero_page_area = moea64_zero_page_area, 352 .activate = moea64_activate, 353 .deactivate = moea64_deactivate, 354 .page_set_memattr = moea64_page_set_memattr, 355 .quick_enter_page = moea64_quick_enter_page, 356 .quick_remove_page = moea64_quick_remove_page, 357 .page_is_mapped = moea64_page_is_mapped, 358 #ifdef __powerpc64__ 359 .page_array_startup = moea64_page_array_startup, 360 #endif 361 362 /* Internal interfaces */ 363 .mapdev = moea64_mapdev, 364 .mapdev_attr = moea64_mapdev_attr, 365 .unmapdev = moea64_unmapdev, 366 .kextract = moea64_kextract, 367 .kenter = moea64_kenter, 368 .kenter_attr = moea64_kenter_attr, 369 .dev_direct_mapped = moea64_dev_direct_mapped, 370 .dumpsys_pa_init = moea64_scan_init, 371 .dumpsys_scan_pmap = moea64_scan_pmap, 372 .dumpsys_dump_pmap_init = moea64_dump_pmap_init, 373 .dumpsys_map_chunk = moea64_dumpsys_map, 374 .map_user_ptr = moea64_map_user_ptr, 375 .decode_kernel_ptr = moea64_decode_kernel_ptr, 376 }; 377 378 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods); 379 380 static struct pvo_head * 381 vm_page_to_pvoh(vm_page_t m) 382 { 383 384 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED); 385 return (&m->md.mdpg_pvoh); 386 } 387 388 static struct pvo_entry * 389 alloc_pvo_entry(int bootstrap) 390 { 391 struct pvo_entry *pvo; 392 393 if (!moea64_initialized || bootstrap) { 394 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) { 395 panic("%s: bpvo pool exhausted, index=%d, size=%d, bytes=%zd." 396 "Try setting machdep.moea64_bpvo_pool_size tunable", 397 __func__, moea64_bpvo_pool_index, 398 moea64_bpvo_pool_size, 399 moea64_bpvo_pool_size * sizeof(struct pvo_entry)); 400 } 401 pvo = &moea64_bpvo_pool[ 402 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)]; 403 bzero(pvo, sizeof(*pvo)); 404 pvo->pvo_vaddr = PVO_BOOTSTRAP; 405 } else 406 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO); 407 408 return (pvo); 409 } 410 411 412 static void 413 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va) 414 { 415 uint64_t vsid; 416 uint64_t hash; 417 int shift; 418 419 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 420 421 pvo->pvo_pmap = pmap; 422 va &= ~ADDR_POFF; 423 pvo->pvo_vaddr |= va; 424 vsid = va_to_vsid(pmap, va); 425 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT) 426 | (vsid << 16); 427 428 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift : 429 ADDR_PIDX_SHFT; 430 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift); 431 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3; 432 } 433 434 static void 435 free_pvo_entry(struct pvo_entry *pvo) 436 { 437 438 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP)) 439 uma_zfree(moea64_pvo_zone, pvo); 440 } 441 442 void 443 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte) 444 { 445 446 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo); 447 lpte->pte_hi |= LPTE_VALID; 448 449 if (pvo->pvo_vaddr & PVO_LARGE) 450 lpte->pte_hi |= LPTE_BIG; 451 if (pvo->pvo_vaddr & PVO_WIRED) 452 lpte->pte_hi |= LPTE_WIRED; 453 if (pvo->pvo_vaddr & PVO_HID) 454 lpte->pte_hi |= LPTE_HID; 455 456 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */ 457 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 458 lpte->pte_lo |= LPTE_BW; 459 else 460 lpte->pte_lo |= LPTE_BR; 461 462 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE)) 463 lpte->pte_lo |= LPTE_NOEXEC; 464 } 465 466 static __inline uint64_t 467 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 468 { 469 uint64_t pte_lo; 470 int i; 471 472 if (ma != VM_MEMATTR_DEFAULT) { 473 switch (ma) { 474 case VM_MEMATTR_UNCACHEABLE: 475 return (LPTE_I | LPTE_G); 476 case VM_MEMATTR_CACHEABLE: 477 return (LPTE_M); 478 case VM_MEMATTR_WRITE_COMBINING: 479 case VM_MEMATTR_WRITE_BACK: 480 case VM_MEMATTR_PREFETCHABLE: 481 return (LPTE_I); 482 case VM_MEMATTR_WRITE_THROUGH: 483 return (LPTE_W | LPTE_M); 484 } 485 } 486 487 /* 488 * Assume the page is cache inhibited and access is guarded unless 489 * it's in our available memory array. 490 */ 491 pte_lo = LPTE_I | LPTE_G; 492 for (i = 0; i < pregions_sz; i++) { 493 if ((pa >= pregions[i].mr_start) && 494 (pa < (pregions[i].mr_start + pregions[i].mr_size))) { 495 pte_lo &= ~(LPTE_I | LPTE_G); 496 pte_lo |= LPTE_M; 497 break; 498 } 499 } 500 501 return pte_lo; 502 } 503 504 /* 505 * Quick sort callout for comparing memory regions. 506 */ 507 static int om_cmp(const void *a, const void *b); 508 509 static int 510 om_cmp(const void *a, const void *b) 511 { 512 const struct ofw_map *mapa; 513 const struct ofw_map *mapb; 514 515 mapa = a; 516 mapb = b; 517 if (mapa->om_pa < mapb->om_pa) 518 return (-1); 519 else if (mapa->om_pa > mapb->om_pa) 520 return (1); 521 else 522 return (0); 523 } 524 525 static void 526 moea64_add_ofw_mappings(phandle_t mmu, size_t sz) 527 { 528 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */ 529 pcell_t acells, trans_cells[sz/sizeof(cell_t)]; 530 struct pvo_entry *pvo; 531 register_t msr; 532 vm_offset_t off; 533 vm_paddr_t pa_base; 534 int i, j; 535 536 bzero(translations, sz); 537 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells, 538 sizeof(acells)); 539 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1) 540 panic("moea64_bootstrap: can't get ofw translations"); 541 542 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations"); 543 sz /= sizeof(cell_t); 544 for (i = 0, j = 0; i < sz; j++) { 545 translations[j].om_va = trans_cells[i++]; 546 translations[j].om_len = trans_cells[i++]; 547 translations[j].om_pa = trans_cells[i++]; 548 if (acells == 2) { 549 translations[j].om_pa <<= 32; 550 translations[j].om_pa |= trans_cells[i++]; 551 } 552 translations[j].om_mode = trans_cells[i++]; 553 } 554 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)", 555 i, sz)); 556 557 sz = j; 558 qsort(translations, sz, sizeof (*translations), om_cmp); 559 560 for (i = 0; i < sz; i++) { 561 pa_base = translations[i].om_pa; 562 #ifndef __powerpc64__ 563 if ((translations[i].om_pa >> 32) != 0) 564 panic("OFW translations above 32-bit boundary!"); 565 #endif 566 567 if (pa_base % PAGE_SIZE) 568 panic("OFW translation not page-aligned (phys)!"); 569 if (translations[i].om_va % PAGE_SIZE) 570 panic("OFW translation not page-aligned (virt)!"); 571 572 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x", 573 pa_base, translations[i].om_va, translations[i].om_len); 574 575 /* Now enter the pages for this mapping */ 576 577 DISABLE_TRANS(msr); 578 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) { 579 /* If this address is direct-mapped, skip remapping */ 580 if (hw_direct_map && 581 translations[i].om_va == PHYS_TO_DMAP(pa_base) && 582 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) 583 == LPTE_M) 584 continue; 585 586 PMAP_LOCK(kernel_pmap); 587 pvo = moea64_pvo_find_va(kernel_pmap, 588 translations[i].om_va + off); 589 PMAP_UNLOCK(kernel_pmap); 590 if (pvo != NULL) 591 continue; 592 593 moea64_kenter(translations[i].om_va + off, 594 pa_base + off); 595 } 596 ENABLE_TRANS(msr); 597 } 598 } 599 600 #ifdef __powerpc64__ 601 static void 602 moea64_probe_large_page(void) 603 { 604 uint16_t pvr = mfpvr() >> 16; 605 606 switch (pvr) { 607 case IBM970: 608 case IBM970FX: 609 case IBM970MP: 610 powerpc_sync(); isync(); 611 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG); 612 powerpc_sync(); isync(); 613 614 /* FALLTHROUGH */ 615 default: 616 if (moea64_large_page_size == 0) { 617 moea64_large_page_size = 0x1000000; /* 16 MB */ 618 moea64_large_page_shift = 24; 619 } 620 } 621 622 moea64_large_page_mask = moea64_large_page_size - 1; 623 } 624 625 static void 626 moea64_bootstrap_slb_prefault(vm_offset_t va, int large) 627 { 628 struct slb *cache; 629 struct slb entry; 630 uint64_t esid, slbe; 631 uint64_t i; 632 633 cache = PCPU_GET(aim.slb); 634 esid = va >> ADDR_SR_SHFT; 635 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID; 636 637 for (i = 0; i < 64; i++) { 638 if (cache[i].slbe == (slbe | i)) 639 return; 640 } 641 642 entry.slbe = slbe; 643 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT; 644 if (large) 645 entry.slbv |= SLBV_L; 646 647 slb_insert_kernel(entry.slbe, entry.slbv); 648 } 649 #endif 650 651 static int 652 moea64_kenter_large(vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap) 653 { 654 struct pvo_entry *pvo; 655 uint64_t pte_lo; 656 int error; 657 658 pte_lo = LPTE_M; 659 pte_lo |= attr; 660 661 pvo = alloc_pvo_entry(bootstrap); 662 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE; 663 init_pvo_entry(pvo, kernel_pmap, va); 664 665 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | 666 VM_PROT_EXECUTE; 667 pvo->pvo_pte.pa = pa | pte_lo; 668 error = moea64_pvo_enter(pvo, NULL, NULL); 669 if (error != 0) 670 panic("Error %d inserting large page\n", error); 671 return (0); 672 } 673 674 static void 675 moea64_setup_direct_map(vm_offset_t kernelstart, 676 vm_offset_t kernelend) 677 { 678 register_t msr; 679 vm_paddr_t pa, pkernelstart, pkernelend; 680 vm_offset_t size, off; 681 uint64_t pte_lo; 682 int i; 683 684 if (moea64_large_page_size == 0) 685 hw_direct_map = 0; 686 687 DISABLE_TRANS(msr); 688 if (hw_direct_map) { 689 PMAP_LOCK(kernel_pmap); 690 for (i = 0; i < pregions_sz; i++) { 691 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start + 692 pregions[i].mr_size; pa += moea64_large_page_size) { 693 pte_lo = LPTE_M; 694 if (pa & moea64_large_page_mask) { 695 pa &= moea64_large_page_mask; 696 pte_lo |= LPTE_G; 697 } 698 if (pa + moea64_large_page_size > 699 pregions[i].mr_start + pregions[i].mr_size) 700 pte_lo |= LPTE_G; 701 702 moea64_kenter_large(PHYS_TO_DMAP(pa), pa, pte_lo, 1); 703 } 704 } 705 PMAP_UNLOCK(kernel_pmap); 706 } 707 708 /* 709 * Make sure the kernel and BPVO pool stay mapped on systems either 710 * without a direct map or on which the kernel is not already executing 711 * out of the direct-mapped region. 712 */ 713 if (kernelstart < DMAP_BASE_ADDRESS) { 714 /* 715 * For pre-dmap execution, we need to use identity mapping 716 * because we will be operating with the mmu on but in the 717 * wrong address configuration until we __restartkernel(). 718 */ 719 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend; 720 pa += PAGE_SIZE) 721 moea64_kenter(pa, pa); 722 } else if (!hw_direct_map) { 723 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS; 724 pkernelend = kernelend & ~DMAP_BASE_ADDRESS; 725 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend; 726 pa += PAGE_SIZE) 727 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 728 } 729 730 if (!hw_direct_map) { 731 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry); 732 off = (vm_offset_t)(moea64_bpvo_pool); 733 for (pa = off; pa < off + size; pa += PAGE_SIZE) 734 moea64_kenter(pa, pa); 735 736 /* Map exception vectors */ 737 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE) 738 moea64_kenter(pa | DMAP_BASE_ADDRESS, pa); 739 } 740 ENABLE_TRANS(msr); 741 742 /* 743 * Allow user to override unmapped_buf_allowed for testing. 744 * XXXKIB Only direct map implementation was tested. 745 */ 746 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed", 747 &unmapped_buf_allowed)) 748 unmapped_buf_allowed = hw_direct_map; 749 } 750 751 /* Quick sort callout for comparing physical addresses. */ 752 static int 753 pa_cmp(const void *a, const void *b) 754 { 755 const vm_paddr_t *pa = a, *pb = b; 756 757 if (*pa < *pb) 758 return (-1); 759 else if (*pa > *pb) 760 return (1); 761 else 762 return (0); 763 } 764 765 void 766 moea64_early_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 767 { 768 int i, j; 769 vm_size_t physsz, hwphyssz; 770 vm_paddr_t kernelphysstart, kernelphysend; 771 int rm_pavail; 772 773 #ifndef __powerpc64__ 774 /* We don't have a direct map since there is no BAT */ 775 hw_direct_map = 0; 776 777 /* Make sure battable is zero, since we have no BAT */ 778 for (i = 0; i < 16; i++) { 779 battable[i].batu = 0; 780 battable[i].batl = 0; 781 } 782 #else 783 moea64_probe_large_page(); 784 785 /* Use a direct map if we have large page support */ 786 if (moea64_large_page_size > 0) 787 hw_direct_map = 1; 788 else 789 hw_direct_map = 0; 790 791 /* Install trap handlers for SLBs */ 792 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap); 793 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap); 794 __syncicache((void *)EXC_DSE, 0x80); 795 __syncicache((void *)EXC_ISE, 0x80); 796 #endif 797 798 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS; 799 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS; 800 801 /* Get physical memory regions from firmware */ 802 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 803 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory"); 804 805 if (PHYS_AVAIL_ENTRIES < regions_sz) 806 panic("moea64_bootstrap: phys_avail too small"); 807 808 phys_avail_count = 0; 809 physsz = 0; 810 hwphyssz = 0; 811 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 812 for (i = 0, j = 0; i < regions_sz; i++, j += 2) { 813 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)", 814 regions[i].mr_start, regions[i].mr_start + 815 regions[i].mr_size, regions[i].mr_size); 816 if (hwphyssz != 0 && 817 (physsz + regions[i].mr_size) >= hwphyssz) { 818 if (physsz < hwphyssz) { 819 phys_avail[j] = regions[i].mr_start; 820 phys_avail[j + 1] = regions[i].mr_start + 821 hwphyssz - physsz; 822 physsz = hwphyssz; 823 phys_avail_count++; 824 dump_avail[j] = phys_avail[j]; 825 dump_avail[j + 1] = phys_avail[j + 1]; 826 } 827 break; 828 } 829 phys_avail[j] = regions[i].mr_start; 830 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size; 831 phys_avail_count++; 832 physsz += regions[i].mr_size; 833 dump_avail[j] = phys_avail[j]; 834 dump_avail[j + 1] = phys_avail[j + 1]; 835 } 836 837 /* Check for overlap with the kernel and exception vectors */ 838 rm_pavail = 0; 839 for (j = 0; j < 2*phys_avail_count; j+=2) { 840 if (phys_avail[j] < EXC_LAST) 841 phys_avail[j] += EXC_LAST; 842 843 if (phys_avail[j] >= kernelphysstart && 844 phys_avail[j+1] <= kernelphysend) { 845 phys_avail[j] = phys_avail[j+1] = ~0; 846 rm_pavail++; 847 continue; 848 } 849 850 if (kernelphysstart >= phys_avail[j] && 851 kernelphysstart < phys_avail[j+1]) { 852 if (kernelphysend < phys_avail[j+1]) { 853 phys_avail[2*phys_avail_count] = 854 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE; 855 phys_avail[2*phys_avail_count + 1] = 856 phys_avail[j+1]; 857 phys_avail_count++; 858 } 859 860 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK; 861 } 862 863 if (kernelphysend >= phys_avail[j] && 864 kernelphysend < phys_avail[j+1]) { 865 if (kernelphysstart > phys_avail[j]) { 866 phys_avail[2*phys_avail_count] = phys_avail[j]; 867 phys_avail[2*phys_avail_count + 1] = 868 kernelphysstart & ~PAGE_MASK; 869 phys_avail_count++; 870 } 871 872 phys_avail[j] = (kernelphysend & ~PAGE_MASK) + 873 PAGE_SIZE; 874 } 875 } 876 877 /* Remove physical available regions marked for removal (~0) */ 878 if (rm_pavail) { 879 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]), 880 pa_cmp); 881 phys_avail_count -= rm_pavail; 882 for (i = 2*phys_avail_count; 883 i < 2*(phys_avail_count + rm_pavail); i+=2) 884 phys_avail[i] = phys_avail[i+1] = 0; 885 } 886 887 physmem = btoc(physsz); 888 889 #ifdef PTEGCOUNT 890 moea64_pteg_count = PTEGCOUNT; 891 #else 892 moea64_pteg_count = 0x1000; 893 894 while (moea64_pteg_count < physmem) 895 moea64_pteg_count <<= 1; 896 897 moea64_pteg_count >>= 1; 898 #endif /* PTEGCOUNT */ 899 } 900 901 void 902 moea64_mid_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 903 { 904 int i; 905 906 /* 907 * Set PTEG mask 908 */ 909 moea64_pteg_mask = moea64_pteg_count - 1; 910 911 /* 912 * Initialize SLB table lock and page locks 913 */ 914 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF); 915 for (i = 0; i < PV_LOCK_COUNT; i++) 916 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF); 917 918 /* 919 * Initialise the bootstrap pvo pool. 920 */ 921 TUNABLE_INT_FETCH("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size); 922 if (moea64_bpvo_pool_size == 0) { 923 if (!hw_direct_map) 924 moea64_bpvo_pool_size = ((ptoa((uintmax_t)physmem) * sizeof(struct vm_page)) / 925 (PAGE_SIZE * PAGE_SIZE)) * BPVO_POOL_EXPANSION_FACTOR; 926 else 927 moea64_bpvo_pool_size = BPVO_POOL_SIZE; 928 } 929 930 if (boothowto & RB_VERBOSE) { 931 printf("mmu_oea64: bpvo pool entries = %d, bpvo pool size = %zu MB\n", 932 moea64_bpvo_pool_size, 933 moea64_bpvo_pool_size*sizeof(struct pvo_entry) / 1048576); 934 } 935 936 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc( 937 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE); 938 moea64_bpvo_pool_index = 0; 939 940 /* Place at address usable through the direct map */ 941 if (hw_direct_map) 942 moea64_bpvo_pool = (struct pvo_entry *) 943 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool); 944 945 /* 946 * Make sure kernel vsid is allocated as well as VSID 0. 947 */ 948 #ifndef __powerpc64__ 949 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW] 950 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW); 951 moea64_vsid_bitmap[0] |= 1; 952 #endif 953 954 /* 955 * Initialize the kernel pmap (which is statically allocated). 956 */ 957 #ifdef __powerpc64__ 958 for (i = 0; i < 64; i++) { 959 pcpup->pc_aim.slb[i].slbv = 0; 960 pcpup->pc_aim.slb[i].slbe = 0; 961 } 962 #else 963 for (i = 0; i < 16; i++) 964 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i; 965 #endif 966 967 kernel_pmap->pmap_phys = kernel_pmap; 968 CPU_FILL(&kernel_pmap->pm_active); 969 RB_INIT(&kernel_pmap->pmap_pvo); 970 971 PMAP_LOCK_INIT(kernel_pmap); 972 973 /* 974 * Now map in all the other buffers we allocated earlier 975 */ 976 977 moea64_setup_direct_map(kernelstart, kernelend); 978 } 979 980 void 981 moea64_late_bootstrap(vm_offset_t kernelstart, vm_offset_t kernelend) 982 { 983 ihandle_t mmui; 984 phandle_t chosen; 985 phandle_t mmu; 986 ssize_t sz; 987 int i; 988 vm_offset_t pa, va; 989 void *dpcpu; 990 991 /* 992 * Set up the Open Firmware pmap and add its mappings if not in real 993 * mode. 994 */ 995 996 chosen = OF_finddevice("/chosen"); 997 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) { 998 mmu = OF_instance_to_package(mmui); 999 if (mmu == -1 || 1000 (sz = OF_getproplen(mmu, "translations")) == -1) 1001 sz = 0; 1002 if (sz > 6144 /* tmpstksz - 2 KB headroom */) 1003 panic("moea64_bootstrap: too many ofw translations"); 1004 1005 if (sz > 0) 1006 moea64_add_ofw_mappings(mmu, sz); 1007 } 1008 1009 /* 1010 * Calculate the last available physical address. 1011 */ 1012 Maxmem = 0; 1013 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1014 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1])); 1015 1016 /* 1017 * Initialize MMU. 1018 */ 1019 pmap_cpu_bootstrap(0); 1020 mtmsr(mfmsr() | PSL_DR | PSL_IR); 1021 pmap_bootstrapped++; 1022 1023 /* 1024 * Set the start and end of kva. 1025 */ 1026 virtual_avail = VM_MIN_KERNEL_ADDRESS; 1027 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS; 1028 1029 /* 1030 * Map the entire KVA range into the SLB. We must not fault there. 1031 */ 1032 #ifdef __powerpc64__ 1033 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH) 1034 moea64_bootstrap_slb_prefault(va, 0); 1035 #endif 1036 1037 /* 1038 * Remap any early IO mappings (console framebuffer, etc.) 1039 */ 1040 bs_remap_earlyboot(); 1041 1042 /* 1043 * Figure out how far we can extend virtual_end into segment 16 1044 * without running into existing mappings. Segment 16 is guaranteed 1045 * to contain neither RAM nor devices (at least on Apple hardware), 1046 * but will generally contain some OFW mappings we should not 1047 * step on. 1048 */ 1049 1050 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */ 1051 PMAP_LOCK(kernel_pmap); 1052 while (virtual_end < VM_MAX_KERNEL_ADDRESS && 1053 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL) 1054 virtual_end += PAGE_SIZE; 1055 PMAP_UNLOCK(kernel_pmap); 1056 #endif 1057 1058 /* 1059 * Allocate a kernel stack with a guard page for thread0 and map it 1060 * into the kernel page map. 1061 */ 1062 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE); 1063 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1064 virtual_avail = va + kstack_pages * PAGE_SIZE; 1065 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va); 1066 thread0.td_kstack = va; 1067 thread0.td_kstack_pages = kstack_pages; 1068 for (i = 0; i < kstack_pages; i++) { 1069 moea64_kenter(va, pa); 1070 pa += PAGE_SIZE; 1071 va += PAGE_SIZE; 1072 } 1073 1074 /* 1075 * Allocate virtual address space for the message buffer. 1076 */ 1077 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE); 1078 msgbufp = (struct msgbuf *)virtual_avail; 1079 va = virtual_avail; 1080 virtual_avail += round_page(msgbufsize); 1081 while (va < virtual_avail) { 1082 moea64_kenter(va, pa); 1083 pa += PAGE_SIZE; 1084 va += PAGE_SIZE; 1085 } 1086 1087 /* 1088 * Allocate virtual address space for the dynamic percpu area. 1089 */ 1090 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE); 1091 dpcpu = (void *)virtual_avail; 1092 va = virtual_avail; 1093 virtual_avail += DPCPU_SIZE; 1094 while (va < virtual_avail) { 1095 moea64_kenter(va, pa); 1096 pa += PAGE_SIZE; 1097 va += PAGE_SIZE; 1098 } 1099 dpcpu_init(dpcpu, curcpu); 1100 1101 crashdumpmap = (caddr_t)virtual_avail; 1102 virtual_avail += MAXDUMPPGS * PAGE_SIZE; 1103 1104 /* 1105 * Allocate some things for page zeroing. We put this directly 1106 * in the page table and use MOEA64_PTE_REPLACE to avoid any 1107 * of the PVO book-keeping or other parts of the VM system 1108 * from even knowing that this hack exists. 1109 */ 1110 1111 if (!hw_direct_map) { 1112 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL, 1113 MTX_DEF); 1114 for (i = 0; i < 2; i++) { 1115 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE; 1116 virtual_end -= PAGE_SIZE; 1117 1118 moea64_kenter(moea64_scratchpage_va[i], 0); 1119 1120 PMAP_LOCK(kernel_pmap); 1121 moea64_scratchpage_pvo[i] = moea64_pvo_find_va( 1122 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]); 1123 PMAP_UNLOCK(kernel_pmap); 1124 } 1125 } 1126 1127 numa_mem_regions(&numa_pregions, &numapregions_sz); 1128 } 1129 1130 static void 1131 moea64_pmap_init_qpages(void) 1132 { 1133 struct pcpu *pc; 1134 int i; 1135 1136 if (hw_direct_map) 1137 return; 1138 1139 CPU_FOREACH(i) { 1140 pc = pcpu_find(i); 1141 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1142 if (pc->pc_qmap_addr == 0) 1143 panic("pmap_init_qpages: unable to allocate KVA"); 1144 PMAP_LOCK(kernel_pmap); 1145 pc->pc_aim.qmap_pvo = 1146 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr); 1147 PMAP_UNLOCK(kernel_pmap); 1148 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF); 1149 } 1150 } 1151 1152 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL); 1153 1154 /* 1155 * Activate a user pmap. This mostly involves setting some non-CPU 1156 * state. 1157 */ 1158 void 1159 moea64_activate(struct thread *td) 1160 { 1161 pmap_t pm; 1162 1163 pm = &td->td_proc->p_vmspace->vm_pmap; 1164 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 1165 1166 #ifdef __powerpc64__ 1167 PCPU_SET(aim.userslb, pm->pm_slb); 1168 __asm __volatile("slbmte %0, %1; isync" :: 1169 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE)); 1170 #else 1171 PCPU_SET(curpmap, pm->pmap_phys); 1172 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid); 1173 #endif 1174 } 1175 1176 void 1177 moea64_deactivate(struct thread *td) 1178 { 1179 pmap_t pm; 1180 1181 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR)); 1182 1183 pm = &td->td_proc->p_vmspace->vm_pmap; 1184 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active); 1185 #ifdef __powerpc64__ 1186 PCPU_SET(aim.userslb, NULL); 1187 #else 1188 PCPU_SET(curpmap, NULL); 1189 #endif 1190 } 1191 1192 void 1193 moea64_unwire(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1194 { 1195 struct pvo_entry key, *pvo; 1196 vm_page_t m; 1197 int64_t refchg; 1198 1199 key.pvo_vaddr = sva; 1200 PMAP_LOCK(pm); 1201 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 1202 pvo != NULL && PVO_VADDR(pvo) < eva; 1203 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) { 1204 if ((pvo->pvo_vaddr & PVO_WIRED) == 0) 1205 panic("moea64_unwire: pvo %p is missing PVO_WIRED", 1206 pvo); 1207 pvo->pvo_vaddr &= ~PVO_WIRED; 1208 refchg = moea64_pte_replace(pvo, 0 /* No invalidation */); 1209 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1210 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1211 if (refchg < 0) 1212 refchg = LPTE_CHG; 1213 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1214 1215 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs); 1216 if (refchg & LPTE_CHG) 1217 vm_page_dirty(m); 1218 if (refchg & LPTE_REF) 1219 vm_page_aflag_set(m, PGA_REFERENCED); 1220 } 1221 pm->pm_stats.wired_count--; 1222 } 1223 PMAP_UNLOCK(pm); 1224 } 1225 1226 /* 1227 * This goes through and sets the physical address of our 1228 * special scratch PTE to the PA we want to zero or copy. Because 1229 * of locking issues (this can get called in pvo_enter() by 1230 * the UMA allocator), we can't use most other utility functions here 1231 */ 1232 1233 static __inline 1234 void moea64_set_scratchpage_pa(int which, vm_paddr_t pa) 1235 { 1236 struct pvo_entry *pvo; 1237 1238 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!")); 1239 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED); 1240 1241 pvo = moea64_scratchpage_pvo[which]; 1242 PMAP_LOCK(pvo->pvo_pmap); 1243 pvo->pvo_pte.pa = 1244 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa; 1245 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1246 PMAP_UNLOCK(pvo->pvo_pmap); 1247 isync(); 1248 } 1249 1250 void 1251 moea64_copy_page(vm_page_t msrc, vm_page_t mdst) 1252 { 1253 vm_offset_t dst; 1254 vm_offset_t src; 1255 1256 dst = VM_PAGE_TO_PHYS(mdst); 1257 src = VM_PAGE_TO_PHYS(msrc); 1258 1259 if (hw_direct_map) { 1260 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst), 1261 PAGE_SIZE); 1262 } else { 1263 mtx_lock(&moea64_scratchpage_mtx); 1264 1265 moea64_set_scratchpage_pa(0, src); 1266 moea64_set_scratchpage_pa(1, dst); 1267 1268 bcopy((void *)moea64_scratchpage_va[0], 1269 (void *)moea64_scratchpage_va[1], PAGE_SIZE); 1270 1271 mtx_unlock(&moea64_scratchpage_mtx); 1272 } 1273 } 1274 1275 static inline void 1276 moea64_copy_pages_dmap(vm_page_t *ma, vm_offset_t a_offset, 1277 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1278 { 1279 void *a_cp, *b_cp; 1280 vm_offset_t a_pg_offset, b_pg_offset; 1281 int cnt; 1282 1283 while (xfersize > 0) { 1284 a_pg_offset = a_offset & PAGE_MASK; 1285 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1286 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1287 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) + 1288 a_pg_offset; 1289 b_pg_offset = b_offset & PAGE_MASK; 1290 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1291 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP( 1292 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) + 1293 b_pg_offset; 1294 bcopy(a_cp, b_cp, cnt); 1295 a_offset += cnt; 1296 b_offset += cnt; 1297 xfersize -= cnt; 1298 } 1299 } 1300 1301 static inline void 1302 moea64_copy_pages_nodmap(vm_page_t *ma, vm_offset_t a_offset, 1303 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1304 { 1305 void *a_cp, *b_cp; 1306 vm_offset_t a_pg_offset, b_pg_offset; 1307 int cnt; 1308 1309 mtx_lock(&moea64_scratchpage_mtx); 1310 while (xfersize > 0) { 1311 a_pg_offset = a_offset & PAGE_MASK; 1312 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 1313 moea64_set_scratchpage_pa(0, 1314 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 1315 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset; 1316 b_pg_offset = b_offset & PAGE_MASK; 1317 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 1318 moea64_set_scratchpage_pa(1, 1319 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 1320 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset; 1321 bcopy(a_cp, b_cp, cnt); 1322 a_offset += cnt; 1323 b_offset += cnt; 1324 xfersize -= cnt; 1325 } 1326 mtx_unlock(&moea64_scratchpage_mtx); 1327 } 1328 1329 void 1330 moea64_copy_pages(vm_page_t *ma, vm_offset_t a_offset, 1331 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 1332 { 1333 1334 if (hw_direct_map) { 1335 moea64_copy_pages_dmap(ma, a_offset, mb, b_offset, 1336 xfersize); 1337 } else { 1338 moea64_copy_pages_nodmap(ma, a_offset, mb, b_offset, 1339 xfersize); 1340 } 1341 } 1342 1343 void 1344 moea64_zero_page_area(vm_page_t m, int off, int size) 1345 { 1346 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1347 1348 if (size + off > PAGE_SIZE) 1349 panic("moea64_zero_page: size + off > PAGE_SIZE"); 1350 1351 if (hw_direct_map) { 1352 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size); 1353 } else { 1354 mtx_lock(&moea64_scratchpage_mtx); 1355 moea64_set_scratchpage_pa(0, pa); 1356 bzero((caddr_t)moea64_scratchpage_va[0] + off, size); 1357 mtx_unlock(&moea64_scratchpage_mtx); 1358 } 1359 } 1360 1361 /* 1362 * Zero a page of physical memory by temporarily mapping it 1363 */ 1364 void 1365 moea64_zero_page(vm_page_t m) 1366 { 1367 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1368 vm_offset_t va, off; 1369 1370 if (!hw_direct_map) { 1371 mtx_lock(&moea64_scratchpage_mtx); 1372 1373 moea64_set_scratchpage_pa(0, pa); 1374 va = moea64_scratchpage_va[0]; 1375 } else { 1376 va = PHYS_TO_DMAP(pa); 1377 } 1378 1379 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 1380 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 1381 1382 if (!hw_direct_map) 1383 mtx_unlock(&moea64_scratchpage_mtx); 1384 } 1385 1386 vm_offset_t 1387 moea64_quick_enter_page(vm_page_t m) 1388 { 1389 struct pvo_entry *pvo; 1390 vm_paddr_t pa = VM_PAGE_TO_PHYS(m); 1391 1392 if (hw_direct_map) 1393 return (PHYS_TO_DMAP(pa)); 1394 1395 /* 1396 * MOEA64_PTE_REPLACE does some locking, so we can't just grab 1397 * a critical section and access the PCPU data like on i386. 1398 * Instead, pin the thread and grab the PCPU lock to prevent 1399 * a preempting thread from using the same PCPU data. 1400 */ 1401 sched_pin(); 1402 1403 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED); 1404 pvo = PCPU_GET(aim.qmap_pvo); 1405 1406 mtx_lock(PCPU_PTR(aim.qmap_lock)); 1407 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) | 1408 (uint64_t)pa; 1409 moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1410 isync(); 1411 1412 return (PCPU_GET(qmap_addr)); 1413 } 1414 1415 void 1416 moea64_quick_remove_page(vm_offset_t addr) 1417 { 1418 if (hw_direct_map) 1419 return; 1420 1421 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED); 1422 KASSERT(PCPU_GET(qmap_addr) == addr, 1423 ("moea64_quick_remove_page: invalid address")); 1424 mtx_unlock(PCPU_PTR(aim.qmap_lock)); 1425 sched_unpin(); 1426 } 1427 1428 boolean_t 1429 moea64_page_is_mapped(vm_page_t m) 1430 { 1431 return (!LIST_EMPTY(&(m)->md.mdpg_pvoh)); 1432 } 1433 1434 /* 1435 * Map the given physical page at the specified virtual address in the 1436 * target pmap with the protection requested. If specified the page 1437 * will be wired down. 1438 */ 1439 1440 int 1441 moea64_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, 1442 vm_prot_t prot, u_int flags, int8_t psind) 1443 { 1444 struct pvo_entry *pvo, *oldpvo; 1445 struct pvo_head *pvo_head; 1446 uint64_t pte_lo; 1447 int error; 1448 1449 if ((m->oflags & VPO_UNMANAGED) == 0) { 1450 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0) 1451 VM_PAGE_OBJECT_BUSY_ASSERT(m); 1452 else 1453 VM_OBJECT_ASSERT_LOCKED(m->object); 1454 } 1455 1456 pvo = alloc_pvo_entry(0); 1457 if (pvo == NULL) 1458 return (KERN_RESOURCE_SHORTAGE); 1459 pvo->pvo_pmap = NULL; /* to be filled in later */ 1460 pvo->pvo_pte.prot = prot; 1461 1462 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m)); 1463 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo; 1464 1465 if ((flags & PMAP_ENTER_WIRED) != 0) 1466 pvo->pvo_vaddr |= PVO_WIRED; 1467 1468 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) { 1469 pvo_head = NULL; 1470 } else { 1471 pvo_head = &m->md.mdpg_pvoh; 1472 pvo->pvo_vaddr |= PVO_MANAGED; 1473 } 1474 1475 PV_PAGE_LOCK(m); 1476 PMAP_LOCK(pmap); 1477 if (pvo->pvo_pmap == NULL) 1478 init_pvo_entry(pvo, pmap, va); 1479 if (prot & VM_PROT_WRITE) 1480 if (pmap_bootstrapped && 1481 (m->oflags & VPO_UNMANAGED) == 0) 1482 vm_page_aflag_set(m, PGA_WRITEABLE); 1483 1484 error = moea64_pvo_enter(pvo, pvo_head, &oldpvo); 1485 if (error == EEXIST) { 1486 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr && 1487 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa && 1488 oldpvo->pvo_pte.prot == prot) { 1489 /* Identical mapping already exists */ 1490 error = 0; 1491 1492 /* If not in page table, reinsert it */ 1493 if (moea64_pte_synch(oldpvo) < 0) { 1494 STAT_MOEA64(moea64_pte_overflow--); 1495 moea64_pte_insert(oldpvo); 1496 } 1497 1498 /* Then just clean up and go home */ 1499 PV_PAGE_UNLOCK(m); 1500 PMAP_UNLOCK(pmap); 1501 free_pvo_entry(pvo); 1502 goto out; 1503 } else { 1504 /* Otherwise, need to kill it first */ 1505 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old " 1506 "mapping does not match new mapping")); 1507 moea64_pvo_remove_from_pmap(oldpvo); 1508 moea64_pvo_enter(pvo, pvo_head, NULL); 1509 } 1510 } 1511 PMAP_UNLOCK(pmap); 1512 PV_PAGE_UNLOCK(m); 1513 1514 /* Free any dead pages */ 1515 if (error == EEXIST) { 1516 moea64_pvo_remove_from_page(oldpvo); 1517 free_pvo_entry(oldpvo); 1518 } 1519 1520 out: 1521 /* 1522 * Flush the page from the instruction cache if this page is 1523 * mapped executable and cacheable. 1524 */ 1525 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 && 1526 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 1527 vm_page_aflag_set(m, PGA_EXECUTABLE); 1528 moea64_syncicache(pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE); 1529 } 1530 return (KERN_SUCCESS); 1531 } 1532 1533 static void 1534 moea64_syncicache(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 1535 vm_size_t sz) 1536 { 1537 1538 /* 1539 * This is much trickier than on older systems because 1540 * we can't sync the icache on physical addresses directly 1541 * without a direct map. Instead we check a couple of cases 1542 * where the memory is already mapped in and, failing that, 1543 * use the same trick we use for page zeroing to create 1544 * a temporary mapping for this physical address. 1545 */ 1546 1547 if (!pmap_bootstrapped) { 1548 /* 1549 * If PMAP is not bootstrapped, we are likely to be 1550 * in real mode. 1551 */ 1552 __syncicache((void *)(uintptr_t)pa, sz); 1553 } else if (pmap == kernel_pmap) { 1554 __syncicache((void *)va, sz); 1555 } else if (hw_direct_map) { 1556 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz); 1557 } else { 1558 /* Use the scratch page to set up a temp mapping */ 1559 1560 mtx_lock(&moea64_scratchpage_mtx); 1561 1562 moea64_set_scratchpage_pa(1, pa & ~ADDR_POFF); 1563 __syncicache((void *)(moea64_scratchpage_va[1] + 1564 (va & ADDR_POFF)), sz); 1565 1566 mtx_unlock(&moea64_scratchpage_mtx); 1567 } 1568 } 1569 1570 /* 1571 * Maps a sequence of resident pages belonging to the same object. 1572 * The sequence begins with the given page m_start. This page is 1573 * mapped at the given virtual address start. Each subsequent page is 1574 * mapped at a virtual address that is offset from start by the same 1575 * amount as the page is offset from m_start within the object. The 1576 * last page in the sequence is the page with the largest offset from 1577 * m_start that can be mapped at a virtual address less than the given 1578 * virtual address end. Not every virtual page between start and end 1579 * is mapped; only those for which a resident page exists with the 1580 * corresponding offset from m_start are mapped. 1581 */ 1582 void 1583 moea64_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1584 vm_page_t m_start, vm_prot_t prot) 1585 { 1586 vm_page_t m; 1587 vm_pindex_t diff, psize; 1588 1589 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1590 1591 psize = atop(end - start); 1592 m = m_start; 1593 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1594 moea64_enter(pm, start + ptoa(diff), m, prot & 1595 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP | 1596 PMAP_ENTER_QUICK_LOCKED, 0); 1597 m = TAILQ_NEXT(m, listq); 1598 } 1599 } 1600 1601 void 1602 moea64_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, 1603 vm_prot_t prot) 1604 { 1605 1606 moea64_enter(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1607 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0); 1608 } 1609 1610 vm_paddr_t 1611 moea64_extract(pmap_t pm, vm_offset_t va) 1612 { 1613 struct pvo_entry *pvo; 1614 vm_paddr_t pa; 1615 1616 PMAP_LOCK(pm); 1617 pvo = moea64_pvo_find_va(pm, va); 1618 if (pvo == NULL) 1619 pa = 0; 1620 else 1621 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 1622 PMAP_UNLOCK(pm); 1623 1624 return (pa); 1625 } 1626 1627 /* 1628 * Atomically extract and hold the physical page with the given 1629 * pmap and virtual address pair if that mapping permits the given 1630 * protection. 1631 */ 1632 vm_page_t 1633 moea64_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1634 { 1635 struct pvo_entry *pvo; 1636 vm_page_t m; 1637 1638 m = NULL; 1639 PMAP_LOCK(pmap); 1640 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1641 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) { 1642 m = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 1643 if (!vm_page_wire_mapped(m)) 1644 m = NULL; 1645 } 1646 PMAP_UNLOCK(pmap); 1647 return (m); 1648 } 1649 1650 static void * 1651 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain, 1652 uint8_t *flags, int wait) 1653 { 1654 struct pvo_entry *pvo; 1655 vm_offset_t va; 1656 vm_page_t m; 1657 int needed_lock; 1658 1659 /* 1660 * This entire routine is a horrible hack to avoid bothering kmem 1661 * for new KVA addresses. Because this can get called from inside 1662 * kmem allocation routines, calling kmem for a new address here 1663 * can lead to multiply locking non-recursive mutexes. 1664 */ 1665 1666 *flags = UMA_SLAB_PRIV; 1667 needed_lock = !PMAP_LOCKED(kernel_pmap); 1668 1669 m = vm_page_alloc_domain(NULL, 0, domain, 1670 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ); 1671 if (m == NULL) 1672 return (NULL); 1673 1674 va = VM_PAGE_TO_PHYS(m); 1675 1676 pvo = alloc_pvo_entry(1 /* bootstrap */); 1677 1678 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE; 1679 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M; 1680 1681 if (needed_lock) 1682 PMAP_LOCK(kernel_pmap); 1683 1684 init_pvo_entry(pvo, kernel_pmap, va); 1685 pvo->pvo_vaddr |= PVO_WIRED; 1686 1687 moea64_pvo_enter(pvo, NULL, NULL); 1688 1689 if (needed_lock) 1690 PMAP_UNLOCK(kernel_pmap); 1691 1692 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0) 1693 bzero((void *)va, PAGE_SIZE); 1694 1695 return (void *)va; 1696 } 1697 1698 extern int elf32_nxstack; 1699 1700 void 1701 moea64_init() 1702 { 1703 1704 CTR0(KTR_PMAP, "moea64_init"); 1705 1706 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry), 1707 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, 1708 UMA_ZONE_VM | UMA_ZONE_NOFREE); 1709 1710 if (!hw_direct_map) { 1711 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc); 1712 } 1713 1714 #ifdef COMPAT_FREEBSD32 1715 elf32_nxstack = 1; 1716 #endif 1717 1718 moea64_initialized = TRUE; 1719 } 1720 1721 boolean_t 1722 moea64_is_referenced(vm_page_t m) 1723 { 1724 1725 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1726 ("moea64_is_referenced: page %p is not managed", m)); 1727 1728 return (moea64_query_bit(m, LPTE_REF)); 1729 } 1730 1731 boolean_t 1732 moea64_is_modified(vm_page_t m) 1733 { 1734 1735 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1736 ("moea64_is_modified: page %p is not managed", m)); 1737 1738 /* 1739 * If the page is not busied then this check is racy. 1740 */ 1741 if (!pmap_page_is_write_mapped(m)) 1742 return (FALSE); 1743 1744 return (moea64_query_bit(m, LPTE_CHG)); 1745 } 1746 1747 boolean_t 1748 moea64_is_prefaultable(pmap_t pmap, vm_offset_t va) 1749 { 1750 struct pvo_entry *pvo; 1751 boolean_t rv = TRUE; 1752 1753 PMAP_LOCK(pmap); 1754 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF); 1755 if (pvo != NULL) 1756 rv = FALSE; 1757 PMAP_UNLOCK(pmap); 1758 return (rv); 1759 } 1760 1761 void 1762 moea64_clear_modify(vm_page_t m) 1763 { 1764 1765 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1766 ("moea64_clear_modify: page %p is not managed", m)); 1767 vm_page_assert_busied(m); 1768 1769 if (!pmap_page_is_write_mapped(m)) 1770 return; 1771 moea64_clear_bit(m, LPTE_CHG); 1772 } 1773 1774 /* 1775 * Clear the write and modified bits in each of the given page's mappings. 1776 */ 1777 void 1778 moea64_remove_write(vm_page_t m) 1779 { 1780 struct pvo_entry *pvo; 1781 int64_t refchg, ret; 1782 pmap_t pmap; 1783 1784 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1785 ("moea64_remove_write: page %p is not managed", m)); 1786 vm_page_assert_busied(m); 1787 1788 if (!pmap_page_is_write_mapped(m)) 1789 return 1790 1791 powerpc_sync(); 1792 PV_PAGE_LOCK(m); 1793 refchg = 0; 1794 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1795 pmap = pvo->pvo_pmap; 1796 PMAP_LOCK(pmap); 1797 if (!(pvo->pvo_vaddr & PVO_DEAD) && 1798 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1799 pvo->pvo_pte.prot &= ~VM_PROT_WRITE; 1800 ret = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 1801 if (ret < 0) 1802 ret = LPTE_CHG; 1803 refchg |= ret; 1804 if (pvo->pvo_pmap == kernel_pmap) 1805 isync(); 1806 } 1807 PMAP_UNLOCK(pmap); 1808 } 1809 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG) 1810 vm_page_dirty(m); 1811 vm_page_aflag_clear(m, PGA_WRITEABLE); 1812 PV_PAGE_UNLOCK(m); 1813 } 1814 1815 /* 1816 * moea64_ts_referenced: 1817 * 1818 * Return a count of reference bits for a page, clearing those bits. 1819 * It is not necessary for every reference bit to be cleared, but it 1820 * is necessary that 0 only be returned when there are truly no 1821 * reference bits set. 1822 * 1823 * XXX: The exact number of bits to check and clear is a matter that 1824 * should be tested and standardized at some point in the future for 1825 * optimal aging of shared pages. 1826 */ 1827 int 1828 moea64_ts_referenced(vm_page_t m) 1829 { 1830 1831 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1832 ("moea64_ts_referenced: page %p is not managed", m)); 1833 return (moea64_clear_bit(m, LPTE_REF)); 1834 } 1835 1836 /* 1837 * Modify the WIMG settings of all mappings for a page. 1838 */ 1839 void 1840 moea64_page_set_memattr(vm_page_t m, vm_memattr_t ma) 1841 { 1842 struct pvo_entry *pvo; 1843 int64_t refchg; 1844 pmap_t pmap; 1845 uint64_t lo; 1846 1847 if ((m->oflags & VPO_UNMANAGED) != 0) { 1848 m->md.mdpg_cache_attrs = ma; 1849 return; 1850 } 1851 1852 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma); 1853 1854 PV_PAGE_LOCK(m); 1855 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 1856 pmap = pvo->pvo_pmap; 1857 PMAP_LOCK(pmap); 1858 if (!(pvo->pvo_vaddr & PVO_DEAD)) { 1859 pvo->pvo_pte.pa &= ~LPTE_WIMG; 1860 pvo->pvo_pte.pa |= lo; 1861 refchg = moea64_pte_replace(pvo, MOEA64_PTE_INVALIDATE); 1862 if (refchg < 0) 1863 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ? 1864 LPTE_CHG : 0; 1865 if ((pvo->pvo_vaddr & PVO_MANAGED) && 1866 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 1867 refchg |= 1868 atomic_readandclear_32(&m->md.mdpg_attrs); 1869 if (refchg & LPTE_CHG) 1870 vm_page_dirty(m); 1871 if (refchg & LPTE_REF) 1872 vm_page_aflag_set(m, PGA_REFERENCED); 1873 } 1874 if (pvo->pvo_pmap == kernel_pmap) 1875 isync(); 1876 } 1877 PMAP_UNLOCK(pmap); 1878 } 1879 m->md.mdpg_cache_attrs = ma; 1880 PV_PAGE_UNLOCK(m); 1881 } 1882 1883 /* 1884 * Map a wired page into kernel virtual address space. 1885 */ 1886 void 1887 moea64_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1888 { 1889 int error; 1890 struct pvo_entry *pvo, *oldpvo; 1891 1892 do { 1893 pvo = alloc_pvo_entry(0); 1894 if (pvo == NULL) 1895 vm_wait(NULL); 1896 } while (pvo == NULL); 1897 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE; 1898 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma); 1899 pvo->pvo_vaddr |= PVO_WIRED; 1900 1901 PMAP_LOCK(kernel_pmap); 1902 oldpvo = moea64_pvo_find_va(kernel_pmap, va); 1903 if (oldpvo != NULL) 1904 moea64_pvo_remove_from_pmap(oldpvo); 1905 init_pvo_entry(pvo, kernel_pmap, va); 1906 error = moea64_pvo_enter(pvo, NULL, NULL); 1907 PMAP_UNLOCK(kernel_pmap); 1908 1909 /* Free any dead pages */ 1910 if (oldpvo != NULL) { 1911 moea64_pvo_remove_from_page(oldpvo); 1912 free_pvo_entry(oldpvo); 1913 } 1914 1915 if (error != 0) 1916 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va, 1917 (uintmax_t)pa, error); 1918 } 1919 1920 void 1921 moea64_kenter(vm_offset_t va, vm_paddr_t pa) 1922 { 1923 1924 moea64_kenter_attr(va, pa, VM_MEMATTR_DEFAULT); 1925 } 1926 1927 /* 1928 * Extract the physical page address associated with the given kernel virtual 1929 * address. 1930 */ 1931 vm_paddr_t 1932 moea64_kextract(vm_offset_t va) 1933 { 1934 struct pvo_entry *pvo; 1935 vm_paddr_t pa; 1936 1937 /* 1938 * Shortcut the direct-mapped case when applicable. We never put 1939 * anything but 1:1 (or 62-bit aliased) mappings below 1940 * VM_MIN_KERNEL_ADDRESS. 1941 */ 1942 if (va < VM_MIN_KERNEL_ADDRESS) 1943 return (va & ~DMAP_BASE_ADDRESS); 1944 1945 PMAP_LOCK(kernel_pmap); 1946 pvo = moea64_pvo_find_va(kernel_pmap, va); 1947 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR, 1948 va)); 1949 pa = PVO_PADDR(pvo) | (va - PVO_VADDR(pvo)); 1950 PMAP_UNLOCK(kernel_pmap); 1951 return (pa); 1952 } 1953 1954 /* 1955 * Remove a wired page from kernel virtual address space. 1956 */ 1957 void 1958 moea64_kremove(vm_offset_t va) 1959 { 1960 moea64_remove(kernel_pmap, va, va + PAGE_SIZE); 1961 } 1962 1963 /* 1964 * Provide a kernel pointer corresponding to a given userland pointer. 1965 * The returned pointer is valid until the next time this function is 1966 * called in this thread. This is used internally in copyin/copyout. 1967 */ 1968 static int 1969 moea64_map_user_ptr(pmap_t pm, volatile const void *uaddr, 1970 void **kaddr, size_t ulen, size_t *klen) 1971 { 1972 size_t l; 1973 #ifdef __powerpc64__ 1974 struct slb *slb; 1975 #endif 1976 register_t slbv; 1977 1978 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK); 1979 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr); 1980 if (l > ulen) 1981 l = ulen; 1982 if (klen) 1983 *klen = l; 1984 else if (l != ulen) 1985 return (EFAULT); 1986 1987 #ifdef __powerpc64__ 1988 /* Try lockless look-up first */ 1989 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr); 1990 1991 if (slb == NULL) { 1992 /* If it isn't there, we need to pre-fault the VSID */ 1993 PMAP_LOCK(pm); 1994 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT; 1995 PMAP_UNLOCK(pm); 1996 } else { 1997 slbv = slb->slbv; 1998 } 1999 2000 /* Mark segment no-execute */ 2001 slbv |= SLBV_N; 2002 #else 2003 slbv = va_to_vsid(pm, (vm_offset_t)uaddr); 2004 2005 /* Mark segment no-execute */ 2006 slbv |= SR_N; 2007 #endif 2008 2009 /* If we have already set this VSID, we can just return */ 2010 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv) 2011 return (0); 2012 2013 __asm __volatile("isync"); 2014 curthread->td_pcb->pcb_cpu.aim.usr_segm = 2015 (uintptr_t)uaddr >> ADDR_SR_SHFT; 2016 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv; 2017 #ifdef __powerpc64__ 2018 __asm __volatile ("slbie %0; slbmte %1, %2; isync" :: 2019 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE)); 2020 #else 2021 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv)); 2022 #endif 2023 2024 return (0); 2025 } 2026 2027 /* 2028 * Figure out where a given kernel pointer (usually in a fault) points 2029 * to from the VM's perspective, potentially remapping into userland's 2030 * address space. 2031 */ 2032 static int 2033 moea64_decode_kernel_ptr(vm_offset_t addr, int *is_user, 2034 vm_offset_t *decoded_addr) 2035 { 2036 vm_offset_t user_sr; 2037 2038 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) { 2039 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm; 2040 addr &= ADDR_PIDX | ADDR_POFF; 2041 addr |= user_sr << ADDR_SR_SHFT; 2042 *decoded_addr = addr; 2043 *is_user = 1; 2044 } else { 2045 *decoded_addr = addr; 2046 *is_user = 0; 2047 } 2048 2049 return (0); 2050 } 2051 2052 /* 2053 * Map a range of physical addresses into kernel virtual address space. 2054 * 2055 * The value passed in *virt is a suggested virtual address for the mapping. 2056 * Architectures which can support a direct-mapped physical to virtual region 2057 * can return the appropriate address within that region, leaving '*virt' 2058 * unchanged. Other architectures should map the pages starting at '*virt' and 2059 * update '*virt' with the first usable address after the mapped region. 2060 */ 2061 vm_offset_t 2062 moea64_map(vm_offset_t *virt, vm_paddr_t pa_start, 2063 vm_paddr_t pa_end, int prot) 2064 { 2065 vm_offset_t sva, va; 2066 2067 if (hw_direct_map) { 2068 /* 2069 * Check if every page in the region is covered by the direct 2070 * map. The direct map covers all of physical memory. Use 2071 * moea64_calc_wimg() as a shortcut to see if the page is in 2072 * physical memory as a way to see if the direct map covers it. 2073 */ 2074 for (va = pa_start; va < pa_end; va += PAGE_SIZE) 2075 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M) 2076 break; 2077 if (va == pa_end) 2078 return (PHYS_TO_DMAP(pa_start)); 2079 } 2080 sva = *virt; 2081 va = sva; 2082 /* XXX respect prot argument */ 2083 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE) 2084 moea64_kenter(va, pa_start); 2085 *virt = va; 2086 2087 return (sva); 2088 } 2089 2090 /* 2091 * Returns true if the pmap's pv is one of the first 2092 * 16 pvs linked to from this page. This count may 2093 * be changed upwards or downwards in the future; it 2094 * is only necessary that true be returned for a small 2095 * subset of pmaps for proper page aging. 2096 */ 2097 boolean_t 2098 moea64_page_exists_quick(pmap_t pmap, vm_page_t m) 2099 { 2100 int loops; 2101 struct pvo_entry *pvo; 2102 boolean_t rv; 2103 2104 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2105 ("moea64_page_exists_quick: page %p is not managed", m)); 2106 loops = 0; 2107 rv = FALSE; 2108 PV_PAGE_LOCK(m); 2109 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2110 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) { 2111 rv = TRUE; 2112 break; 2113 } 2114 if (++loops >= 16) 2115 break; 2116 } 2117 PV_PAGE_UNLOCK(m); 2118 return (rv); 2119 } 2120 2121 void 2122 moea64_page_init(vm_page_t m) 2123 { 2124 2125 m->md.mdpg_attrs = 0; 2126 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT; 2127 LIST_INIT(&m->md.mdpg_pvoh); 2128 } 2129 2130 /* 2131 * Return the number of managed mappings to the given physical page 2132 * that are wired. 2133 */ 2134 int 2135 moea64_page_wired_mappings(vm_page_t m) 2136 { 2137 struct pvo_entry *pvo; 2138 int count; 2139 2140 count = 0; 2141 if ((m->oflags & VPO_UNMANAGED) != 0) 2142 return (count); 2143 PV_PAGE_LOCK(m); 2144 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) 2145 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED) 2146 count++; 2147 PV_PAGE_UNLOCK(m); 2148 return (count); 2149 } 2150 2151 static uintptr_t moea64_vsidcontext; 2152 2153 uintptr_t 2154 moea64_get_unique_vsid(void) { 2155 u_int entropy; 2156 register_t hash; 2157 uint32_t mask; 2158 int i; 2159 2160 entropy = 0; 2161 __asm __volatile("mftb %0" : "=r"(entropy)); 2162 2163 mtx_lock(&moea64_slb_mutex); 2164 for (i = 0; i < NVSIDS; i += VSID_NBPW) { 2165 u_int n; 2166 2167 /* 2168 * Create a new value by mutiplying by a prime and adding in 2169 * entropy from the timebase register. This is to make the 2170 * VSID more random so that the PT hash function collides 2171 * less often. (Note that the prime casues gcc to do shifts 2172 * instead of a multiply.) 2173 */ 2174 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy; 2175 hash = moea64_vsidcontext & (NVSIDS - 1); 2176 if (hash == 0) /* 0 is special, avoid it */ 2177 continue; 2178 n = hash >> 5; 2179 mask = 1 << (hash & (VSID_NBPW - 1)); 2180 hash = (moea64_vsidcontext & VSID_HASHMASK); 2181 if (moea64_vsid_bitmap[n] & mask) { /* collision? */ 2182 /* anything free in this bucket? */ 2183 if (moea64_vsid_bitmap[n] == 0xffffffff) { 2184 entropy = (moea64_vsidcontext >> 20); 2185 continue; 2186 } 2187 i = ffs(~moea64_vsid_bitmap[n]) - 1; 2188 mask = 1 << i; 2189 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW); 2190 hash |= i; 2191 } 2192 if (hash == VSID_VRMA) /* also special, avoid this too */ 2193 continue; 2194 KASSERT(!(moea64_vsid_bitmap[n] & mask), 2195 ("Allocating in-use VSID %#zx\n", hash)); 2196 moea64_vsid_bitmap[n] |= mask; 2197 mtx_unlock(&moea64_slb_mutex); 2198 return (hash); 2199 } 2200 2201 mtx_unlock(&moea64_slb_mutex); 2202 panic("%s: out of segments",__func__); 2203 } 2204 2205 #ifdef __powerpc64__ 2206 int 2207 moea64_pinit(pmap_t pmap) 2208 { 2209 2210 RB_INIT(&pmap->pmap_pvo); 2211 2212 pmap->pm_slb_tree_root = slb_alloc_tree(); 2213 pmap->pm_slb = slb_alloc_user_cache(); 2214 pmap->pm_slb_len = 0; 2215 2216 return (1); 2217 } 2218 #else 2219 int 2220 moea64_pinit(pmap_t pmap) 2221 { 2222 int i; 2223 uint32_t hash; 2224 2225 RB_INIT(&pmap->pmap_pvo); 2226 2227 if (pmap_bootstrapped) 2228 pmap->pmap_phys = (pmap_t)moea64_kextract((vm_offset_t)pmap); 2229 else 2230 pmap->pmap_phys = pmap; 2231 2232 /* 2233 * Allocate some segment registers for this pmap. 2234 */ 2235 hash = moea64_get_unique_vsid(); 2236 2237 for (i = 0; i < 16; i++) 2238 pmap->pm_sr[i] = VSID_MAKE(i, hash); 2239 2240 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0")); 2241 2242 return (1); 2243 } 2244 #endif 2245 2246 /* 2247 * Initialize the pmap associated with process 0. 2248 */ 2249 void 2250 moea64_pinit0(pmap_t pm) 2251 { 2252 2253 PMAP_LOCK_INIT(pm); 2254 moea64_pinit(pm); 2255 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 2256 } 2257 2258 /* 2259 * Set the physical protection on the specified range of this map as requested. 2260 */ 2261 static void 2262 moea64_pvo_protect( pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot) 2263 { 2264 struct vm_page *pg; 2265 vm_prot_t oldprot; 2266 int32_t refchg; 2267 2268 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2269 2270 /* 2271 * Change the protection of the page. 2272 */ 2273 oldprot = pvo->pvo_pte.prot; 2274 pvo->pvo_pte.prot = prot; 2275 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2276 2277 /* 2278 * If the PVO is in the page table, update mapping 2279 */ 2280 refchg = moea64_pte_replace(pvo, MOEA64_PTE_PROT_UPDATE); 2281 if (refchg < 0) 2282 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0; 2283 2284 if (pm != kernel_pmap && pg != NULL && 2285 (pg->a.flags & PGA_EXECUTABLE) == 0 && 2286 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) { 2287 if ((pg->oflags & VPO_UNMANAGED) == 0) 2288 vm_page_aflag_set(pg, PGA_EXECUTABLE); 2289 moea64_syncicache(pm, PVO_VADDR(pvo), 2290 PVO_PADDR(pvo), PAGE_SIZE); 2291 } 2292 2293 /* 2294 * Update vm about the REF/CHG bits if the page is managed and we have 2295 * removed write access. 2296 */ 2297 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) && 2298 (oldprot & VM_PROT_WRITE)) { 2299 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2300 if (refchg & LPTE_CHG) 2301 vm_page_dirty(pg); 2302 if (refchg & LPTE_REF) 2303 vm_page_aflag_set(pg, PGA_REFERENCED); 2304 } 2305 } 2306 2307 void 2308 moea64_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, 2309 vm_prot_t prot) 2310 { 2311 struct pvo_entry *pvo, *tpvo, key; 2312 2313 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, 2314 sva, eva, prot); 2315 2316 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap, 2317 ("moea64_protect: non current pmap")); 2318 2319 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2320 moea64_remove(pm, sva, eva); 2321 return; 2322 } 2323 2324 PMAP_LOCK(pm); 2325 key.pvo_vaddr = sva; 2326 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2327 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2328 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2329 moea64_pvo_protect(pm, pvo, prot); 2330 } 2331 PMAP_UNLOCK(pm); 2332 } 2333 2334 /* 2335 * Map a list of wired pages into kernel virtual address space. This is 2336 * intended for temporary mappings which do not need page modification or 2337 * references recorded. Existing mappings in the region are overwritten. 2338 */ 2339 void 2340 moea64_qenter(vm_offset_t va, vm_page_t *m, int count) 2341 { 2342 while (count-- > 0) { 2343 moea64_kenter(va, VM_PAGE_TO_PHYS(*m)); 2344 va += PAGE_SIZE; 2345 m++; 2346 } 2347 } 2348 2349 /* 2350 * Remove page mappings from kernel virtual address space. Intended for 2351 * temporary mappings entered by moea64_qenter. 2352 */ 2353 void 2354 moea64_qremove(vm_offset_t va, int count) 2355 { 2356 while (count-- > 0) { 2357 moea64_kremove(va); 2358 va += PAGE_SIZE; 2359 } 2360 } 2361 2362 void 2363 moea64_release_vsid(uint64_t vsid) 2364 { 2365 int idx, mask; 2366 2367 mtx_lock(&moea64_slb_mutex); 2368 idx = vsid & (NVSIDS-1); 2369 mask = 1 << (idx % VSID_NBPW); 2370 idx /= VSID_NBPW; 2371 KASSERT(moea64_vsid_bitmap[idx] & mask, 2372 ("Freeing unallocated VSID %#jx", vsid)); 2373 moea64_vsid_bitmap[idx] &= ~mask; 2374 mtx_unlock(&moea64_slb_mutex); 2375 } 2376 2377 2378 void 2379 moea64_release(pmap_t pmap) 2380 { 2381 2382 /* 2383 * Free segment registers' VSIDs 2384 */ 2385 #ifdef __powerpc64__ 2386 slb_free_tree(pmap); 2387 slb_free_user_cache(pmap->pm_slb); 2388 #else 2389 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0")); 2390 2391 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0])); 2392 #endif 2393 } 2394 2395 /* 2396 * Remove all pages mapped by the specified pmap 2397 */ 2398 void 2399 moea64_remove_pages(pmap_t pm) 2400 { 2401 struct pvo_entry *pvo, *tpvo; 2402 struct pvo_dlist tofree; 2403 2404 SLIST_INIT(&tofree); 2405 2406 PMAP_LOCK(pm); 2407 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) { 2408 if (pvo->pvo_vaddr & PVO_WIRED) 2409 continue; 2410 2411 /* 2412 * For locking reasons, remove this from the page table and 2413 * pmap, but save delinking from the vm_page for a second 2414 * pass 2415 */ 2416 moea64_pvo_remove_from_pmap(pvo); 2417 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2418 } 2419 PMAP_UNLOCK(pm); 2420 2421 while (!SLIST_EMPTY(&tofree)) { 2422 pvo = SLIST_FIRST(&tofree); 2423 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2424 moea64_pvo_remove_from_page(pvo); 2425 free_pvo_entry(pvo); 2426 } 2427 } 2428 2429 /* 2430 * Remove the given range of addresses from the specified map. 2431 */ 2432 void 2433 moea64_remove(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 2434 { 2435 struct pvo_entry *pvo, *tpvo, key; 2436 struct pvo_dlist tofree; 2437 2438 /* 2439 * Perform an unsynchronized read. This is, however, safe. 2440 */ 2441 if (pm->pm_stats.resident_count == 0) 2442 return; 2443 2444 key.pvo_vaddr = sva; 2445 2446 SLIST_INIT(&tofree); 2447 2448 PMAP_LOCK(pm); 2449 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key); 2450 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) { 2451 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo); 2452 2453 /* 2454 * For locking reasons, remove this from the page table and 2455 * pmap, but save delinking from the vm_page for a second 2456 * pass 2457 */ 2458 moea64_pvo_remove_from_pmap(pvo); 2459 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink); 2460 } 2461 PMAP_UNLOCK(pm); 2462 2463 while (!SLIST_EMPTY(&tofree)) { 2464 pvo = SLIST_FIRST(&tofree); 2465 SLIST_REMOVE_HEAD(&tofree, pvo_dlink); 2466 moea64_pvo_remove_from_page(pvo); 2467 free_pvo_entry(pvo); 2468 } 2469 } 2470 2471 /* 2472 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove() 2473 * will reflect changes in pte's back to the vm_page. 2474 */ 2475 void 2476 moea64_remove_all(vm_page_t m) 2477 { 2478 struct pvo_entry *pvo, *next_pvo; 2479 struct pvo_head freequeue; 2480 int wasdead; 2481 pmap_t pmap; 2482 2483 LIST_INIT(&freequeue); 2484 2485 PV_PAGE_LOCK(m); 2486 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) { 2487 pmap = pvo->pvo_pmap; 2488 PMAP_LOCK(pmap); 2489 wasdead = (pvo->pvo_vaddr & PVO_DEAD); 2490 if (!wasdead) 2491 moea64_pvo_remove_from_pmap(pvo); 2492 moea64_pvo_remove_from_page_locked(pvo, m); 2493 if (!wasdead) 2494 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink); 2495 PMAP_UNLOCK(pmap); 2496 2497 } 2498 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings")); 2499 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable")); 2500 PV_PAGE_UNLOCK(m); 2501 2502 /* Clean up UMA allocations */ 2503 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo) 2504 free_pvo_entry(pvo); 2505 } 2506 2507 /* 2508 * Allocate a physical page of memory directly from the phys_avail map. 2509 * Can only be called from moea64_bootstrap before avail start and end are 2510 * calculated. 2511 */ 2512 vm_offset_t 2513 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align) 2514 { 2515 vm_offset_t s, e; 2516 int i, j; 2517 2518 size = round_page(size); 2519 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 2520 if (align != 0) 2521 s = roundup2(phys_avail[i], align); 2522 else 2523 s = phys_avail[i]; 2524 e = s + size; 2525 2526 if (s < phys_avail[i] || e > phys_avail[i + 1]) 2527 continue; 2528 2529 if (s + size > platform_real_maxaddr()) 2530 continue; 2531 2532 if (s == phys_avail[i]) { 2533 phys_avail[i] += size; 2534 } else if (e == phys_avail[i + 1]) { 2535 phys_avail[i + 1] -= size; 2536 } else { 2537 for (j = phys_avail_count * 2; j > i; j -= 2) { 2538 phys_avail[j] = phys_avail[j - 2]; 2539 phys_avail[j + 1] = phys_avail[j - 1]; 2540 } 2541 2542 phys_avail[i + 3] = phys_avail[i + 1]; 2543 phys_avail[i + 1] = s; 2544 phys_avail[i + 2] = e; 2545 phys_avail_count++; 2546 } 2547 2548 return (s); 2549 } 2550 panic("moea64_bootstrap_alloc: could not allocate memory"); 2551 } 2552 2553 static int 2554 moea64_pvo_enter(struct pvo_entry *pvo, struct pvo_head *pvo_head, 2555 struct pvo_entry **oldpvop) 2556 { 2557 struct pvo_entry *old_pvo; 2558 int err; 2559 2560 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2561 2562 STAT_MOEA64(moea64_pvo_enter_calls++); 2563 2564 /* 2565 * Add to pmap list 2566 */ 2567 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2568 2569 if (old_pvo != NULL) { 2570 if (oldpvop != NULL) 2571 *oldpvop = old_pvo; 2572 return (EEXIST); 2573 } 2574 2575 if (pvo_head != NULL) { 2576 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink); 2577 } 2578 2579 if (pvo->pvo_vaddr & PVO_WIRED) 2580 pvo->pvo_pmap->pm_stats.wired_count++; 2581 pvo->pvo_pmap->pm_stats.resident_count++; 2582 2583 /* 2584 * Insert it into the hardware page table 2585 */ 2586 err = moea64_pte_insert(pvo); 2587 if (err != 0) { 2588 panic("moea64_pvo_enter: overflow"); 2589 } 2590 2591 STAT_MOEA64(moea64_pvo_entries++); 2592 2593 if (pvo->pvo_pmap == kernel_pmap) 2594 isync(); 2595 2596 #ifdef __powerpc64__ 2597 /* 2598 * Make sure all our bootstrap mappings are in the SLB as soon 2599 * as virtual memory is switched on. 2600 */ 2601 if (!pmap_bootstrapped) 2602 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo), 2603 pvo->pvo_vaddr & PVO_LARGE); 2604 #endif 2605 2606 return (0); 2607 } 2608 2609 static void 2610 moea64_pvo_remove_from_pmap(struct pvo_entry *pvo) 2611 { 2612 struct vm_page *pg; 2613 int32_t refchg; 2614 2615 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap")); 2616 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED); 2617 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO")); 2618 2619 /* 2620 * If there is an active pte entry, we need to deactivate it 2621 */ 2622 refchg = moea64_pte_unset(pvo); 2623 if (refchg < 0) { 2624 /* 2625 * If it was evicted from the page table, be pessimistic and 2626 * dirty the page. 2627 */ 2628 if (pvo->pvo_pte.prot & VM_PROT_WRITE) 2629 refchg = LPTE_CHG; 2630 else 2631 refchg = 0; 2632 } 2633 2634 /* 2635 * Update our statistics. 2636 */ 2637 pvo->pvo_pmap->pm_stats.resident_count--; 2638 if (pvo->pvo_vaddr & PVO_WIRED) 2639 pvo->pvo_pmap->pm_stats.wired_count--; 2640 2641 /* 2642 * Remove this PVO from the pmap list. 2643 */ 2644 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo); 2645 2646 /* 2647 * Mark this for the next sweep 2648 */ 2649 pvo->pvo_vaddr |= PVO_DEAD; 2650 2651 /* Send RC bits to VM */ 2652 if ((pvo->pvo_vaddr & PVO_MANAGED) && 2653 (pvo->pvo_pte.prot & VM_PROT_WRITE)) { 2654 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2655 if (pg != NULL) { 2656 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs); 2657 if (refchg & LPTE_CHG) 2658 vm_page_dirty(pg); 2659 if (refchg & LPTE_REF) 2660 vm_page_aflag_set(pg, PGA_REFERENCED); 2661 } 2662 } 2663 } 2664 2665 static inline void 2666 moea64_pvo_remove_from_page_locked(struct pvo_entry *pvo, 2667 vm_page_t m) 2668 { 2669 2670 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page")); 2671 2672 /* Use NULL pmaps as a sentinel for races in page deletion */ 2673 if (pvo->pvo_pmap == NULL) 2674 return; 2675 pvo->pvo_pmap = NULL; 2676 2677 /* 2678 * Update vm about page writeability/executability if managed 2679 */ 2680 PV_LOCKASSERT(PVO_PADDR(pvo)); 2681 if (pvo->pvo_vaddr & PVO_MANAGED) { 2682 if (m != NULL) { 2683 LIST_REMOVE(pvo, pvo_vlink); 2684 if (LIST_EMPTY(vm_page_to_pvoh(m))) 2685 vm_page_aflag_clear(m, 2686 PGA_WRITEABLE | PGA_EXECUTABLE); 2687 } 2688 } 2689 2690 STAT_MOEA64(moea64_pvo_entries--); 2691 STAT_MOEA64(moea64_pvo_remove_calls++); 2692 } 2693 2694 static void 2695 moea64_pvo_remove_from_page(struct pvo_entry *pvo) 2696 { 2697 vm_page_t pg = NULL; 2698 2699 if (pvo->pvo_vaddr & PVO_MANAGED) 2700 pg = PHYS_TO_VM_PAGE(PVO_PADDR(pvo)); 2701 2702 PV_LOCK(PVO_PADDR(pvo)); 2703 moea64_pvo_remove_from_page_locked(pvo, pg); 2704 PV_UNLOCK(PVO_PADDR(pvo)); 2705 } 2706 2707 static struct pvo_entry * 2708 moea64_pvo_find_va(pmap_t pm, vm_offset_t va) 2709 { 2710 struct pvo_entry key; 2711 2712 PMAP_LOCK_ASSERT(pm, MA_OWNED); 2713 2714 key.pvo_vaddr = va & ~ADDR_POFF; 2715 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key)); 2716 } 2717 2718 static boolean_t 2719 moea64_query_bit(vm_page_t m, uint64_t ptebit) 2720 { 2721 struct pvo_entry *pvo; 2722 int64_t ret; 2723 boolean_t rv; 2724 2725 /* 2726 * See if this bit is stored in the page already. 2727 */ 2728 if (m->md.mdpg_attrs & ptebit) 2729 return (TRUE); 2730 2731 /* 2732 * Examine each PTE. Sync so that any pending REF/CHG bits are 2733 * flushed to the PTEs. 2734 */ 2735 rv = FALSE; 2736 powerpc_sync(); 2737 PV_PAGE_LOCK(m); 2738 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2739 ret = 0; 2740 2741 /* 2742 * See if this pvo has a valid PTE. if so, fetch the 2743 * REF/CHG bits from the valid PTE. If the appropriate 2744 * ptebit is set, return success. 2745 */ 2746 PMAP_LOCK(pvo->pvo_pmap); 2747 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2748 ret = moea64_pte_synch(pvo); 2749 PMAP_UNLOCK(pvo->pvo_pmap); 2750 2751 if (ret > 0) { 2752 atomic_set_32(&m->md.mdpg_attrs, 2753 ret & (LPTE_CHG | LPTE_REF)); 2754 if (ret & ptebit) { 2755 rv = TRUE; 2756 break; 2757 } 2758 } 2759 } 2760 PV_PAGE_UNLOCK(m); 2761 2762 return (rv); 2763 } 2764 2765 static u_int 2766 moea64_clear_bit(vm_page_t m, u_int64_t ptebit) 2767 { 2768 u_int count; 2769 struct pvo_entry *pvo; 2770 int64_t ret; 2771 2772 /* 2773 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so 2774 * we can reset the right ones). 2775 */ 2776 powerpc_sync(); 2777 2778 /* 2779 * For each pvo entry, clear the pte's ptebit. 2780 */ 2781 count = 0; 2782 PV_PAGE_LOCK(m); 2783 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) { 2784 ret = 0; 2785 2786 PMAP_LOCK(pvo->pvo_pmap); 2787 if (!(pvo->pvo_vaddr & PVO_DEAD)) 2788 ret = moea64_pte_clear(pvo, ptebit); 2789 PMAP_UNLOCK(pvo->pvo_pmap); 2790 2791 if (ret > 0 && (ret & ptebit)) 2792 count++; 2793 } 2794 atomic_clear_32(&m->md.mdpg_attrs, ptebit); 2795 PV_PAGE_UNLOCK(m); 2796 2797 return (count); 2798 } 2799 2800 boolean_t 2801 moea64_dev_direct_mapped(vm_paddr_t pa, vm_size_t size) 2802 { 2803 struct pvo_entry *pvo, key; 2804 vm_offset_t ppa; 2805 int error = 0; 2806 2807 if (hw_direct_map && mem_valid(pa, size) == 0) 2808 return (0); 2809 2810 PMAP_LOCK(kernel_pmap); 2811 ppa = pa & ~ADDR_POFF; 2812 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa; 2813 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key); 2814 ppa < pa + size; ppa += PAGE_SIZE, 2815 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) { 2816 if (pvo == NULL || PVO_PADDR(pvo) != ppa) { 2817 error = EFAULT; 2818 break; 2819 } 2820 } 2821 PMAP_UNLOCK(kernel_pmap); 2822 2823 return (error); 2824 } 2825 2826 /* 2827 * Map a set of physical memory pages into the kernel virtual 2828 * address space. Return a pointer to where it is mapped. This 2829 * routine is intended to be used for mapping device memory, 2830 * NOT real memory. 2831 */ 2832 void * 2833 moea64_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2834 { 2835 vm_offset_t va, tmpva, ppa, offset; 2836 2837 ppa = trunc_page(pa); 2838 offset = pa & PAGE_MASK; 2839 size = roundup2(offset + size, PAGE_SIZE); 2840 2841 va = kva_alloc(size); 2842 2843 if (!va) 2844 panic("moea64_mapdev: Couldn't alloc kernel virtual memory"); 2845 2846 for (tmpva = va; size > 0;) { 2847 moea64_kenter_attr(tmpva, ppa, ma); 2848 size -= PAGE_SIZE; 2849 tmpva += PAGE_SIZE; 2850 ppa += PAGE_SIZE; 2851 } 2852 2853 return ((void *)(va + offset)); 2854 } 2855 2856 void * 2857 moea64_mapdev(vm_paddr_t pa, vm_size_t size) 2858 { 2859 2860 return moea64_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT); 2861 } 2862 2863 void 2864 moea64_unmapdev(vm_offset_t va, vm_size_t size) 2865 { 2866 vm_offset_t base, offset; 2867 2868 base = trunc_page(va); 2869 offset = va & PAGE_MASK; 2870 size = roundup2(offset + size, PAGE_SIZE); 2871 2872 moea64_qremove(base, atop(size)); 2873 kva_free(base, size); 2874 } 2875 2876 void 2877 moea64_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2878 { 2879 struct pvo_entry *pvo; 2880 vm_offset_t lim; 2881 vm_paddr_t pa; 2882 vm_size_t len; 2883 2884 if (__predict_false(pm == NULL)) 2885 pm = &curthread->td_proc->p_vmspace->vm_pmap; 2886 2887 PMAP_LOCK(pm); 2888 while (sz > 0) { 2889 lim = round_page(va+1); 2890 len = MIN(lim - va, sz); 2891 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF); 2892 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) { 2893 pa = PVO_PADDR(pvo) | (va & ADDR_POFF); 2894 moea64_syncicache(pm, va, pa, len); 2895 } 2896 va += len; 2897 sz -= len; 2898 } 2899 PMAP_UNLOCK(pm); 2900 } 2901 2902 void 2903 moea64_dumpsys_map(vm_paddr_t pa, size_t sz, void **va) 2904 { 2905 2906 *va = (void *)(uintptr_t)pa; 2907 } 2908 2909 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2910 2911 void 2912 moea64_scan_init() 2913 { 2914 struct pvo_entry *pvo; 2915 vm_offset_t va; 2916 int i; 2917 2918 if (!do_minidump) { 2919 /* Initialize phys. segments for dumpsys(). */ 2920 memset(&dump_map, 0, sizeof(dump_map)); 2921 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz); 2922 for (i = 0; i < pregions_sz; i++) { 2923 dump_map[i].pa_start = pregions[i].mr_start; 2924 dump_map[i].pa_size = pregions[i].mr_size; 2925 } 2926 return; 2927 } 2928 2929 /* Virtual segments for minidumps: */ 2930 memset(&dump_map, 0, sizeof(dump_map)); 2931 2932 /* 1st: kernel .data and .bss. */ 2933 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2934 dump_map[0].pa_size = round_page((uintptr_t)_end) - 2935 dump_map[0].pa_start; 2936 2937 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2938 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr; 2939 dump_map[1].pa_size = round_page(msgbufp->msg_size); 2940 2941 /* 3rd: kernel VM. */ 2942 va = dump_map[1].pa_start + dump_map[1].pa_size; 2943 /* Find start of next chunk (from va). */ 2944 while (va < virtual_end) { 2945 /* Don't dump the buffer cache. */ 2946 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2947 va = kmi.buffer_eva; 2948 continue; 2949 } 2950 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2951 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD)) 2952 break; 2953 va += PAGE_SIZE; 2954 } 2955 if (va < virtual_end) { 2956 dump_map[2].pa_start = va; 2957 va += PAGE_SIZE; 2958 /* Find last page in chunk. */ 2959 while (va < virtual_end) { 2960 /* Don't run into the buffer cache. */ 2961 if (va == kmi.buffer_sva) 2962 break; 2963 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF); 2964 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD)) 2965 break; 2966 va += PAGE_SIZE; 2967 } 2968 dump_map[2].pa_size = va - dump_map[2].pa_start; 2969 } 2970 } 2971 2972 #ifdef __powerpc64__ 2973 2974 static size_t 2975 moea64_scan_pmap() 2976 { 2977 struct pvo_entry *pvo; 2978 vm_paddr_t pa, pa_end; 2979 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp; 2980 uint64_t lpsize; 2981 2982 lpsize = moea64_large_page_size; 2983 kstart = trunc_page((vm_offset_t)_etext); 2984 kend = round_page((vm_offset_t)_end); 2985 kstart_lp = kstart & ~moea64_large_page_mask; 2986 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask; 2987 2988 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, " 2989 "kstart_lp=0x%016lx, kend_lp=0x%016lx", 2990 kstart, kend, kstart_lp, kend_lp); 2991 2992 PMAP_LOCK(kernel_pmap); 2993 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) { 2994 va = pvo->pvo_vaddr; 2995 2996 if (va & PVO_DEAD) 2997 continue; 2998 2999 /* Skip DMAP (except kernel area) */ 3000 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) { 3001 if (va & PVO_LARGE) { 3002 pgva = va & ~moea64_large_page_mask; 3003 if (pgva < kstart_lp || pgva >= kend_lp) 3004 continue; 3005 } else { 3006 pgva = trunc_page(va); 3007 if (pgva < kstart || pgva >= kend) 3008 continue; 3009 } 3010 } 3011 3012 pa = PVO_PADDR(pvo); 3013 3014 if (va & PVO_LARGE) { 3015 pa_end = pa + lpsize; 3016 for (; pa < pa_end; pa += PAGE_SIZE) { 3017 if (is_dumpable(pa)) 3018 dump_add_page(pa); 3019 } 3020 } else { 3021 if (is_dumpable(pa)) 3022 dump_add_page(pa); 3023 } 3024 } 3025 PMAP_UNLOCK(kernel_pmap); 3026 3027 return (sizeof(struct lpte) * moea64_pteg_count * 8); 3028 } 3029 3030 static struct dump_context dump_ctx; 3031 3032 static void * 3033 moea64_dump_pmap_init(unsigned blkpgs) 3034 { 3035 dump_ctx.ptex = 0; 3036 dump_ctx.ptex_end = moea64_pteg_count * 8; 3037 dump_ctx.blksz = blkpgs * PAGE_SIZE; 3038 return (&dump_ctx); 3039 } 3040 3041 #else 3042 3043 static size_t 3044 moea64_scan_pmap() 3045 { 3046 return (0); 3047 } 3048 3049 static void * 3050 moea64_dump_pmap_init(unsigned blkpgs) 3051 { 3052 return (NULL); 3053 } 3054 3055 #endif 3056 3057 #ifdef __powerpc64__ 3058 static void 3059 moea64_map_range(vm_offset_t va, vm_paddr_t pa, vm_size_t npages) 3060 { 3061 3062 for (; npages > 0; --npages) { 3063 if (moea64_large_page_size != 0 && 3064 (pa & moea64_large_page_mask) == 0 && 3065 (va & moea64_large_page_mask) == 0 && 3066 npages >= (moea64_large_page_size >> PAGE_SHIFT)) { 3067 PMAP_LOCK(kernel_pmap); 3068 moea64_kenter_large(va, pa, 0, 0); 3069 PMAP_UNLOCK(kernel_pmap); 3070 pa += moea64_large_page_size; 3071 va += moea64_large_page_size; 3072 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1; 3073 } else { 3074 moea64_kenter(va, pa); 3075 pa += PAGE_SIZE; 3076 va += PAGE_SIZE; 3077 } 3078 } 3079 } 3080 3081 static void 3082 moea64_page_array_startup(long pages) 3083 { 3084 long dom_pages[MAXMEMDOM]; 3085 vm_paddr_t pa; 3086 vm_offset_t va, vm_page_base; 3087 vm_size_t needed, size; 3088 long page; 3089 int domain; 3090 int i; 3091 3092 vm_page_base = 0xd000000000000000ULL; 3093 3094 /* Short-circuit single-domain systems. */ 3095 if (vm_ndomains == 1) { 3096 size = round_page(pages * sizeof(struct vm_page)); 3097 pa = vm_phys_early_alloc(0, size); 3098 vm_page_base = moea64_map(&vm_page_base, 3099 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE); 3100 vm_page_array_size = pages; 3101 vm_page_array = (vm_page_t)vm_page_base; 3102 return; 3103 } 3104 3105 page = 0; 3106 for (i = 0; i < MAXMEMDOM; i++) 3107 dom_pages[i] = 0; 3108 3109 /* Now get the number of pages required per domain. */ 3110 for (i = 0; i < vm_phys_nsegs; i++) { 3111 domain = vm_phys_segs[i].domain; 3112 KASSERT(domain < MAXMEMDOM, 3113 ("Invalid vm_phys_segs NUMA domain %d!\n", domain)); 3114 /* Get size of vm_page_array needed for this segment. */ 3115 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start); 3116 dom_pages[domain] += size; 3117 } 3118 3119 for (i = 0; phys_avail[i + 1] != 0; i+= 2) { 3120 domain = _vm_phys_domain(phys_avail[i]); 3121 KASSERT(domain < MAXMEMDOM, 3122 ("Invalid phys_avail NUMA domain %d!\n", domain)); 3123 size = btoc(phys_avail[i + 1] - phys_avail[i]); 3124 dom_pages[domain] += size; 3125 } 3126 3127 /* 3128 * Map in chunks that can get us all 16MB pages. There will be some 3129 * overlap between domains, but that's acceptable for now. 3130 */ 3131 vm_page_array_size = 0; 3132 va = vm_page_base; 3133 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) { 3134 if (dom_pages[i] == 0) 3135 continue; 3136 size = ulmin(pages - vm_page_array_size, dom_pages[i]); 3137 size = round_page(size * sizeof(struct vm_page)); 3138 needed = size; 3139 size = roundup2(size, moea64_large_page_size); 3140 pa = vm_phys_early_alloc(i, size); 3141 vm_page_array_size += size / sizeof(struct vm_page); 3142 moea64_map_range(va, pa, size >> PAGE_SHIFT); 3143 /* Scoot up domain 0, to reduce the domain page overlap. */ 3144 if (i == 0) 3145 vm_page_base += size - needed; 3146 va += size; 3147 } 3148 vm_page_array = (vm_page_t)vm_page_base; 3149 vm_page_array_size = pages; 3150 } 3151 #endif 3152 3153 static int64_t 3154 moea64_null_method(void) 3155 { 3156 return (0); 3157 } 3158 3159 static int64_t moea64_pte_replace_default(struct pvo_entry *pvo, int flags) 3160 { 3161 int64_t refchg; 3162 3163 refchg = moea64_pte_unset(pvo); 3164 moea64_pte_insert(pvo); 3165 3166 return (refchg); 3167 } 3168 3169 struct moea64_funcs *moea64_ops; 3170 3171 #define DEFINE_OEA64_IFUNC(ret, func, args, def) \ 3172 DEFINE_IFUNC(, ret, moea64_##func, args) { \ 3173 moea64_##func##_t f; \ 3174 if (moea64_ops == NULL) \ 3175 return ((moea64_##func##_t)def); \ 3176 f = moea64_ops->func; \ 3177 return (f != NULL ? f : (moea64_##func##_t)def);\ 3178 } 3179 3180 DEFINE_OEA64_IFUNC(int64_t, pte_replace, (struct pvo_entry *, int), 3181 moea64_pte_replace_default) 3182 DEFINE_OEA64_IFUNC(int64_t, pte_insert, (struct pvo_entry *), moea64_null_method) 3183 DEFINE_OEA64_IFUNC(int64_t, pte_unset, (struct pvo_entry *), moea64_null_method) 3184 DEFINE_OEA64_IFUNC(int64_t, pte_clear, (struct pvo_entry *, uint64_t), 3185 moea64_null_method) 3186 DEFINE_OEA64_IFUNC(int64_t, pte_synch, (struct pvo_entry *), moea64_null_method) 3187