112640815SMarcel Moolenaar /*- 212640815SMarcel Moolenaar * Copyright (c) 2008 Marcel Moolenaar 312640815SMarcel Moolenaar * All rights reserved. 412640815SMarcel Moolenaar * 512640815SMarcel Moolenaar * Redistribution and use in source and binary forms, with or without 612640815SMarcel Moolenaar * modification, are permitted provided that the following conditions 712640815SMarcel Moolenaar * are met: 812640815SMarcel Moolenaar * 912640815SMarcel Moolenaar * 1. Redistributions of source code must retain the above copyright 1012640815SMarcel Moolenaar * notice, this list of conditions and the following disclaimer. 1112640815SMarcel Moolenaar * 2. Redistributions in binary form must reproduce the above copyright 1212640815SMarcel Moolenaar * notice, this list of conditions and the following disclaimer in the 1312640815SMarcel Moolenaar * documentation and/or other materials provided with the distribution. 1412640815SMarcel Moolenaar * 1512640815SMarcel Moolenaar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1612640815SMarcel Moolenaar * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1712640815SMarcel Moolenaar * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1812640815SMarcel Moolenaar * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1912640815SMarcel Moolenaar * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2012640815SMarcel Moolenaar * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2112640815SMarcel Moolenaar * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2212640815SMarcel Moolenaar * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2312640815SMarcel Moolenaar * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2412640815SMarcel Moolenaar * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2512640815SMarcel Moolenaar */ 2612640815SMarcel Moolenaar 2712640815SMarcel Moolenaar #include <sys/cdefs.h> 2812640815SMarcel Moolenaar __FBSDID("$FreeBSD$"); 2912640815SMarcel Moolenaar 3012640815SMarcel Moolenaar #include <sys/param.h> 3112640815SMarcel Moolenaar #include <sys/systm.h> 3212640815SMarcel Moolenaar #include <sys/kernel.h> 3312640815SMarcel Moolenaar #include <sys/bus.h> 3412640815SMarcel Moolenaar #include <sys/pcpu.h> 3512640815SMarcel Moolenaar #include <sys/proc.h> 3612640815SMarcel Moolenaar #include <sys/smp.h> 3712640815SMarcel Moolenaar 3812640815SMarcel Moolenaar #include <machine/bus.h> 3912640815SMarcel Moolenaar #include <machine/cpu.h> 4012640815SMarcel Moolenaar #include <machine/hid.h> 4112640815SMarcel Moolenaar #include <machine/intr_machdep.h> 4212640815SMarcel Moolenaar #include <machine/pcb.h> 4312640815SMarcel Moolenaar #include <machine/psl.h> 4412640815SMarcel Moolenaar #include <machine/smp.h> 4512640815SMarcel Moolenaar #include <machine/spr.h> 4612640815SMarcel Moolenaar #include <machine/trap_aim.h> 4712640815SMarcel Moolenaar 4812640815SMarcel Moolenaar #include <dev/ofw/openfirm.h> 4912640815SMarcel Moolenaar #include <machine/ofw_machdep.h> 5012640815SMarcel Moolenaar 5112640815SMarcel Moolenaar void *ap_pcpu; 5212640815SMarcel Moolenaar 53dab90f68SNathan Whitehorn static register_t bsp_state[8] __aligned(8); 54999987e5SNathan Whitehorn 55999987e5SNathan Whitehorn static void cpudep_save_config(void *dummy); 56999987e5SNathan Whitehorn SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL); 57999987e5SNathan Whitehorn 58c3e289e1SNathan Whitehorn void 59c3e289e1SNathan Whitehorn cpudep_ap_early_bootstrap(void) 60c3e289e1SNathan Whitehorn { 61c3e289e1SNathan Whitehorn register_t reg; 62c3e289e1SNathan Whitehorn 63c3e289e1SNathan Whitehorn __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu)); 64c3e289e1SNathan Whitehorn powerpc_sync(); 65c3e289e1SNathan Whitehorn 66c3e289e1SNathan Whitehorn switch (mfpvr() >> 16) { 67c3e289e1SNathan Whitehorn case IBM970: 68c3e289e1SNathan Whitehorn case IBM970FX: 69c3e289e1SNathan Whitehorn case IBM970MP: 70c3e289e1SNathan Whitehorn /* Restore HID4 and HID5, which are necessary for the MMU */ 71c3e289e1SNathan Whitehorn 72c3e289e1SNathan Whitehorn __asm __volatile("ld %0, 16(%2); sync; isync; \ 73c3e289e1SNathan Whitehorn mtspr %1, %0; sync; isync;" 74c3e289e1SNathan Whitehorn : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); 75c3e289e1SNathan Whitehorn __asm __volatile("ld %0, 24(%2); sync; isync; \ 76c3e289e1SNathan Whitehorn mtspr %1, %0; sync; isync;" 77c3e289e1SNathan Whitehorn : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); 78c3e289e1SNathan Whitehorn powerpc_sync(); 79c3e289e1SNathan Whitehorn break; 80c3e289e1SNathan Whitehorn } 81c3e289e1SNathan Whitehorn } 82c3e289e1SNathan Whitehorn 83999987e5SNathan Whitehorn uintptr_t 84999987e5SNathan Whitehorn cpudep_ap_bootstrap(void) 85999987e5SNathan Whitehorn { 86999987e5SNathan Whitehorn register_t msr, sp; 87999987e5SNathan Whitehorn 88999987e5SNathan Whitehorn msr = PSL_KERNSET & ~PSL_EE; 89999987e5SNathan Whitehorn mtmsr(msr); 90999987e5SNathan Whitehorn isync(); 91999987e5SNathan Whitehorn 92999987e5SNathan Whitehorn pcpup->pc_curthread = pcpup->pc_idlethread; 93999987e5SNathan Whitehorn pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 94999987e5SNathan Whitehorn sp = pcpup->pc_curpcb->pcb_sp; 95999987e5SNathan Whitehorn 96999987e5SNathan Whitehorn return (sp); 97999987e5SNathan Whitehorn } 98999987e5SNathan Whitehorn 996e326900SMarcel Moolenaar static register_t 100ed6e65a2SNathan Whitehorn mpc74xx_l2_enable(register_t l2cr_config) 1016e326900SMarcel Moolenaar { 102ed6e65a2SNathan Whitehorn register_t ccr, bit; 103ed6e65a2SNathan Whitehorn uint16_t vers; 104ed6e65a2SNathan Whitehorn 105ed6e65a2SNathan Whitehorn vers = mfpvr() >> 16; 106ed6e65a2SNathan Whitehorn switch (vers) { 107ed6e65a2SNathan Whitehorn case MPC7400: 108ed6e65a2SNathan Whitehorn case MPC7410: 109ed6e65a2SNathan Whitehorn bit = L2CR_L2IP; 110ed6e65a2SNathan Whitehorn break; 111ed6e65a2SNathan Whitehorn default: 112ed6e65a2SNathan Whitehorn bit = L2CR_L2I; 113ed6e65a2SNathan Whitehorn break; 114ed6e65a2SNathan Whitehorn } 1156e326900SMarcel Moolenaar 1166e326900SMarcel Moolenaar ccr = mfspr(SPR_L2CR); 1176e326900SMarcel Moolenaar if (ccr & L2CR_L2E) 1186e326900SMarcel Moolenaar return (ccr); 1196e326900SMarcel Moolenaar 1206e326900SMarcel Moolenaar /* Configure L2 cache. */ 1216e326900SMarcel Moolenaar ccr = l2cr_config & ~L2CR_L2E; 1226e326900SMarcel Moolenaar mtspr(SPR_L2CR, ccr | L2CR_L2I); 1236e326900SMarcel Moolenaar do { 1246e326900SMarcel Moolenaar ccr = mfspr(SPR_L2CR); 125ed6e65a2SNathan Whitehorn } while (ccr & bit); 1266e326900SMarcel Moolenaar powerpc_sync(); 1276e326900SMarcel Moolenaar mtspr(SPR_L2CR, l2cr_config); 1286e326900SMarcel Moolenaar powerpc_sync(); 1296e326900SMarcel Moolenaar 1306e326900SMarcel Moolenaar return (l2cr_config); 1316e326900SMarcel Moolenaar } 1326e326900SMarcel Moolenaar 1336e326900SMarcel Moolenaar static register_t 134999987e5SNathan Whitehorn mpc745x_l3_enable(register_t l3cr_config) 1356e326900SMarcel Moolenaar { 1366e326900SMarcel Moolenaar register_t ccr; 1376e326900SMarcel Moolenaar 1386e326900SMarcel Moolenaar ccr = mfspr(SPR_L3CR); 1396e326900SMarcel Moolenaar if (ccr & L3CR_L3E) 1406e326900SMarcel Moolenaar return (ccr); 1416e326900SMarcel Moolenaar 1426e326900SMarcel Moolenaar /* Configure L3 cache. */ 1436e326900SMarcel Moolenaar ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN); 1446e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr); 1456e326900SMarcel Moolenaar ccr |= 0x4000000; /* Magic, but documented. */ 1466e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr); 1476e326900SMarcel Moolenaar ccr |= L3CR_L3CLKEN; 1486e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr); 1496e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr | L3CR_L3I); 1506e326900SMarcel Moolenaar while (mfspr(SPR_L3CR) & L3CR_L3I) 1516e326900SMarcel Moolenaar ; 1526e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN); 1536e326900SMarcel Moolenaar powerpc_sync(); 1546e326900SMarcel Moolenaar DELAY(100); 1556e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr); 1566e326900SMarcel Moolenaar powerpc_sync(); 1576e326900SMarcel Moolenaar DELAY(100); 1586e326900SMarcel Moolenaar ccr |= L3CR_L3E; 1596e326900SMarcel Moolenaar mtspr(SPR_L3CR, ccr); 1606e326900SMarcel Moolenaar powerpc_sync(); 1616e326900SMarcel Moolenaar 1626e326900SMarcel Moolenaar return(ccr); 1636e326900SMarcel Moolenaar } 1646e326900SMarcel Moolenaar 1656e326900SMarcel Moolenaar static register_t 166ed6e65a2SNathan Whitehorn mpc74xx_l1d_enable(void) 1676e326900SMarcel Moolenaar { 1686e326900SMarcel Moolenaar register_t hid; 1696e326900SMarcel Moolenaar 1706e326900SMarcel Moolenaar hid = mfspr(SPR_HID0); 1716e326900SMarcel Moolenaar if (hid & HID0_DCE) 1726e326900SMarcel Moolenaar return (hid); 1736e326900SMarcel Moolenaar 1746e326900SMarcel Moolenaar /* Enable L1 D-cache */ 1756e326900SMarcel Moolenaar hid |= HID0_DCE; 1766e326900SMarcel Moolenaar powerpc_sync(); 1776e326900SMarcel Moolenaar mtspr(SPR_HID0, hid | HID0_DCFI); 1786e326900SMarcel Moolenaar powerpc_sync(); 1796e326900SMarcel Moolenaar 1806e326900SMarcel Moolenaar return (hid); 1816e326900SMarcel Moolenaar } 1826e326900SMarcel Moolenaar 1836e326900SMarcel Moolenaar static register_t 184ed6e65a2SNathan Whitehorn mpc74xx_l1i_enable(void) 1856e326900SMarcel Moolenaar { 1866e326900SMarcel Moolenaar register_t hid; 1876e326900SMarcel Moolenaar 1886e326900SMarcel Moolenaar hid = mfspr(SPR_HID0); 1896e326900SMarcel Moolenaar if (hid & HID0_ICE) 1906e326900SMarcel Moolenaar return (hid); 1916e326900SMarcel Moolenaar 1926e326900SMarcel Moolenaar /* Enable L1 I-cache */ 1936e326900SMarcel Moolenaar hid |= HID0_ICE; 1946e326900SMarcel Moolenaar isync(); 1956e326900SMarcel Moolenaar mtspr(SPR_HID0, hid | HID0_ICFI); 1966e326900SMarcel Moolenaar isync(); 1976e326900SMarcel Moolenaar 1986e326900SMarcel Moolenaar return (hid); 1996e326900SMarcel Moolenaar } 2006e326900SMarcel Moolenaar 201999987e5SNathan Whitehorn static void 202999987e5SNathan Whitehorn cpudep_save_config(void *dummy) 20312640815SMarcel Moolenaar { 204999987e5SNathan Whitehorn uint16_t vers; 2056e326900SMarcel Moolenaar 206999987e5SNathan Whitehorn vers = mfpvr() >> 16; 20712640815SMarcel Moolenaar 208999987e5SNathan Whitehorn switch(vers) { 209999987e5SNathan Whitehorn case IBM970: 210999987e5SNathan Whitehorn case IBM970FX: 211999987e5SNathan Whitehorn case IBM970MP: 212c3e289e1SNathan Whitehorn #ifdef __powerpc64__ 213c3e289e1SNathan Whitehorn bsp_state[0] = mfspr(SPR_HID0); 214c3e289e1SNathan Whitehorn bsp_state[1] = mfspr(SPR_HID1); 215c3e289e1SNathan Whitehorn bsp_state[2] = mfspr(SPR_HID4); 216c3e289e1SNathan Whitehorn bsp_state[3] = mfspr(SPR_HID5); 217c3e289e1SNathan Whitehorn #else 218999987e5SNathan Whitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 219999987e5SNathan Whitehorn : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0)); 220999987e5SNathan Whitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 221999987e5SNathan Whitehorn : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1)); 222999987e5SNathan Whitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 223999987e5SNathan Whitehorn : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4)); 224999987e5SNathan Whitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 225999987e5SNathan Whitehorn : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5)); 226c3e289e1SNathan Whitehorn #endif 227999987e5SNathan Whitehorn 228dab90f68SNathan Whitehorn powerpc_sync(); 229dab90f68SNathan Whitehorn 230999987e5SNathan Whitehorn break; 2312971d3bbSNathan Whitehorn case IBMCELLBE: 232cebdaa58SNathan Whitehorn #ifdef NOTYET /* Causes problems if in instruction stream on 970 */ 2332971d3bbSNathan Whitehorn if (mfmsr() & PSL_HV) { 2342971d3bbSNathan Whitehorn bsp_state[0] = mfspr(SPR_HID0); 2352971d3bbSNathan Whitehorn bsp_state[1] = mfspr(SPR_HID1); 2362971d3bbSNathan Whitehorn bsp_state[2] = mfspr(SPR_HID4); 2372971d3bbSNathan Whitehorn bsp_state[3] = mfspr(SPR_HID6); 2382971d3bbSNathan Whitehorn 2392971d3bbSNathan Whitehorn bsp_state[4] = mfspr(SPR_CELL_TSCR); 2402971d3bbSNathan Whitehorn } 241cebdaa58SNathan Whitehorn #endif 2422971d3bbSNathan Whitehorn 2432971d3bbSNathan Whitehorn bsp_state[5] = mfspr(SPR_CELL_TSRL); 2442971d3bbSNathan Whitehorn 2452971d3bbSNathan Whitehorn break; 246999987e5SNathan Whitehorn case MPC7450: 247999987e5SNathan Whitehorn case MPC7455: 248999987e5SNathan Whitehorn case MPC7457: 249999987e5SNathan Whitehorn /* Only MPC745x CPUs have an L3 cache. */ 250999987e5SNathan Whitehorn bsp_state[3] = mfspr(SPR_L3CR); 251999987e5SNathan Whitehorn 252999987e5SNathan Whitehorn /* Fallthrough */ 253999987e5SNathan Whitehorn case MPC7400: 254999987e5SNathan Whitehorn case MPC7410: 255999987e5SNathan Whitehorn case MPC7447A: 256999987e5SNathan Whitehorn case MPC7448: 257999987e5SNathan Whitehorn bsp_state[2] = mfspr(SPR_L2CR); 258999987e5SNathan Whitehorn bsp_state[1] = mfspr(SPR_HID1); 259999987e5SNathan Whitehorn bsp_state[0] = mfspr(SPR_HID0); 260999987e5SNathan Whitehorn break; 261999987e5SNathan Whitehorn } 262999987e5SNathan Whitehorn } 263999987e5SNathan Whitehorn 264999987e5SNathan Whitehorn void 265999987e5SNathan Whitehorn cpudep_ap_setup() 266999987e5SNathan Whitehorn { 267999987e5SNathan Whitehorn register_t reg; 268999987e5SNathan Whitehorn uint16_t vers; 269999987e5SNathan Whitehorn 270999987e5SNathan Whitehorn vers = mfpvr() >> 16; 271999987e5SNathan Whitehorn 272999987e5SNathan Whitehorn switch(vers) { 273999987e5SNathan Whitehorn case IBM970: 274999987e5SNathan Whitehorn case IBM970FX: 275999987e5SNathan Whitehorn case IBM970MP: 276999987e5SNathan Whitehorn /* Set HIOR to 0 */ 277999987e5SNathan Whitehorn __asm __volatile("mtspr 311,%0" :: "r"(0)); 2786e326900SMarcel Moolenaar powerpc_sync(); 27912640815SMarcel Moolenaar 280999987e5SNathan Whitehorn /* 281999987e5SNathan Whitehorn * The 970 has strange rules about how to update HID registers. 282999987e5SNathan Whitehorn * See Table 2-3, 970MP manual 283999987e5SNathan Whitehorn */ 284999987e5SNathan Whitehorn 285dab90f68SNathan Whitehorn __asm __volatile("mtasr %0; sync" :: "r"(0)); 286999987e5SNathan Whitehorn __asm __volatile(" \ 287999987e5SNathan Whitehorn ld %0,0(%2); \ 288dab90f68SNathan Whitehorn sync; isync; \ 289999987e5SNathan Whitehorn mtspr %1, %0; \ 290999987e5SNathan Whitehorn mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ 291dab90f68SNathan Whitehorn mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ 292dab90f68SNathan Whitehorn sync; isync" 293999987e5SNathan Whitehorn : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state)); 294dab90f68SNathan Whitehorn __asm __volatile("ld %0, 8(%2); sync; isync; \ 295dab90f68SNathan Whitehorn mtspr %1, %0; mtspr %1, %0; sync; isync" 296dab90f68SNathan Whitehorn : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state)); 297dab90f68SNathan Whitehorn __asm __volatile("ld %0, 16(%2); sync; isync; \ 298dab90f68SNathan Whitehorn mtspr %1, %0; sync; isync;" 299999987e5SNathan Whitehorn : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); 300dab90f68SNathan Whitehorn __asm __volatile("ld %0, 24(%2); sync; isync; \ 301dab90f68SNathan Whitehorn mtspr %1, %0; sync; isync;" 302999987e5SNathan Whitehorn : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); 303999987e5SNathan Whitehorn 304999987e5SNathan Whitehorn powerpc_sync(); 305999987e5SNathan Whitehorn break; 3062971d3bbSNathan Whitehorn case IBMCELLBE: 307cebdaa58SNathan Whitehorn #ifdef NOTYET /* Causes problems if in instruction stream on 970 */ 3082971d3bbSNathan Whitehorn if (mfmsr() & PSL_HV) { 3092971d3bbSNathan Whitehorn mtspr(SPR_HID0, bsp_state[0]); 3102971d3bbSNathan Whitehorn mtspr(SPR_HID1, bsp_state[1]); 3112971d3bbSNathan Whitehorn mtspr(SPR_HID4, bsp_state[2]); 3122971d3bbSNathan Whitehorn mtspr(SPR_HID6, bsp_state[3]); 3132971d3bbSNathan Whitehorn 3142971d3bbSNathan Whitehorn mtspr(SPR_CELL_TSCR, bsp_state[4]); 3152971d3bbSNathan Whitehorn } 316cebdaa58SNathan Whitehorn #endif 3172971d3bbSNathan Whitehorn 3182971d3bbSNathan Whitehorn mtspr(SPR_CELL_TSRL, bsp_state[5]); 3192971d3bbSNathan Whitehorn 3202971d3bbSNathan Whitehorn break; 321999987e5SNathan Whitehorn case MPC7450: 322999987e5SNathan Whitehorn case MPC7455: 323999987e5SNathan Whitehorn case MPC7457: 324999987e5SNathan Whitehorn /* Only MPC745x CPUs have an L3 cache. */ 325999987e5SNathan Whitehorn reg = mpc745x_l3_enable(bsp_state[3]); 326999987e5SNathan Whitehorn 327999987e5SNathan Whitehorn /* Fallthrough */ 328999987e5SNathan Whitehorn case MPC7400: 329999987e5SNathan Whitehorn case MPC7410: 330999987e5SNathan Whitehorn case MPC7447A: 331999987e5SNathan Whitehorn case MPC7448: 332999987e5SNathan Whitehorn /* XXX: Program the CPU ID into PIR */ 3336e326900SMarcel Moolenaar __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); 3346e326900SMarcel Moolenaar 3356e326900SMarcel Moolenaar powerpc_sync(); 33612640815SMarcel Moolenaar isync(); 33712640815SMarcel Moolenaar 338999987e5SNathan Whitehorn mtspr(SPR_HID0, bsp_state[0]); isync(); 339999987e5SNathan Whitehorn mtspr(SPR_HID1, bsp_state[1]); isync(); 3406e326900SMarcel Moolenaar 341ed6e65a2SNathan Whitehorn reg = mpc74xx_l2_enable(bsp_state[2]); 342ed6e65a2SNathan Whitehorn reg = mpc74xx_l1d_enable(); 343ed6e65a2SNathan Whitehorn reg = mpc74xx_l1i_enable(); 34412640815SMarcel Moolenaar 345999987e5SNathan Whitehorn break; 346999987e5SNathan Whitehorn default: 347999987e5SNathan Whitehorn printf("WARNING: Unknown CPU type. Cache performace may be " 348999987e5SNathan Whitehorn "suboptimal.\n"); 349999987e5SNathan Whitehorn break; 350999987e5SNathan Whitehorn } 35112640815SMarcel Moolenaar } 35212640815SMarcel Moolenaar 353