1aa6bc7dcSRafal Jaworowski /*-
24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause
371e3c308SPedro F. Giffuni *
4aa6bc7dcSRafal Jaworowski * Copyright (c) 2011-2012 Semihalf.
5aa6bc7dcSRafal Jaworowski * All rights reserved.
6aa6bc7dcSRafal Jaworowski *
7aa6bc7dcSRafal Jaworowski * Redistribution and use in source and binary forms, with or without
8aa6bc7dcSRafal Jaworowski * modification, are permitted provided that the following conditions
9aa6bc7dcSRafal Jaworowski * are met:
10aa6bc7dcSRafal Jaworowski * 1. Redistributions of source code must retain the above copyright
11aa6bc7dcSRafal Jaworowski * notice, this list of conditions and the following disclaimer.
12aa6bc7dcSRafal Jaworowski * 2. Redistributions in binary form must reproduce the above copyright
13aa6bc7dcSRafal Jaworowski * notice, this list of conditions and the following disclaimer in the
14aa6bc7dcSRafal Jaworowski * documentation and/or other materials provided with the distribution.
15aa6bc7dcSRafal Jaworowski *
16aa6bc7dcSRafal Jaworowski * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17aa6bc7dcSRafal Jaworowski * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18aa6bc7dcSRafal Jaworowski * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19aa6bc7dcSRafal Jaworowski * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20aa6bc7dcSRafal Jaworowski * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21aa6bc7dcSRafal Jaworowski * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22aa6bc7dcSRafal Jaworowski * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23aa6bc7dcSRafal Jaworowski * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24aa6bc7dcSRafal Jaworowski * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25aa6bc7dcSRafal Jaworowski * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26aa6bc7dcSRafal Jaworowski * SUCH DAMAGE.
27aa6bc7dcSRafal Jaworowski */
28aa6bc7dcSRafal Jaworowski
29aa6bc7dcSRafal Jaworowski #include <sys/cdefs.h>
30fdafd315SWarner Losh
31aa6bc7dcSRafal Jaworowski #include <sys/types.h>
323f068cbfSJustin Hibbits #include <sys/param.h>
333f068cbfSJustin Hibbits #include <sys/proc.h>
34aa6bc7dcSRafal Jaworowski #include <sys/reboot.h>
35aa6bc7dcSRafal Jaworowski
363f068cbfSJustin Hibbits #include <vm/vm.h>
373f068cbfSJustin Hibbits #include <vm/pmap.h>
383f068cbfSJustin Hibbits
39aa6bc7dcSRafal Jaworowski #include <machine/machdep.h>
40aa6bc7dcSRafal Jaworowski
41aa6bc7dcSRafal Jaworowski #include <dev/fdt/fdt_common.h>
42aa6bc7dcSRafal Jaworowski
43aa6bc7dcSRafal Jaworowski #include <powerpc/mpc85xx/mpc85xx.h>
44aa6bc7dcSRafal Jaworowski
45aa6bc7dcSRafal Jaworowski extern void dcache_enable(void);
46aa6bc7dcSRafal Jaworowski extern void dcache_inval(void);
47aa6bc7dcSRafal Jaworowski extern void icache_enable(void);
48aa6bc7dcSRafal Jaworowski extern void icache_inval(void);
49aa6bc7dcSRafal Jaworowski extern void l2cache_enable(void);
50aa6bc7dcSRafal Jaworowski extern void l2cache_inval(void);
513f068cbfSJustin Hibbits extern void bpred_enable(void);
52aa6bc7dcSRafal Jaworowski
53aa6bc7dcSRafal Jaworowski void
booke_enable_l1_cache(void)54aa6bc7dcSRafal Jaworowski booke_enable_l1_cache(void)
55aa6bc7dcSRafal Jaworowski {
56aa6bc7dcSRafal Jaworowski uint32_t csr;
57aa6bc7dcSRafal Jaworowski
58aa6bc7dcSRafal Jaworowski /* Enable D-cache if applicable */
59aa6bc7dcSRafal Jaworowski csr = mfspr(SPR_L1CSR0);
60aa6bc7dcSRafal Jaworowski if ((csr & L1CSR0_DCE) == 0) {
61aa6bc7dcSRafal Jaworowski dcache_inval();
62aa6bc7dcSRafal Jaworowski dcache_enable();
63aa6bc7dcSRafal Jaworowski }
64aa6bc7dcSRafal Jaworowski
65aa6bc7dcSRafal Jaworowski csr = mfspr(SPR_L1CSR0);
66aa6bc7dcSRafal Jaworowski if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
67aa6bc7dcSRafal Jaworowski printf("L1 D-cache %sabled\n",
68aa6bc7dcSRafal Jaworowski (csr & L1CSR0_DCE) ? "en" : "dis");
69aa6bc7dcSRafal Jaworowski
70aa6bc7dcSRafal Jaworowski /* Enable L1 I-cache if applicable. */
71aa6bc7dcSRafal Jaworowski csr = mfspr(SPR_L1CSR1);
72aa6bc7dcSRafal Jaworowski if ((csr & L1CSR1_ICE) == 0) {
73aa6bc7dcSRafal Jaworowski icache_inval();
74aa6bc7dcSRafal Jaworowski icache_enable();
75aa6bc7dcSRafal Jaworowski }
76aa6bc7dcSRafal Jaworowski
77aa6bc7dcSRafal Jaworowski csr = mfspr(SPR_L1CSR1);
78aa6bc7dcSRafal Jaworowski if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
79aa6bc7dcSRafal Jaworowski printf("L1 I-cache %sabled\n",
80aa6bc7dcSRafal Jaworowski (csr & L1CSR1_ICE) ? "en" : "dis");
81aa6bc7dcSRafal Jaworowski }
82aa6bc7dcSRafal Jaworowski
83aa6bc7dcSRafal Jaworowski void
booke_enable_l2_cache(void)84aa6bc7dcSRafal Jaworowski booke_enable_l2_cache(void)
85aa6bc7dcSRafal Jaworowski {
86aa6bc7dcSRafal Jaworowski uint32_t csr;
87aa6bc7dcSRafal Jaworowski
88aa6bc7dcSRafal Jaworowski /* Enable L2 cache on E500mc */
89aa6bc7dcSRafal Jaworowski if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
90aa6bc7dcSRafal Jaworowski (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
91aa6bc7dcSRafal Jaworowski csr = mfspr(SPR_L2CSR0);
928415f755SBrandon Bergren /*
938415f755SBrandon Bergren * Don't actually attempt to manipulate the L2 cache if
948415f755SBrandon Bergren * L2CFG0 is zero.
958415f755SBrandon Bergren *
968415f755SBrandon Bergren * Any chip with a working L2 cache will have a nonzero
978415f755SBrandon Bergren * L2CFG0, as it will have a nonzero L2CSIZE field.
988415f755SBrandon Bergren *
998415f755SBrandon Bergren * This fixes waiting forever for cache enable in qemu,
1008415f755SBrandon Bergren * which does not implement the L2 cache.
1018415f755SBrandon Bergren */
1028415f755SBrandon Bergren if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
103aa6bc7dcSRafal Jaworowski l2cache_inval();
104aa6bc7dcSRafal Jaworowski l2cache_enable();
105aa6bc7dcSRafal Jaworowski }
106aa6bc7dcSRafal Jaworowski
107aa6bc7dcSRafal Jaworowski csr = mfspr(SPR_L2CSR0);
108aa6bc7dcSRafal Jaworowski if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0)
109aa6bc7dcSRafal Jaworowski printf("L2 cache %sabled\n",
110aa6bc7dcSRafal Jaworowski (csr & L2CSR0_L2E) ? "en" : "dis");
111aa6bc7dcSRafal Jaworowski }
112aa6bc7dcSRafal Jaworowski }
113aa6bc7dcSRafal Jaworowski
114aa6bc7dcSRafal Jaworowski void
booke_enable_bpred(void)1153f068cbfSJustin Hibbits booke_enable_bpred(void)
116aa6bc7dcSRafal Jaworowski {
1173f068cbfSJustin Hibbits uint32_t csr;
118aa6bc7dcSRafal Jaworowski
1193f068cbfSJustin Hibbits bpred_enable();
1203f068cbfSJustin Hibbits csr = mfspr(SPR_BUCSR);
1213f068cbfSJustin Hibbits if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0)
1223f068cbfSJustin Hibbits printf("Branch Predictor %sabled\n",
1233f068cbfSJustin Hibbits (csr & BUCSR_BPEN) ? "en" : "dis");
124aa6bc7dcSRafal Jaworowski }
125aa6bc7dcSRafal Jaworowski
126aa6bc7dcSRafal Jaworowski void
booke_disable_l2_cache(void)127aa6bc7dcSRafal Jaworowski booke_disable_l2_cache(void)
128aa6bc7dcSRafal Jaworowski {
129aa6bc7dcSRafal Jaworowski }
13081962477SJustin Hibbits
13181962477SJustin Hibbits /* Return 0 on handled success, otherwise signal number. */
13281962477SJustin Hibbits int
cpu_machine_check(struct thread * td,struct trapframe * frame,int * ucode)13381962477SJustin Hibbits cpu_machine_check(struct thread *td, struct trapframe *frame, int *ucode)
13481962477SJustin Hibbits {
13581962477SJustin Hibbits
13681962477SJustin Hibbits *ucode = BUS_OBJERR;
13781962477SJustin Hibbits return (SIGBUS);
13881962477SJustin Hibbits }
139