1 /*- 2 * Copyright (c) 2011-2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/types.h> 31 #include <sys/reboot.h> 32 33 #include <machine/machdep.h> 34 35 #include <dev/fdt/fdt_common.h> 36 37 #include <powerpc/mpc85xx/mpc85xx.h> 38 39 extern void dcache_enable(void); 40 extern void dcache_inval(void); 41 extern void icache_enable(void); 42 extern void icache_inval(void); 43 extern void l2cache_enable(void); 44 extern void l2cache_inval(void); 45 46 void 47 booke_init_tlb(vm_paddr_t fdt_immr_pa) 48 { 49 50 /* Initialize TLB1 handling */ 51 tlb1_init(fdt_immr_pa); 52 } 53 54 void 55 booke_enable_l1_cache(void) 56 { 57 uint32_t csr; 58 59 /* Enable D-cache if applicable */ 60 csr = mfspr(SPR_L1CSR0); 61 if ((csr & L1CSR0_DCE) == 0) { 62 dcache_inval(); 63 dcache_enable(); 64 } 65 66 csr = mfspr(SPR_L1CSR0); 67 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) 68 printf("L1 D-cache %sabled\n", 69 (csr & L1CSR0_DCE) ? "en" : "dis"); 70 71 /* Enable L1 I-cache if applicable. */ 72 csr = mfspr(SPR_L1CSR1); 73 if ((csr & L1CSR1_ICE) == 0) { 74 icache_inval(); 75 icache_enable(); 76 } 77 78 csr = mfspr(SPR_L1CSR1); 79 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) 80 printf("L1 I-cache %sabled\n", 81 (csr & L1CSR1_ICE) ? "en" : "dis"); 82 } 83 84 #if 0 85 void 86 booke_enable_l2_cache(void) 87 { 88 uint32_t csr; 89 90 /* Enable L2 cache on E500mc */ 91 if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || 92 (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { 93 csr = mfspr(SPR_L2CSR0); 94 if ((csr & L2CSR0_L2E) == 0) { 95 l2cache_inval(); 96 l2cache_enable(); 97 } 98 99 csr = mfspr(SPR_L2CSR0); 100 if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) 101 printf("L2 cache %sabled\n", 102 (csr & L2CSR0_L2E) ? "en" : "dis"); 103 } 104 } 105 106 void 107 booke_enable_l3_cache(void) 108 { 109 uint32_t csr, size, ver; 110 111 /* Enable L3 CoreNet Platform Cache (CPC) */ 112 ver = SVR_VER(mfspr(SPR_SVR)); 113 if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 || 114 ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) { 115 csr = ccsr_read4(OCP85XX_CPC_CSR0); 116 if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { 117 l3cache_inval(); 118 l3cache_enable(); 119 } 120 121 csr = ccsr_read4(OCP85XX_CPC_CSR0); 122 if ((boothowto & RB_VERBOSE) != 0 || 123 (csr & OCP85XX_CPC_CSR0_CE) == 0) { 124 size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0)); 125 printf("L3 Corenet Platform Cache: %d KB %sabled\n", 126 size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? 127 "dis" : "en"); 128 } 129 } 130 } 131 132 void 133 booke_disable_l2_cache(void) 134 { 135 } 136 137 static void 138 l3cache_inval(void) 139 { 140 141 /* Flash invalidate the CPC and clear all the locks */ 142 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI | 143 OCP85XX_CPC_CSR0_LFC); 144 while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI | 145 OCP85XX_CPC_CSR0_LFC)) 146 ; 147 } 148 149 static void 150 l3cache_enable(void) 151 { 152 153 ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE | 154 OCP85XX_CPC_CSR0_PE); 155 /* Read back to sync write */ 156 ccsr_read4(OCP85XX_CPC_CSR0); 157 } 158 #endif 159