1 /*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51 #include <sys/cdefs.h> 52 __FBSDID("$FreeBSD$"); 53 54 #include "opt_kstack_pages.h" 55 56 #include <sys/param.h> 57 #include <sys/conf.h> 58 #include <sys/malloc.h> 59 #include <sys/ktr.h> 60 #include <sys/proc.h> 61 #include <sys/user.h> 62 #include <sys/queue.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kerneldump.h> 66 #include <sys/linker.h> 67 #include <sys/msgbuf.h> 68 #include <sys/lock.h> 69 #include <sys/mutex.h> 70 #include <sys/rwlock.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 #include <sys/vmmeter.h> 74 75 #include <vm/vm.h> 76 #include <vm/vm_page.h> 77 #include <vm/vm_kern.h> 78 #include <vm/vm_pageout.h> 79 #include <vm/vm_extern.h> 80 #include <vm/vm_object.h> 81 #include <vm/vm_param.h> 82 #include <vm/vm_map.h> 83 #include <vm/vm_pager.h> 84 #include <vm/uma.h> 85 86 #include <machine/cpu.h> 87 #include <machine/pcb.h> 88 #include <machine/platform.h> 89 90 #include <machine/tlb.h> 91 #include <machine/spr.h> 92 #include <machine/md_var.h> 93 #include <machine/mmuvar.h> 94 #include <machine/pmap.h> 95 #include <machine/pte.h> 96 97 #include "mmu_if.h" 98 99 #define SPARSE_MAPDEV 100 #ifdef DEBUG 101 #define debugf(fmt, args...) printf(fmt, ##args) 102 #else 103 #define debugf(fmt, args...) 104 #endif 105 106 #define TODO panic("%s: not implemented", __func__); 107 108 extern unsigned char _etext[]; 109 extern unsigned char _end[]; 110 111 extern uint32_t *bootinfo; 112 113 vm_paddr_t kernload; 114 vm_offset_t kernstart; 115 vm_size_t kernsize; 116 117 /* Message buffer and tables. */ 118 static vm_offset_t data_start; 119 static vm_size_t data_end; 120 121 /* Phys/avail memory regions. */ 122 static struct mem_region *availmem_regions; 123 static int availmem_regions_sz; 124 static struct mem_region *physmem_regions; 125 static int physmem_regions_sz; 126 127 /* Reserved KVA space and mutex for mmu_booke_zero_page. */ 128 static vm_offset_t zero_page_va; 129 static struct mtx zero_page_mutex; 130 131 static struct mtx tlbivax_mutex; 132 133 /* Reserved KVA space and mutex for mmu_booke_copy_page. */ 134 static vm_offset_t copy_page_src_va; 135 static vm_offset_t copy_page_dst_va; 136 static struct mtx copy_page_mutex; 137 138 /**************************************************************************/ 139 /* PMAP */ 140 /**************************************************************************/ 141 142 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 143 vm_prot_t, u_int flags, int8_t psind); 144 145 unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 146 unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 147 148 /* 149 * If user pmap is processed with mmu_booke_remove and the resident count 150 * drops to 0, there are no more pages to remove, so we need not continue. 151 */ 152 #define PMAP_REMOVE_DONE(pmap) \ 153 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 154 155 extern int elf32_nxstack; 156 157 /**************************************************************************/ 158 /* TLB and TID handling */ 159 /**************************************************************************/ 160 161 /* Translation ID busy table */ 162 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 163 164 /* 165 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 166 * core revisions and should be read from h/w registers during early config. 167 */ 168 uint32_t tlb0_entries; 169 uint32_t tlb0_ways; 170 uint32_t tlb0_entries_per_way; 171 uint32_t tlb1_entries; 172 173 #define TLB0_ENTRIES (tlb0_entries) 174 #define TLB0_WAYS (tlb0_ways) 175 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 176 177 #define TLB1_ENTRIES (tlb1_entries) 178 #define TLB1_MAXENTRIES 64 179 180 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE; 181 182 static tlbtid_t tid_alloc(struct pmap *); 183 static void tid_flush(tlbtid_t tid); 184 185 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 186 187 static void tlb1_read_entry(tlb_entry_t *, unsigned int); 188 static void tlb1_write_entry(tlb_entry_t *, unsigned int); 189 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 190 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 191 192 static vm_size_t tsize2size(unsigned int); 193 static unsigned int size2tsize(vm_size_t); 194 static unsigned int ilog2(unsigned int); 195 196 static void set_mas4_defaults(void); 197 198 static inline void tlb0_flush_entry(vm_offset_t); 199 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 200 201 /**************************************************************************/ 202 /* Page table management */ 203 /**************************************************************************/ 204 205 static struct rwlock_padalign pvh_global_lock; 206 207 /* Data for the pv entry allocation mechanism */ 208 static uma_zone_t pvzone; 209 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 210 211 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 212 213 #ifndef PMAP_SHPGPERPROC 214 #define PMAP_SHPGPERPROC 200 215 #endif 216 217 static void ptbl_init(void); 218 static struct ptbl_buf *ptbl_buf_alloc(void); 219 static void ptbl_buf_free(struct ptbl_buf *); 220 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 221 222 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t); 223 static void ptbl_free(mmu_t, pmap_t, unsigned int); 224 static void ptbl_hold(mmu_t, pmap_t, unsigned int); 225 static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 226 227 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 228 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 229 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t); 230 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 231 static void kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, 232 vm_offset_t pdir); 233 234 static pv_entry_t pv_alloc(void); 235 static void pv_free(pv_entry_t); 236 static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 237 static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 238 239 static void booke_pmap_init_qpages(void); 240 241 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 242 #define PTBL_BUFS (128 * 16) 243 244 struct ptbl_buf { 245 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 246 vm_offset_t kva; /* va of mapping */ 247 }; 248 249 /* ptbl free list and a lock used for access synchronization. */ 250 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 251 static struct mtx ptbl_buf_freelist_lock; 252 253 /* Base address of kva space allocated fot ptbl bufs. */ 254 static vm_offset_t ptbl_buf_pool_vabase; 255 256 /* Pointer to ptbl_buf structures. */ 257 static struct ptbl_buf *ptbl_bufs; 258 259 #ifdef SMP 260 extern tlb_entry_t __boot_tlb1[]; 261 void pmap_bootstrap_ap(volatile uint32_t *); 262 #endif 263 264 /* 265 * Kernel MMU interface 266 */ 267 static void mmu_booke_clear_modify(mmu_t, vm_page_t); 268 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 269 vm_size_t, vm_offset_t); 270 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 271 static void mmu_booke_copy_pages(mmu_t, vm_page_t *, 272 vm_offset_t, vm_page_t *, vm_offset_t, int); 273 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 274 vm_prot_t, u_int flags, int8_t psind); 275 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 276 vm_page_t, vm_prot_t); 277 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 278 vm_prot_t); 279 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 280 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 281 vm_prot_t); 282 static void mmu_booke_init(mmu_t); 283 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 284 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 285 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 286 static int mmu_booke_ts_referenced(mmu_t, vm_page_t); 287 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 288 int); 289 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 290 vm_paddr_t *); 291 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 292 vm_object_t, vm_pindex_t, vm_size_t); 293 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294 static void mmu_booke_page_init(mmu_t, vm_page_t); 295 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 296 static void mmu_booke_pinit(mmu_t, pmap_t); 297 static void mmu_booke_pinit0(mmu_t, pmap_t); 298 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 299 vm_prot_t); 300 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 301 static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 302 static void mmu_booke_release(mmu_t, pmap_t); 303 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 304 static void mmu_booke_remove_all(mmu_t, vm_page_t); 305 static void mmu_booke_remove_write(mmu_t, vm_page_t); 306 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307 static void mmu_booke_zero_page(mmu_t, vm_page_t); 308 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 309 static void mmu_booke_activate(mmu_t, struct thread *); 310 static void mmu_booke_deactivate(mmu_t, struct thread *); 311 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 312 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 313 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t); 314 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 315 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 316 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 317 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t); 318 static void mmu_booke_kremove(mmu_t, vm_offset_t); 319 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 320 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 321 vm_size_t); 322 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t, 323 void **); 324 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t, 325 void *); 326 static void mmu_booke_scan_init(mmu_t); 327 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m); 328 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr); 329 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, 330 vm_size_t sz, vm_memattr_t mode); 331 332 static mmu_method_t mmu_booke_methods[] = { 333 /* pmap dispatcher interface */ 334 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 335 MMUMETHOD(mmu_copy, mmu_booke_copy), 336 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 337 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 338 MMUMETHOD(mmu_enter, mmu_booke_enter), 339 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 340 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 341 MMUMETHOD(mmu_extract, mmu_booke_extract), 342 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 343 MMUMETHOD(mmu_init, mmu_booke_init), 344 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 345 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 346 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 347 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 348 MMUMETHOD(mmu_map, mmu_booke_map), 349 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 350 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 351 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 352 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 353 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 354 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 355 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 356 MMUMETHOD(mmu_protect, mmu_booke_protect), 357 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 358 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 359 MMUMETHOD(mmu_release, mmu_booke_release), 360 MMUMETHOD(mmu_remove, mmu_booke_remove), 361 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 362 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 363 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 364 MMUMETHOD(mmu_unwire, mmu_booke_unwire), 365 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 366 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 367 MMUMETHOD(mmu_activate, mmu_booke_activate), 368 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 369 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page), 370 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr), 377 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 378 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr), 379 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 380 MMUMETHOD(mmu_kremove, mmu_booke_kremove), 381 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 382 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr), 383 384 /* dumpsys() support */ 385 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 386 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 387 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init), 388 389 { 0, 0 } 390 }; 391 392 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 393 394 static __inline uint32_t 395 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) 396 { 397 uint32_t attrib; 398 int i; 399 400 if (ma != VM_MEMATTR_DEFAULT) { 401 switch (ma) { 402 case VM_MEMATTR_UNCACHEABLE: 403 return (MAS2_I | MAS2_G); 404 case VM_MEMATTR_WRITE_COMBINING: 405 case VM_MEMATTR_WRITE_BACK: 406 case VM_MEMATTR_PREFETCHABLE: 407 return (MAS2_I); 408 case VM_MEMATTR_WRITE_THROUGH: 409 return (MAS2_W | MAS2_M); 410 case VM_MEMATTR_CACHEABLE: 411 return (MAS2_M); 412 } 413 } 414 415 /* 416 * Assume the page is cache inhibited and access is guarded unless 417 * it's in our available memory array. 418 */ 419 attrib = _TLB_ENTRY_IO; 420 for (i = 0; i < physmem_regions_sz; i++) { 421 if ((pa >= physmem_regions[i].mr_start) && 422 (pa < (physmem_regions[i].mr_start + 423 physmem_regions[i].mr_size))) { 424 attrib = _TLB_ENTRY_MEM; 425 break; 426 } 427 } 428 429 return (attrib); 430 } 431 432 static inline void 433 tlb_miss_lock(void) 434 { 435 #ifdef SMP 436 struct pcpu *pc; 437 438 if (!smp_started) 439 return; 440 441 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 442 if (pc != pcpup) { 443 444 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 445 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 446 447 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 448 ("tlb_miss_lock: tried to lock self")); 449 450 tlb_lock(pc->pc_booke_tlb_lock); 451 452 CTR1(KTR_PMAP, "%s: locked", __func__); 453 } 454 } 455 #endif 456 } 457 458 static inline void 459 tlb_miss_unlock(void) 460 { 461 #ifdef SMP 462 struct pcpu *pc; 463 464 if (!smp_started) 465 return; 466 467 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 468 if (pc != pcpup) { 469 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 470 __func__, pc->pc_cpuid); 471 472 tlb_unlock(pc->pc_booke_tlb_lock); 473 474 CTR1(KTR_PMAP, "%s: unlocked", __func__); 475 } 476 } 477 #endif 478 } 479 480 /* Return number of entries in TLB0. */ 481 static __inline void 482 tlb0_get_tlbconf(void) 483 { 484 uint32_t tlb0_cfg; 485 486 tlb0_cfg = mfspr(SPR_TLB0CFG); 487 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 488 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 489 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 490 } 491 492 /* Return number of entries in TLB1. */ 493 static __inline void 494 tlb1_get_tlbconf(void) 495 { 496 uint32_t tlb1_cfg; 497 498 tlb1_cfg = mfspr(SPR_TLB1CFG); 499 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK; 500 } 501 502 /**************************************************************************/ 503 /* Page table related */ 504 /**************************************************************************/ 505 506 /* Initialize pool of kva ptbl buffers. */ 507 static void 508 ptbl_init(void) 509 { 510 int i; 511 512 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 513 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 514 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 515 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 516 517 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 518 TAILQ_INIT(&ptbl_buf_freelist); 519 520 for (i = 0; i < PTBL_BUFS; i++) { 521 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 522 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 523 } 524 } 525 526 /* Get a ptbl_buf from the freelist. */ 527 static struct ptbl_buf * 528 ptbl_buf_alloc(void) 529 { 530 struct ptbl_buf *buf; 531 532 mtx_lock(&ptbl_buf_freelist_lock); 533 buf = TAILQ_FIRST(&ptbl_buf_freelist); 534 if (buf != NULL) 535 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 536 mtx_unlock(&ptbl_buf_freelist_lock); 537 538 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 539 540 return (buf); 541 } 542 543 /* Return ptbl buff to free pool. */ 544 static void 545 ptbl_buf_free(struct ptbl_buf *buf) 546 { 547 548 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 549 550 mtx_lock(&ptbl_buf_freelist_lock); 551 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 552 mtx_unlock(&ptbl_buf_freelist_lock); 553 } 554 555 /* 556 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 557 */ 558 static void 559 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 560 { 561 struct ptbl_buf *pbuf; 562 563 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 564 565 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 566 567 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 568 if (pbuf->kva == (vm_offset_t)ptbl) { 569 /* Remove from pmap ptbl buf list. */ 570 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 571 572 /* Free corresponding ptbl buf. */ 573 ptbl_buf_free(pbuf); 574 break; 575 } 576 } 577 578 /* Allocate page table. */ 579 static pte_t * 580 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep) 581 { 582 vm_page_t mtbl[PTBL_PAGES]; 583 vm_page_t m; 584 struct ptbl_buf *pbuf; 585 unsigned int pidx; 586 pte_t *ptbl; 587 int i, j; 588 589 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 590 (pmap == kernel_pmap), pdir_idx); 591 592 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 593 ("ptbl_alloc: invalid pdir_idx")); 594 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 595 ("pte_alloc: valid ptbl entry exists!")); 596 597 pbuf = ptbl_buf_alloc(); 598 if (pbuf == NULL) 599 panic("pte_alloc: couldn't alloc kernel virtual memory"); 600 601 ptbl = (pte_t *)pbuf->kva; 602 603 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 604 605 /* Allocate ptbl pages, this will sleep! */ 606 for (i = 0; i < PTBL_PAGES; i++) { 607 pidx = (PTBL_PAGES * pdir_idx) + i; 608 while ((m = vm_page_alloc(NULL, pidx, 609 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 610 PMAP_UNLOCK(pmap); 611 rw_wunlock(&pvh_global_lock); 612 if (nosleep) { 613 ptbl_free_pmap_ptbl(pmap, ptbl); 614 for (j = 0; j < i; j++) 615 vm_page_free(mtbl[j]); 616 atomic_subtract_int(&vm_cnt.v_wire_count, i); 617 return (NULL); 618 } 619 VM_WAIT; 620 rw_wlock(&pvh_global_lock); 621 PMAP_LOCK(pmap); 622 } 623 mtbl[i] = m; 624 } 625 626 /* Map allocated pages into kernel_pmap. */ 627 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 628 629 /* Zero whole ptbl. */ 630 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 631 632 /* Add pbuf to the pmap ptbl bufs list. */ 633 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 634 635 return (ptbl); 636 } 637 638 /* Free ptbl pages and invalidate pdir entry. */ 639 static void 640 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 641 { 642 pte_t *ptbl; 643 vm_paddr_t pa; 644 vm_offset_t va; 645 vm_page_t m; 646 int i; 647 648 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 649 (pmap == kernel_pmap), pdir_idx); 650 651 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 652 ("ptbl_free: invalid pdir_idx")); 653 654 ptbl = pmap->pm_pdir[pdir_idx]; 655 656 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 657 658 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 659 660 /* 661 * Invalidate the pdir entry as soon as possible, so that other CPUs 662 * don't attempt to look up the page tables we are releasing. 663 */ 664 mtx_lock_spin(&tlbivax_mutex); 665 tlb_miss_lock(); 666 667 pmap->pm_pdir[pdir_idx] = NULL; 668 669 tlb_miss_unlock(); 670 mtx_unlock_spin(&tlbivax_mutex); 671 672 for (i = 0; i < PTBL_PAGES; i++) { 673 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 674 pa = pte_vatopa(mmu, kernel_pmap, va); 675 m = PHYS_TO_VM_PAGE(pa); 676 vm_page_free_zero(m); 677 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 678 mmu_booke_kremove(mmu, va); 679 } 680 681 ptbl_free_pmap_ptbl(pmap, ptbl); 682 } 683 684 /* 685 * Decrement ptbl pages hold count and attempt to free ptbl pages. 686 * Called when removing pte entry from ptbl. 687 * 688 * Return 1 if ptbl pages were freed. 689 */ 690 static int 691 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 692 { 693 pte_t *ptbl; 694 vm_paddr_t pa; 695 vm_page_t m; 696 int i; 697 698 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 699 (pmap == kernel_pmap), pdir_idx); 700 701 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 702 ("ptbl_unhold: invalid pdir_idx")); 703 KASSERT((pmap != kernel_pmap), 704 ("ptbl_unhold: unholding kernel ptbl!")); 705 706 ptbl = pmap->pm_pdir[pdir_idx]; 707 708 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 709 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 710 ("ptbl_unhold: non kva ptbl")); 711 712 /* decrement hold count */ 713 for (i = 0; i < PTBL_PAGES; i++) { 714 pa = pte_vatopa(mmu, kernel_pmap, 715 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 716 m = PHYS_TO_VM_PAGE(pa); 717 m->wire_count--; 718 } 719 720 /* 721 * Free ptbl pages if there are no pte etries in this ptbl. 722 * wire_count has the same value for all ptbl pages, so check the last 723 * page. 724 */ 725 if (m->wire_count == 0) { 726 ptbl_free(mmu, pmap, pdir_idx); 727 728 //debugf("ptbl_unhold: e (freed ptbl)\n"); 729 return (1); 730 } 731 732 return (0); 733 } 734 735 /* 736 * Increment hold count for ptbl pages. This routine is used when a new pte 737 * entry is being inserted into the ptbl. 738 */ 739 static void 740 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 741 { 742 vm_paddr_t pa; 743 pte_t *ptbl; 744 vm_page_t m; 745 int i; 746 747 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 748 pdir_idx); 749 750 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 751 ("ptbl_hold: invalid pdir_idx")); 752 KASSERT((pmap != kernel_pmap), 753 ("ptbl_hold: holding kernel ptbl!")); 754 755 ptbl = pmap->pm_pdir[pdir_idx]; 756 757 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 758 759 for (i = 0; i < PTBL_PAGES; i++) { 760 pa = pte_vatopa(mmu, kernel_pmap, 761 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 762 m = PHYS_TO_VM_PAGE(pa); 763 m->wire_count++; 764 } 765 } 766 767 /* Allocate pv_entry structure. */ 768 pv_entry_t 769 pv_alloc(void) 770 { 771 pv_entry_t pv; 772 773 pv_entry_count++; 774 if (pv_entry_count > pv_entry_high_water) 775 pagedaemon_wakeup(); 776 pv = uma_zalloc(pvzone, M_NOWAIT); 777 778 return (pv); 779 } 780 781 /* Free pv_entry structure. */ 782 static __inline void 783 pv_free(pv_entry_t pve) 784 { 785 786 pv_entry_count--; 787 uma_zfree(pvzone, pve); 788 } 789 790 791 /* Allocate and initialize pv_entry structure. */ 792 static void 793 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 794 { 795 pv_entry_t pve; 796 797 //int su = (pmap == kernel_pmap); 798 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 799 // (u_int32_t)pmap, va, (u_int32_t)m); 800 801 pve = pv_alloc(); 802 if (pve == NULL) 803 panic("pv_insert: no pv entries!"); 804 805 pve->pv_pmap = pmap; 806 pve->pv_va = va; 807 808 /* add to pv_list */ 809 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 810 rw_assert(&pvh_global_lock, RA_WLOCKED); 811 812 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 813 814 //debugf("pv_insert: e\n"); 815 } 816 817 /* Destroy pv entry. */ 818 static void 819 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 820 { 821 pv_entry_t pve; 822 823 //int su = (pmap == kernel_pmap); 824 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 825 826 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 827 rw_assert(&pvh_global_lock, RA_WLOCKED); 828 829 /* find pv entry */ 830 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 831 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 832 /* remove from pv_list */ 833 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 834 if (TAILQ_EMPTY(&m->md.pv_list)) 835 vm_page_aflag_clear(m, PGA_WRITEABLE); 836 837 /* free pv entry struct */ 838 pv_free(pve); 839 break; 840 } 841 } 842 843 //debugf("pv_remove: e\n"); 844 } 845 846 /* 847 * Clean pte entry, try to free page table page if requested. 848 * 849 * Return 1 if ptbl pages were freed, otherwise return 0. 850 */ 851 static int 852 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 853 { 854 unsigned int pdir_idx = PDIR_IDX(va); 855 unsigned int ptbl_idx = PTBL_IDX(va); 856 vm_page_t m; 857 pte_t *ptbl; 858 pte_t *pte; 859 860 //int su = (pmap == kernel_pmap); 861 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 862 // su, (u_int32_t)pmap, va, flags); 863 864 ptbl = pmap->pm_pdir[pdir_idx]; 865 KASSERT(ptbl, ("pte_remove: null ptbl")); 866 867 pte = &ptbl[ptbl_idx]; 868 869 if (pte == NULL || !PTE_ISVALID(pte)) 870 return (0); 871 872 if (PTE_ISWIRED(pte)) 873 pmap->pm_stats.wired_count--; 874 875 /* Get vm_page_t for mapped pte. */ 876 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 877 878 /* Handle managed entry. */ 879 if (PTE_ISMANAGED(pte)) { 880 881 if (PTE_ISMODIFIED(pte)) 882 vm_page_dirty(m); 883 884 if (PTE_ISREFERENCED(pte)) 885 vm_page_aflag_set(m, PGA_REFERENCED); 886 887 pv_remove(pmap, va, m); 888 } else if (m->md.pv_tracked) { 889 /* 890 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is 891 * used. This is needed by the NCSW support code for fast 892 * VA<->PA translation. 893 */ 894 pv_remove(pmap, va, m); 895 if (TAILQ_EMPTY(&m->md.pv_list)) 896 m->md.pv_tracked = false; 897 } 898 899 mtx_lock_spin(&tlbivax_mutex); 900 tlb_miss_lock(); 901 902 tlb0_flush_entry(va); 903 *pte = 0; 904 905 tlb_miss_unlock(); 906 mtx_unlock_spin(&tlbivax_mutex); 907 908 pmap->pm_stats.resident_count--; 909 910 if (flags & PTBL_UNHOLD) { 911 //debugf("pte_remove: e (unhold)\n"); 912 return (ptbl_unhold(mmu, pmap, pdir_idx)); 913 } 914 915 //debugf("pte_remove: e\n"); 916 return (0); 917 } 918 919 /* 920 * Insert PTE for a given page and virtual address. 921 */ 922 static int 923 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags, 924 boolean_t nosleep) 925 { 926 unsigned int pdir_idx = PDIR_IDX(va); 927 unsigned int ptbl_idx = PTBL_IDX(va); 928 pte_t *ptbl, *pte; 929 930 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 931 pmap == kernel_pmap, pmap, va); 932 933 /* Get the page table pointer. */ 934 ptbl = pmap->pm_pdir[pdir_idx]; 935 936 if (ptbl == NULL) { 937 /* Allocate page table pages. */ 938 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep); 939 if (ptbl == NULL) { 940 KASSERT(nosleep, ("nosleep and NULL ptbl")); 941 return (ENOMEM); 942 } 943 } else { 944 /* 945 * Check if there is valid mapping for requested 946 * va, if there is, remove it. 947 */ 948 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 949 if (PTE_ISVALID(pte)) { 950 pte_remove(mmu, pmap, va, PTBL_HOLD); 951 } else { 952 /* 953 * pte is not used, increment hold count 954 * for ptbl pages. 955 */ 956 if (pmap != kernel_pmap) 957 ptbl_hold(mmu, pmap, pdir_idx); 958 } 959 } 960 961 /* 962 * Insert pv_entry into pv_list for mapped page if part of managed 963 * memory. 964 */ 965 if ((m->oflags & VPO_UNMANAGED) == 0) { 966 flags |= PTE_MANAGED; 967 968 /* Create and insert pv entry. */ 969 pv_insert(pmap, va, m); 970 } 971 972 pmap->pm_stats.resident_count++; 973 974 mtx_lock_spin(&tlbivax_mutex); 975 tlb_miss_lock(); 976 977 tlb0_flush_entry(va); 978 if (pmap->pm_pdir[pdir_idx] == NULL) { 979 /* 980 * If we just allocated a new page table, hook it in 981 * the pdir. 982 */ 983 pmap->pm_pdir[pdir_idx] = ptbl; 984 } 985 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 986 *pte = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m)); 987 *pte |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */ 988 989 tlb_miss_unlock(); 990 mtx_unlock_spin(&tlbivax_mutex); 991 return (0); 992 } 993 994 /* Return the pa for the given pmap/va. */ 995 static vm_paddr_t 996 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 997 { 998 vm_paddr_t pa = 0; 999 pte_t *pte; 1000 1001 pte = pte_find(mmu, pmap, va); 1002 if ((pte != NULL) && PTE_ISVALID(pte)) 1003 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 1004 return (pa); 1005 } 1006 1007 /* Get a pointer to a PTE in a page table. */ 1008 static pte_t * 1009 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1010 { 1011 unsigned int pdir_idx = PDIR_IDX(va); 1012 unsigned int ptbl_idx = PTBL_IDX(va); 1013 1014 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 1015 1016 if (pmap->pm_pdir[pdir_idx]) 1017 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 1018 1019 return (NULL); 1020 } 1021 1022 /* Set up kernel page tables. */ 1023 static void 1024 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir) 1025 { 1026 int i; 1027 vm_offset_t va; 1028 pte_t *pte; 1029 1030 /* Initialize kernel pdir */ 1031 for (i = 0; i < kernel_ptbls; i++) 1032 kernel_pmap->pm_pdir[kptbl_min + i] = 1033 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1034 1035 /* 1036 * Fill in PTEs covering kernel code and data. They are not required 1037 * for address translation, as this area is covered by static TLB1 1038 * entries, but for pte_vatopa() to work correctly with kernel area 1039 * addresses. 1040 */ 1041 for (va = addr; va < data_end; va += PAGE_SIZE) { 1042 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1043 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart)); 1044 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1045 PTE_VALID | PTE_PS_4KB; 1046 } 1047 } 1048 1049 /**************************************************************************/ 1050 /* PMAP related */ 1051 /**************************************************************************/ 1052 1053 /* 1054 * This is called during booke_init, before the system is really initialized. 1055 */ 1056 static void 1057 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 1058 { 1059 vm_paddr_t phys_kernelend; 1060 struct mem_region *mp, *mp1; 1061 int cnt, i, j; 1062 vm_paddr_t s, e, sz; 1063 vm_paddr_t physsz, hwphyssz; 1064 u_int phys_avail_count; 1065 vm_size_t kstack0_sz; 1066 vm_offset_t kernel_pdir, kstack0; 1067 vm_paddr_t kstack0_phys; 1068 void *dpcpu; 1069 1070 debugf("mmu_booke_bootstrap: entered\n"); 1071 1072 /* Set interesting system properties */ 1073 hw_direct_map = 0; 1074 elf32_nxstack = 1; 1075 1076 /* Initialize invalidation mutex */ 1077 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 1078 1079 /* Read TLB0 size and associativity. */ 1080 tlb0_get_tlbconf(); 1081 1082 /* 1083 * Align kernel start and end address (kernel image). 1084 * Note that kernel end does not necessarily relate to kernsize. 1085 * kernsize is the size of the kernel that is actually mapped. 1086 */ 1087 kernstart = trunc_page(start); 1088 data_start = round_page(kernelend); 1089 data_end = data_start; 1090 1091 /* 1092 * Addresses of preloaded modules (like file systems) use 1093 * physical addresses. Make sure we relocate those into 1094 * virtual addresses. 1095 */ 1096 preload_addr_relocate = kernstart - kernload; 1097 1098 /* Allocate the dynamic per-cpu area. */ 1099 dpcpu = (void *)data_end; 1100 data_end += DPCPU_SIZE; 1101 1102 /* Allocate space for the message buffer. */ 1103 msgbufp = (struct msgbuf *)data_end; 1104 data_end += msgbufsize; 1105 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1106 data_end); 1107 1108 data_end = round_page(data_end); 1109 1110 /* Allocate space for ptbl_bufs. */ 1111 ptbl_bufs = (struct ptbl_buf *)data_end; 1112 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1113 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1114 data_end); 1115 1116 data_end = round_page(data_end); 1117 1118 /* Allocate PTE tables for kernel KVA. */ 1119 kernel_pdir = data_end; 1120 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS, 1121 PDIR_SIZE); 1122 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1123 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1124 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1125 1126 debugf(" data_end: 0x%08x\n", data_end); 1127 if (data_end - kernstart > kernsize) { 1128 kernsize += tlb1_mapin_region(kernstart + kernsize, 1129 kernload + kernsize, (data_end - kernstart) - kernsize); 1130 } 1131 data_end = kernstart + kernsize; 1132 debugf(" updated data_end: 0x%08x\n", data_end); 1133 1134 /* 1135 * Clear the structures - note we can only do it safely after the 1136 * possible additional TLB1 translations are in place (above) so that 1137 * all range up to the currently calculated 'data_end' is covered. 1138 */ 1139 dpcpu_init(dpcpu, 0); 1140 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1141 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1142 1143 /*******************************************************/ 1144 /* Set the start and end of kva. */ 1145 /*******************************************************/ 1146 virtual_avail = round_page(data_end); 1147 virtual_end = VM_MAX_KERNEL_ADDRESS; 1148 1149 /* Allocate KVA space for page zero/copy operations. */ 1150 zero_page_va = virtual_avail; 1151 virtual_avail += PAGE_SIZE; 1152 copy_page_src_va = virtual_avail; 1153 virtual_avail += PAGE_SIZE; 1154 copy_page_dst_va = virtual_avail; 1155 virtual_avail += PAGE_SIZE; 1156 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1157 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1158 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1159 1160 /* Initialize page zero/copy mutexes. */ 1161 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1162 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1163 1164 /* Allocate KVA space for ptbl bufs. */ 1165 ptbl_buf_pool_vabase = virtual_avail; 1166 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1167 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1168 ptbl_buf_pool_vabase, virtual_avail); 1169 1170 /* Calculate corresponding physical addresses for the kernel region. */ 1171 phys_kernelend = kernload + kernsize; 1172 debugf("kernel image and allocated data:\n"); 1173 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload); 1174 debugf(" kernstart = 0x%08x\n", kernstart); 1175 debugf(" kernsize = 0x%08x\n", kernsize); 1176 1177 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1178 panic("mmu_booke_bootstrap: phys_avail too small"); 1179 1180 /* 1181 * Remove kernel physical address range from avail regions list. Page 1182 * align all regions. Non-page aligned memory isn't very interesting 1183 * to us. Also, sort the entries for ascending addresses. 1184 */ 1185 1186 /* Retrieve phys/avail mem regions */ 1187 mem_regions(&physmem_regions, &physmem_regions_sz, 1188 &availmem_regions, &availmem_regions_sz); 1189 sz = 0; 1190 cnt = availmem_regions_sz; 1191 debugf("processing avail regions:\n"); 1192 for (mp = availmem_regions; mp->mr_size; mp++) { 1193 s = mp->mr_start; 1194 e = mp->mr_start + mp->mr_size; 1195 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e); 1196 /* Check whether this region holds all of the kernel. */ 1197 if (s < kernload && e > phys_kernelend) { 1198 availmem_regions[cnt].mr_start = phys_kernelend; 1199 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1200 e = kernload; 1201 } 1202 /* Look whether this regions starts within the kernel. */ 1203 if (s >= kernload && s < phys_kernelend) { 1204 if (e <= phys_kernelend) 1205 goto empty; 1206 s = phys_kernelend; 1207 } 1208 /* Now look whether this region ends within the kernel. */ 1209 if (e > kernload && e <= phys_kernelend) { 1210 if (s >= kernload) 1211 goto empty; 1212 e = kernload; 1213 } 1214 /* Now page align the start and size of the region. */ 1215 s = round_page(s); 1216 e = trunc_page(e); 1217 if (e < s) 1218 e = s; 1219 sz = e - s; 1220 debugf("%09jx-%09jx = %jx\n", 1221 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz); 1222 1223 /* Check whether some memory is left here. */ 1224 if (sz == 0) { 1225 empty: 1226 memmove(mp, mp + 1, 1227 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1228 cnt--; 1229 mp--; 1230 continue; 1231 } 1232 1233 /* Do an insertion sort. */ 1234 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1235 if (s < mp1->mr_start) 1236 break; 1237 if (mp1 < mp) { 1238 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1239 mp1->mr_start = s; 1240 mp1->mr_size = sz; 1241 } else { 1242 mp->mr_start = s; 1243 mp->mr_size = sz; 1244 } 1245 } 1246 availmem_regions_sz = cnt; 1247 1248 /*******************************************************/ 1249 /* Steal physical memory for kernel stack from the end */ 1250 /* of the first avail region */ 1251 /*******************************************************/ 1252 kstack0_sz = kstack_pages * PAGE_SIZE; 1253 kstack0_phys = availmem_regions[0].mr_start + 1254 availmem_regions[0].mr_size; 1255 kstack0_phys -= kstack0_sz; 1256 availmem_regions[0].mr_size -= kstack0_sz; 1257 1258 /*******************************************************/ 1259 /* Fill in phys_avail table, based on availmem_regions */ 1260 /*******************************************************/ 1261 phys_avail_count = 0; 1262 physsz = 0; 1263 hwphyssz = 0; 1264 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1265 1266 debugf("fill in phys_avail:\n"); 1267 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1268 1269 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n", 1270 (uintmax_t)availmem_regions[i].mr_start, 1271 (uintmax_t)availmem_regions[i].mr_start + 1272 availmem_regions[i].mr_size, 1273 (uintmax_t)availmem_regions[i].mr_size); 1274 1275 if (hwphyssz != 0 && 1276 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1277 debugf(" hw.physmem adjust\n"); 1278 if (physsz < hwphyssz) { 1279 phys_avail[j] = availmem_regions[i].mr_start; 1280 phys_avail[j + 1] = 1281 availmem_regions[i].mr_start + 1282 hwphyssz - physsz; 1283 physsz = hwphyssz; 1284 phys_avail_count++; 1285 } 1286 break; 1287 } 1288 1289 phys_avail[j] = availmem_regions[i].mr_start; 1290 phys_avail[j + 1] = availmem_regions[i].mr_start + 1291 availmem_regions[i].mr_size; 1292 phys_avail_count++; 1293 physsz += availmem_regions[i].mr_size; 1294 } 1295 physmem = btoc(physsz); 1296 1297 /* Calculate the last available physical address. */ 1298 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1299 ; 1300 Maxmem = powerpc_btop(phys_avail[i + 1]); 1301 1302 debugf("Maxmem = 0x%08lx\n", Maxmem); 1303 debugf("phys_avail_count = %d\n", phys_avail_count); 1304 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n", 1305 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem); 1306 1307 /*******************************************************/ 1308 /* Initialize (statically allocated) kernel pmap. */ 1309 /*******************************************************/ 1310 PMAP_LOCK_INIT(kernel_pmap); 1311 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1312 1313 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1314 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1315 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1316 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1317 1318 kernel_pte_alloc(data_end, kernstart, kernel_pdir); 1319 for (i = 0; i < MAXCPU; i++) { 1320 kernel_pmap->pm_tid[i] = TID_KERNEL; 1321 1322 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1323 tidbusy[i][TID_KERNEL] = kernel_pmap; 1324 } 1325 1326 /* Mark kernel_pmap active on all CPUs */ 1327 CPU_FILL(&kernel_pmap->pm_active); 1328 1329 /* 1330 * Initialize the global pv list lock. 1331 */ 1332 rw_init(&pvh_global_lock, "pmap pv global"); 1333 1334 /*******************************************************/ 1335 /* Final setup */ 1336 /*******************************************************/ 1337 1338 /* Enter kstack0 into kernel map, provide guard page */ 1339 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1340 thread0.td_kstack = kstack0; 1341 thread0.td_kstack_pages = kstack_pages; 1342 1343 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1344 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n", 1345 kstack0_phys, kstack0_phys + kstack0_sz); 1346 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1347 1348 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1349 for (i = 0; i < kstack_pages; i++) { 1350 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1351 kstack0 += PAGE_SIZE; 1352 kstack0_phys += PAGE_SIZE; 1353 } 1354 1355 pmap_bootstrapped = 1; 1356 1357 debugf("virtual_avail = %08x\n", virtual_avail); 1358 debugf("virtual_end = %08x\n", virtual_end); 1359 1360 debugf("mmu_booke_bootstrap: exit\n"); 1361 } 1362 1363 #ifdef SMP 1364 void 1365 tlb1_ap_prep(void) 1366 { 1367 tlb_entry_t *e, tmp; 1368 unsigned int i; 1369 1370 /* Prepare TLB1 image for AP processors */ 1371 e = __boot_tlb1; 1372 for (i = 0; i < TLB1_ENTRIES; i++) { 1373 tlb1_read_entry(&tmp, i); 1374 1375 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED)) 1376 memcpy(e++, &tmp, sizeof(tmp)); 1377 } 1378 } 1379 1380 void 1381 pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1382 { 1383 int i; 1384 1385 /* 1386 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1387 * have the snapshot of its contents in the s/w __boot_tlb1[] table 1388 * created by tlb1_ap_prep(), so use these values directly to 1389 * (re)program AP's TLB1 hardware. 1390 * 1391 * Start at index 1 because index 0 has the kernel map. 1392 */ 1393 for (i = 1; i < TLB1_ENTRIES; i++) { 1394 if (__boot_tlb1[i].mas1 & MAS1_VALID) 1395 tlb1_write_entry(&__boot_tlb1[i], i); 1396 } 1397 1398 set_mas4_defaults(); 1399 } 1400 #endif 1401 1402 static void 1403 booke_pmap_init_qpages(void) 1404 { 1405 struct pcpu *pc; 1406 int i; 1407 1408 CPU_FOREACH(i) { 1409 pc = pcpu_find(i); 1410 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE); 1411 if (pc->pc_qmap_addr == 0) 1412 panic("pmap_init_qpages: unable to allocate KVA"); 1413 } 1414 } 1415 1416 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL); 1417 1418 /* 1419 * Get the physical page address for the given pmap/virtual address. 1420 */ 1421 static vm_paddr_t 1422 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1423 { 1424 vm_paddr_t pa; 1425 1426 PMAP_LOCK(pmap); 1427 pa = pte_vatopa(mmu, pmap, va); 1428 PMAP_UNLOCK(pmap); 1429 1430 return (pa); 1431 } 1432 1433 /* 1434 * Extract the physical page address associated with the given 1435 * kernel virtual address. 1436 */ 1437 static vm_paddr_t 1438 mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1439 { 1440 tlb_entry_t e; 1441 int i; 1442 1443 /* Check TLB1 mappings */ 1444 for (i = 0; i < TLB1_ENTRIES; i++) { 1445 tlb1_read_entry(&e, i); 1446 if (!(e.mas1 & MAS1_VALID)) 1447 continue; 1448 if (va >= e.virt && va < e.virt + e.size) 1449 return (e.phys + (va - e.virt)); 1450 } 1451 1452 return (pte_vatopa(mmu, kernel_pmap, va)); 1453 } 1454 1455 /* 1456 * Initialize the pmap module. 1457 * Called by vm_init, to initialize any structures that the pmap 1458 * system needs to map virtual memory. 1459 */ 1460 static void 1461 mmu_booke_init(mmu_t mmu) 1462 { 1463 int shpgperproc = PMAP_SHPGPERPROC; 1464 1465 /* 1466 * Initialize the address space (zone) for the pv entries. Set a 1467 * high water mark so that the system can recover from excessive 1468 * numbers of pv entries. 1469 */ 1470 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1471 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1472 1473 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1474 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count; 1475 1476 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1477 pv_entry_high_water = 9 * (pv_entry_max / 10); 1478 1479 uma_zone_reserve_kva(pvzone, pv_entry_max); 1480 1481 /* Pre-fill pvzone with initial number of pv entries. */ 1482 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1483 1484 /* Initialize ptbl allocation. */ 1485 ptbl_init(); 1486 } 1487 1488 /* 1489 * Map a list of wired pages into kernel virtual address space. This is 1490 * intended for temporary mappings which do not need page modification or 1491 * references recorded. Existing mappings in the region are overwritten. 1492 */ 1493 static void 1494 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1495 { 1496 vm_offset_t va; 1497 1498 va = sva; 1499 while (count-- > 0) { 1500 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1501 va += PAGE_SIZE; 1502 m++; 1503 } 1504 } 1505 1506 /* 1507 * Remove page mappings from kernel virtual address space. Intended for 1508 * temporary mappings entered by mmu_booke_qenter. 1509 */ 1510 static void 1511 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1512 { 1513 vm_offset_t va; 1514 1515 va = sva; 1516 while (count-- > 0) { 1517 mmu_booke_kremove(mmu, va); 1518 va += PAGE_SIZE; 1519 } 1520 } 1521 1522 /* 1523 * Map a wired page into kernel virtual address space. 1524 */ 1525 static void 1526 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1527 { 1528 1529 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT); 1530 } 1531 1532 static void 1533 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma) 1534 { 1535 uint32_t flags; 1536 pte_t *pte; 1537 1538 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1539 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1540 1541 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1542 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT; 1543 flags |= PTE_PS_4KB; 1544 1545 pte = pte_find(mmu, kernel_pmap, va); 1546 1547 mtx_lock_spin(&tlbivax_mutex); 1548 tlb_miss_lock(); 1549 1550 if (PTE_ISVALID(pte)) { 1551 1552 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1553 1554 /* Flush entry from TLB0 */ 1555 tlb0_flush_entry(va); 1556 } 1557 1558 *pte = PTE_RPN_FROM_PA(pa) | flags; 1559 1560 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1561 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1562 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1563 1564 /* Flush the real memory from the instruction cache. */ 1565 if ((flags & (PTE_I | PTE_G)) == 0) 1566 __syncicache((void *)va, PAGE_SIZE); 1567 1568 tlb_miss_unlock(); 1569 mtx_unlock_spin(&tlbivax_mutex); 1570 } 1571 1572 /* 1573 * Remove a page from kernel page table. 1574 */ 1575 static void 1576 mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1577 { 1578 pte_t *pte; 1579 1580 CTR2(KTR_PMAP,"%s: s (va = 0x%08x)\n", __func__, va); 1581 1582 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1583 (va <= VM_MAX_KERNEL_ADDRESS)), 1584 ("mmu_booke_kremove: invalid va")); 1585 1586 pte = pte_find(mmu, kernel_pmap, va); 1587 1588 if (!PTE_ISVALID(pte)) { 1589 1590 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1591 1592 return; 1593 } 1594 1595 mtx_lock_spin(&tlbivax_mutex); 1596 tlb_miss_lock(); 1597 1598 /* Invalidate entry in TLB0, update PTE. */ 1599 tlb0_flush_entry(va); 1600 *pte = 0; 1601 1602 tlb_miss_unlock(); 1603 mtx_unlock_spin(&tlbivax_mutex); 1604 } 1605 1606 /* 1607 * Initialize pmap associated with process 0. 1608 */ 1609 static void 1610 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1611 { 1612 1613 PMAP_LOCK_INIT(pmap); 1614 mmu_booke_pinit(mmu, pmap); 1615 PCPU_SET(curpmap, pmap); 1616 } 1617 1618 /* 1619 * Initialize a preallocated and zeroed pmap structure, 1620 * such as one in a vmspace structure. 1621 */ 1622 static void 1623 mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1624 { 1625 int i; 1626 1627 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1628 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1629 1630 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1631 1632 for (i = 0; i < MAXCPU; i++) 1633 pmap->pm_tid[i] = TID_NONE; 1634 CPU_ZERO(&kernel_pmap->pm_active); 1635 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1636 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1637 TAILQ_INIT(&pmap->pm_ptbl_list); 1638 } 1639 1640 /* 1641 * Release any resources held by the given physical map. 1642 * Called when a pmap initialized by mmu_booke_pinit is being released. 1643 * Should only be called if the map contains no valid mappings. 1644 */ 1645 static void 1646 mmu_booke_release(mmu_t mmu, pmap_t pmap) 1647 { 1648 1649 KASSERT(pmap->pm_stats.resident_count == 0, 1650 ("pmap_release: pmap resident count %ld != 0", 1651 pmap->pm_stats.resident_count)); 1652 } 1653 1654 /* 1655 * Insert the given physical page at the specified virtual address in the 1656 * target physical map with the protection requested. If specified the page 1657 * will be wired down. 1658 */ 1659 static int 1660 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1661 vm_prot_t prot, u_int flags, int8_t psind) 1662 { 1663 int error; 1664 1665 rw_wlock(&pvh_global_lock); 1666 PMAP_LOCK(pmap); 1667 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind); 1668 rw_wunlock(&pvh_global_lock); 1669 PMAP_UNLOCK(pmap); 1670 return (error); 1671 } 1672 1673 static int 1674 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1675 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused) 1676 { 1677 pte_t *pte; 1678 vm_paddr_t pa; 1679 uint32_t flags; 1680 int error, su, sync; 1681 1682 pa = VM_PAGE_TO_PHYS(m); 1683 su = (pmap == kernel_pmap); 1684 sync = 0; 1685 1686 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1687 // "pa=0x%08x prot=0x%08x flags=%#x)\n", 1688 // (u_int32_t)pmap, su, pmap->pm_tid, 1689 // (u_int32_t)m, va, pa, prot, flags); 1690 1691 if (su) { 1692 KASSERT(((va >= virtual_avail) && 1693 (va <= VM_MAX_KERNEL_ADDRESS)), 1694 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1695 } else { 1696 KASSERT((va <= VM_MAXUSER_ADDRESS), 1697 ("mmu_booke_enter_locked: user pmap, non user va")); 1698 } 1699 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1700 VM_OBJECT_ASSERT_LOCKED(m->object); 1701 1702 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1703 1704 /* 1705 * If there is an existing mapping, and the physical address has not 1706 * changed, must be protection or wiring change. 1707 */ 1708 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1709 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1710 1711 /* 1712 * Before actually updating pte->flags we calculate and 1713 * prepare its new value in a helper var. 1714 */ 1715 flags = *pte; 1716 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1717 1718 /* Wiring change, just update stats. */ 1719 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) { 1720 if (!PTE_ISWIRED(pte)) { 1721 flags |= PTE_WIRED; 1722 pmap->pm_stats.wired_count++; 1723 } 1724 } else { 1725 if (PTE_ISWIRED(pte)) { 1726 flags &= ~PTE_WIRED; 1727 pmap->pm_stats.wired_count--; 1728 } 1729 } 1730 1731 if (prot & VM_PROT_WRITE) { 1732 /* Add write permissions. */ 1733 flags |= PTE_SW; 1734 if (!su) 1735 flags |= PTE_UW; 1736 1737 if ((flags & PTE_MANAGED) != 0) 1738 vm_page_aflag_set(m, PGA_WRITEABLE); 1739 } else { 1740 /* Handle modified pages, sense modify status. */ 1741 1742 /* 1743 * The PTE_MODIFIED flag could be set by underlying 1744 * TLB misses since we last read it (above), possibly 1745 * other CPUs could update it so we check in the PTE 1746 * directly rather than rely on that saved local flags 1747 * copy. 1748 */ 1749 if (PTE_ISMODIFIED(pte)) 1750 vm_page_dirty(m); 1751 } 1752 1753 if (prot & VM_PROT_EXECUTE) { 1754 flags |= PTE_SX; 1755 if (!su) 1756 flags |= PTE_UX; 1757 1758 /* 1759 * Check existing flags for execute permissions: if we 1760 * are turning execute permissions on, icache should 1761 * be flushed. 1762 */ 1763 if ((*pte & (PTE_UX | PTE_SX)) == 0) 1764 sync++; 1765 } 1766 1767 flags &= ~PTE_REFERENCED; 1768 1769 /* 1770 * The new flags value is all calculated -- only now actually 1771 * update the PTE. 1772 */ 1773 mtx_lock_spin(&tlbivax_mutex); 1774 tlb_miss_lock(); 1775 1776 tlb0_flush_entry(va); 1777 *pte &= ~PTE_FLAGS_MASK; 1778 *pte |= flags; 1779 1780 tlb_miss_unlock(); 1781 mtx_unlock_spin(&tlbivax_mutex); 1782 1783 } else { 1784 /* 1785 * If there is an existing mapping, but it's for a different 1786 * physical address, pte_enter() will delete the old mapping. 1787 */ 1788 //if ((pte != NULL) && PTE_ISVALID(pte)) 1789 // debugf("mmu_booke_enter_locked: replace\n"); 1790 //else 1791 // debugf("mmu_booke_enter_locked: new\n"); 1792 1793 /* Now set up the flags and install the new mapping. */ 1794 flags = (PTE_SR | PTE_VALID); 1795 flags |= PTE_M; 1796 1797 if (!su) 1798 flags |= PTE_UR; 1799 1800 if (prot & VM_PROT_WRITE) { 1801 flags |= PTE_SW; 1802 if (!su) 1803 flags |= PTE_UW; 1804 1805 if ((m->oflags & VPO_UNMANAGED) == 0) 1806 vm_page_aflag_set(m, PGA_WRITEABLE); 1807 } 1808 1809 if (prot & VM_PROT_EXECUTE) { 1810 flags |= PTE_SX; 1811 if (!su) 1812 flags |= PTE_UX; 1813 } 1814 1815 /* If its wired update stats. */ 1816 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) 1817 flags |= PTE_WIRED; 1818 1819 error = pte_enter(mmu, pmap, m, va, flags, 1820 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0); 1821 if (error != 0) 1822 return (KERN_RESOURCE_SHORTAGE); 1823 1824 if ((flags & PMAP_ENTER_WIRED) != 0) 1825 pmap->pm_stats.wired_count++; 1826 1827 /* Flush the real memory from the instruction cache. */ 1828 if (prot & VM_PROT_EXECUTE) 1829 sync++; 1830 } 1831 1832 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1833 __syncicache((void *)va, PAGE_SIZE); 1834 sync = 0; 1835 } 1836 1837 return (KERN_SUCCESS); 1838 } 1839 1840 /* 1841 * Maps a sequence of resident pages belonging to the same object. 1842 * The sequence begins with the given page m_start. This page is 1843 * mapped at the given virtual address start. Each subsequent page is 1844 * mapped at a virtual address that is offset from start by the same 1845 * amount as the page is offset from m_start within the object. The 1846 * last page in the sequence is the page with the largest offset from 1847 * m_start that can be mapped at a virtual address less than the given 1848 * virtual address end. Not every virtual page between start and end 1849 * is mapped; only those for which a resident page exists with the 1850 * corresponding offset from m_start are mapped. 1851 */ 1852 static void 1853 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1854 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1855 { 1856 vm_page_t m; 1857 vm_pindex_t diff, psize; 1858 1859 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1860 1861 psize = atop(end - start); 1862 m = m_start; 1863 rw_wlock(&pvh_global_lock); 1864 PMAP_LOCK(pmap); 1865 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1866 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1867 prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1868 PMAP_ENTER_NOSLEEP, 0); 1869 m = TAILQ_NEXT(m, listq); 1870 } 1871 rw_wunlock(&pvh_global_lock); 1872 PMAP_UNLOCK(pmap); 1873 } 1874 1875 static void 1876 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1877 vm_prot_t prot) 1878 { 1879 1880 rw_wlock(&pvh_global_lock); 1881 PMAP_LOCK(pmap); 1882 mmu_booke_enter_locked(mmu, pmap, va, m, 1883 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 1884 0); 1885 rw_wunlock(&pvh_global_lock); 1886 PMAP_UNLOCK(pmap); 1887 } 1888 1889 /* 1890 * Remove the given range of addresses from the specified map. 1891 * 1892 * It is assumed that the start and end are properly rounded to the page size. 1893 */ 1894 static void 1895 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1896 { 1897 pte_t *pte; 1898 uint8_t hold_flag; 1899 1900 int su = (pmap == kernel_pmap); 1901 1902 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1903 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1904 1905 if (su) { 1906 KASSERT(((va >= virtual_avail) && 1907 (va <= VM_MAX_KERNEL_ADDRESS)), 1908 ("mmu_booke_remove: kernel pmap, non kernel va")); 1909 } else { 1910 KASSERT((va <= VM_MAXUSER_ADDRESS), 1911 ("mmu_booke_remove: user pmap, non user va")); 1912 } 1913 1914 if (PMAP_REMOVE_DONE(pmap)) { 1915 //debugf("mmu_booke_remove: e (empty)\n"); 1916 return; 1917 } 1918 1919 hold_flag = PTBL_HOLD_FLAG(pmap); 1920 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1921 1922 rw_wlock(&pvh_global_lock); 1923 PMAP_LOCK(pmap); 1924 for (; va < endva; va += PAGE_SIZE) { 1925 pte = pte_find(mmu, pmap, va); 1926 if ((pte != NULL) && PTE_ISVALID(pte)) 1927 pte_remove(mmu, pmap, va, hold_flag); 1928 } 1929 PMAP_UNLOCK(pmap); 1930 rw_wunlock(&pvh_global_lock); 1931 1932 //debugf("mmu_booke_remove: e\n"); 1933 } 1934 1935 /* 1936 * Remove physical page from all pmaps in which it resides. 1937 */ 1938 static void 1939 mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1940 { 1941 pv_entry_t pv, pvn; 1942 uint8_t hold_flag; 1943 1944 rw_wlock(&pvh_global_lock); 1945 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1946 pvn = TAILQ_NEXT(pv, pv_link); 1947 1948 PMAP_LOCK(pv->pv_pmap); 1949 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1950 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1951 PMAP_UNLOCK(pv->pv_pmap); 1952 } 1953 vm_page_aflag_clear(m, PGA_WRITEABLE); 1954 rw_wunlock(&pvh_global_lock); 1955 } 1956 1957 /* 1958 * Map a range of physical addresses into kernel virtual address space. 1959 */ 1960 static vm_offset_t 1961 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1962 vm_paddr_t pa_end, int prot) 1963 { 1964 vm_offset_t sva = *virt; 1965 vm_offset_t va = sva; 1966 1967 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1968 // sva, pa_start, pa_end); 1969 1970 while (pa_start < pa_end) { 1971 mmu_booke_kenter(mmu, va, pa_start); 1972 va += PAGE_SIZE; 1973 pa_start += PAGE_SIZE; 1974 } 1975 *virt = va; 1976 1977 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1978 return (sva); 1979 } 1980 1981 /* 1982 * The pmap must be activated before it's address space can be accessed in any 1983 * way. 1984 */ 1985 static void 1986 mmu_booke_activate(mmu_t mmu, struct thread *td) 1987 { 1988 pmap_t pmap; 1989 u_int cpuid; 1990 1991 pmap = &td->td_proc->p_vmspace->vm_pmap; 1992 1993 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1994 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1995 1996 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1997 1998 sched_pin(); 1999 2000 cpuid = PCPU_GET(cpuid); 2001 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 2002 PCPU_SET(curpmap, pmap); 2003 2004 if (pmap->pm_tid[cpuid] == TID_NONE) 2005 tid_alloc(pmap); 2006 2007 /* Load PID0 register with pmap tid value. */ 2008 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 2009 __asm __volatile("isync"); 2010 2011 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0); 2012 2013 sched_unpin(); 2014 2015 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 2016 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 2017 } 2018 2019 /* 2020 * Deactivate the specified process's address space. 2021 */ 2022 static void 2023 mmu_booke_deactivate(mmu_t mmu, struct thread *td) 2024 { 2025 pmap_t pmap; 2026 2027 pmap = &td->td_proc->p_vmspace->vm_pmap; 2028 2029 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 2030 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 2031 2032 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); 2033 2034 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 2035 PCPU_SET(curpmap, NULL); 2036 } 2037 2038 /* 2039 * Copy the range specified by src_addr/len 2040 * from the source map to the range dst_addr/len 2041 * in the destination map. 2042 * 2043 * This routine is only advisory and need not do anything. 2044 */ 2045 static void 2046 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 2047 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 2048 { 2049 2050 } 2051 2052 /* 2053 * Set the physical protection on the specified range of this map as requested. 2054 */ 2055 static void 2056 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 2057 vm_prot_t prot) 2058 { 2059 vm_offset_t va; 2060 vm_page_t m; 2061 pte_t *pte; 2062 2063 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2064 mmu_booke_remove(mmu, pmap, sva, eva); 2065 return; 2066 } 2067 2068 if (prot & VM_PROT_WRITE) 2069 return; 2070 2071 PMAP_LOCK(pmap); 2072 for (va = sva; va < eva; va += PAGE_SIZE) { 2073 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2074 if (PTE_ISVALID(pte)) { 2075 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2076 2077 mtx_lock_spin(&tlbivax_mutex); 2078 tlb_miss_lock(); 2079 2080 /* Handle modified pages. */ 2081 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 2082 vm_page_dirty(m); 2083 2084 tlb0_flush_entry(va); 2085 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2086 2087 tlb_miss_unlock(); 2088 mtx_unlock_spin(&tlbivax_mutex); 2089 } 2090 } 2091 } 2092 PMAP_UNLOCK(pmap); 2093 } 2094 2095 /* 2096 * Clear the write and modified bits in each of the given page's mappings. 2097 */ 2098 static void 2099 mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 2100 { 2101 pv_entry_t pv; 2102 pte_t *pte; 2103 2104 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2105 ("mmu_booke_remove_write: page %p is not managed", m)); 2106 2107 /* 2108 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2109 * set by another thread while the object is locked. Thus, 2110 * if PGA_WRITEABLE is clear, no page table entries need updating. 2111 */ 2112 VM_OBJECT_ASSERT_WLOCKED(m->object); 2113 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2114 return; 2115 rw_wlock(&pvh_global_lock); 2116 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2117 PMAP_LOCK(pv->pv_pmap); 2118 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2119 if (PTE_ISVALID(pte)) { 2120 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2121 2122 mtx_lock_spin(&tlbivax_mutex); 2123 tlb_miss_lock(); 2124 2125 /* Handle modified pages. */ 2126 if (PTE_ISMODIFIED(pte)) 2127 vm_page_dirty(m); 2128 2129 /* Flush mapping from TLB0. */ 2130 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 2131 2132 tlb_miss_unlock(); 2133 mtx_unlock_spin(&tlbivax_mutex); 2134 } 2135 } 2136 PMAP_UNLOCK(pv->pv_pmap); 2137 } 2138 vm_page_aflag_clear(m, PGA_WRITEABLE); 2139 rw_wunlock(&pvh_global_lock); 2140 } 2141 2142 static void 2143 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 2144 { 2145 pte_t *pte; 2146 pmap_t pmap; 2147 vm_page_t m; 2148 vm_offset_t addr; 2149 vm_paddr_t pa = 0; 2150 int active, valid; 2151 2152 va = trunc_page(va); 2153 sz = round_page(sz); 2154 2155 rw_wlock(&pvh_global_lock); 2156 pmap = PCPU_GET(curpmap); 2157 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2158 while (sz > 0) { 2159 PMAP_LOCK(pm); 2160 pte = pte_find(mmu, pm, va); 2161 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2162 if (valid) 2163 pa = PTE_PA(pte); 2164 PMAP_UNLOCK(pm); 2165 if (valid) { 2166 if (!active) { 2167 /* Create a mapping in the active pmap. */ 2168 addr = 0; 2169 m = PHYS_TO_VM_PAGE(pa); 2170 PMAP_LOCK(pmap); 2171 pte_enter(mmu, pmap, m, addr, 2172 PTE_SR | PTE_VALID | PTE_UR, FALSE); 2173 __syncicache((void *)addr, PAGE_SIZE); 2174 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2175 PMAP_UNLOCK(pmap); 2176 } else 2177 __syncicache((void *)va, PAGE_SIZE); 2178 } 2179 va += PAGE_SIZE; 2180 sz -= PAGE_SIZE; 2181 } 2182 rw_wunlock(&pvh_global_lock); 2183 } 2184 2185 /* 2186 * Atomically extract and hold the physical page with the given 2187 * pmap and virtual address pair if that mapping permits the given 2188 * protection. 2189 */ 2190 static vm_page_t 2191 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2192 vm_prot_t prot) 2193 { 2194 pte_t *pte; 2195 vm_page_t m; 2196 uint32_t pte_wbit; 2197 vm_paddr_t pa; 2198 2199 m = NULL; 2200 pa = 0; 2201 PMAP_LOCK(pmap); 2202 retry: 2203 pte = pte_find(mmu, pmap, va); 2204 if ((pte != NULL) && PTE_ISVALID(pte)) { 2205 if (pmap == kernel_pmap) 2206 pte_wbit = PTE_SW; 2207 else 2208 pte_wbit = PTE_UW; 2209 2210 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2211 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2212 goto retry; 2213 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2214 vm_page_hold(m); 2215 } 2216 } 2217 2218 PA_UNLOCK_COND(pa); 2219 PMAP_UNLOCK(pmap); 2220 return (m); 2221 } 2222 2223 /* 2224 * Initialize a vm_page's machine-dependent fields. 2225 */ 2226 static void 2227 mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2228 { 2229 2230 TAILQ_INIT(&m->md.pv_list); 2231 } 2232 2233 /* 2234 * mmu_booke_zero_page_area zeros the specified hardware page by 2235 * mapping it into virtual memory and using bzero to clear 2236 * its contents. 2237 * 2238 * off and size must reside within a single page. 2239 */ 2240 static void 2241 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2242 { 2243 vm_offset_t va; 2244 2245 /* XXX KASSERT off and size are within a single page? */ 2246 2247 mtx_lock(&zero_page_mutex); 2248 va = zero_page_va; 2249 2250 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2251 bzero((caddr_t)va + off, size); 2252 mmu_booke_kremove(mmu, va); 2253 2254 mtx_unlock(&zero_page_mutex); 2255 } 2256 2257 /* 2258 * mmu_booke_zero_page zeros the specified hardware page. 2259 */ 2260 static void 2261 mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2262 { 2263 vm_offset_t off, va; 2264 2265 mtx_lock(&zero_page_mutex); 2266 va = zero_page_va; 2267 2268 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2269 for (off = 0; off < PAGE_SIZE; off += cacheline_size) 2270 __asm __volatile("dcbz 0,%0" :: "r"(va + off)); 2271 mmu_booke_kremove(mmu, va); 2272 2273 mtx_unlock(&zero_page_mutex); 2274 } 2275 2276 /* 2277 * mmu_booke_copy_page copies the specified (machine independent) page by 2278 * mapping the page into virtual memory and using memcopy to copy the page, 2279 * one machine dependent page at a time. 2280 */ 2281 static void 2282 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2283 { 2284 vm_offset_t sva, dva; 2285 2286 sva = copy_page_src_va; 2287 dva = copy_page_dst_va; 2288 2289 mtx_lock(©_page_mutex); 2290 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2291 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2292 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2293 mmu_booke_kremove(mmu, dva); 2294 mmu_booke_kremove(mmu, sva); 2295 mtx_unlock(©_page_mutex); 2296 } 2297 2298 static inline void 2299 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2300 vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2301 { 2302 void *a_cp, *b_cp; 2303 vm_offset_t a_pg_offset, b_pg_offset; 2304 int cnt; 2305 2306 mtx_lock(©_page_mutex); 2307 while (xfersize > 0) { 2308 a_pg_offset = a_offset & PAGE_MASK; 2309 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2310 mmu_booke_kenter(mmu, copy_page_src_va, 2311 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2312 a_cp = (char *)copy_page_src_va + a_pg_offset; 2313 b_pg_offset = b_offset & PAGE_MASK; 2314 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2315 mmu_booke_kenter(mmu, copy_page_dst_va, 2316 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2317 b_cp = (char *)copy_page_dst_va + b_pg_offset; 2318 bcopy(a_cp, b_cp, cnt); 2319 mmu_booke_kremove(mmu, copy_page_dst_va); 2320 mmu_booke_kremove(mmu, copy_page_src_va); 2321 a_offset += cnt; 2322 b_offset += cnt; 2323 xfersize -= cnt; 2324 } 2325 mtx_unlock(©_page_mutex); 2326 } 2327 2328 static vm_offset_t 2329 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m) 2330 { 2331 vm_paddr_t paddr; 2332 vm_offset_t qaddr; 2333 uint32_t flags; 2334 pte_t *pte; 2335 2336 paddr = VM_PAGE_TO_PHYS(m); 2337 2338 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 2339 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT; 2340 flags |= PTE_PS_4KB; 2341 2342 critical_enter(); 2343 qaddr = PCPU_GET(qmap_addr); 2344 2345 pte = pte_find(mmu, kernel_pmap, qaddr); 2346 2347 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy")); 2348 2349 /* 2350 * XXX: tlbivax is broadcast to other cores, but qaddr should 2351 * not be present in other TLBs. Is there a better instruction 2352 * sequence to use? Or just forget it & use mmu_booke_kenter()... 2353 */ 2354 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK)); 2355 __asm __volatile("isync; msync"); 2356 2357 *pte = PTE_RPN_FROM_PA(paddr) | flags; 2358 2359 /* Flush the real memory from the instruction cache. */ 2360 if ((flags & (PTE_I | PTE_G)) == 0) 2361 __syncicache((void *)qaddr, PAGE_SIZE); 2362 2363 return (qaddr); 2364 } 2365 2366 static void 2367 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr) 2368 { 2369 pte_t *pte; 2370 2371 pte = pte_find(mmu, kernel_pmap, addr); 2372 2373 KASSERT(PCPU_GET(qmap_addr) == addr, 2374 ("mmu_booke_quick_remove_page: invalid address")); 2375 KASSERT(*pte != 0, 2376 ("mmu_booke_quick_remove_page: PTE not in use")); 2377 2378 *pte = 0; 2379 critical_exit(); 2380 } 2381 2382 /* 2383 * Return whether or not the specified physical page was modified 2384 * in any of physical maps. 2385 */ 2386 static boolean_t 2387 mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2388 { 2389 pte_t *pte; 2390 pv_entry_t pv; 2391 boolean_t rv; 2392 2393 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2394 ("mmu_booke_is_modified: page %p is not managed", m)); 2395 rv = FALSE; 2396 2397 /* 2398 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2399 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2400 * is clear, no PTEs can be modified. 2401 */ 2402 VM_OBJECT_ASSERT_WLOCKED(m->object); 2403 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2404 return (rv); 2405 rw_wlock(&pvh_global_lock); 2406 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2407 PMAP_LOCK(pv->pv_pmap); 2408 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2409 PTE_ISVALID(pte)) { 2410 if (PTE_ISMODIFIED(pte)) 2411 rv = TRUE; 2412 } 2413 PMAP_UNLOCK(pv->pv_pmap); 2414 if (rv) 2415 break; 2416 } 2417 rw_wunlock(&pvh_global_lock); 2418 return (rv); 2419 } 2420 2421 /* 2422 * Return whether or not the specified virtual address is eligible 2423 * for prefault. 2424 */ 2425 static boolean_t 2426 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2427 { 2428 2429 return (FALSE); 2430 } 2431 2432 /* 2433 * Return whether or not the specified physical page was referenced 2434 * in any physical maps. 2435 */ 2436 static boolean_t 2437 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2438 { 2439 pte_t *pte; 2440 pv_entry_t pv; 2441 boolean_t rv; 2442 2443 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2444 ("mmu_booke_is_referenced: page %p is not managed", m)); 2445 rv = FALSE; 2446 rw_wlock(&pvh_global_lock); 2447 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2448 PMAP_LOCK(pv->pv_pmap); 2449 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2450 PTE_ISVALID(pte)) { 2451 if (PTE_ISREFERENCED(pte)) 2452 rv = TRUE; 2453 } 2454 PMAP_UNLOCK(pv->pv_pmap); 2455 if (rv) 2456 break; 2457 } 2458 rw_wunlock(&pvh_global_lock); 2459 return (rv); 2460 } 2461 2462 /* 2463 * Clear the modify bits on the specified physical page. 2464 */ 2465 static void 2466 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2467 { 2468 pte_t *pte; 2469 pv_entry_t pv; 2470 2471 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2472 ("mmu_booke_clear_modify: page %p is not managed", m)); 2473 VM_OBJECT_ASSERT_WLOCKED(m->object); 2474 KASSERT(!vm_page_xbusied(m), 2475 ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2476 2477 /* 2478 * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2479 * If the object containing the page is locked and the page is not 2480 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2481 */ 2482 if ((m->aflags & PGA_WRITEABLE) == 0) 2483 return; 2484 rw_wlock(&pvh_global_lock); 2485 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2486 PMAP_LOCK(pv->pv_pmap); 2487 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2488 PTE_ISVALID(pte)) { 2489 mtx_lock_spin(&tlbivax_mutex); 2490 tlb_miss_lock(); 2491 2492 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2493 tlb0_flush_entry(pv->pv_va); 2494 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2495 PTE_REFERENCED); 2496 } 2497 2498 tlb_miss_unlock(); 2499 mtx_unlock_spin(&tlbivax_mutex); 2500 } 2501 PMAP_UNLOCK(pv->pv_pmap); 2502 } 2503 rw_wunlock(&pvh_global_lock); 2504 } 2505 2506 /* 2507 * Return a count of reference bits for a page, clearing those bits. 2508 * It is not necessary for every reference bit to be cleared, but it 2509 * is necessary that 0 only be returned when there are truly no 2510 * reference bits set. 2511 * 2512 * As an optimization, update the page's dirty field if a modified bit is 2513 * found while counting reference bits. This opportunistic update can be 2514 * performed at low cost and can eliminate the need for some future calls 2515 * to pmap_is_modified(). However, since this function stops after 2516 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some 2517 * dirty pages. Those dirty pages will only be detected by a future call 2518 * to pmap_is_modified(). 2519 */ 2520 static int 2521 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2522 { 2523 pte_t *pte; 2524 pv_entry_t pv; 2525 int count; 2526 2527 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2528 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2529 count = 0; 2530 rw_wlock(&pvh_global_lock); 2531 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2532 PMAP_LOCK(pv->pv_pmap); 2533 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2534 PTE_ISVALID(pte)) { 2535 if (PTE_ISMODIFIED(pte)) 2536 vm_page_dirty(m); 2537 if (PTE_ISREFERENCED(pte)) { 2538 mtx_lock_spin(&tlbivax_mutex); 2539 tlb_miss_lock(); 2540 2541 tlb0_flush_entry(pv->pv_va); 2542 *pte &= ~PTE_REFERENCED; 2543 2544 tlb_miss_unlock(); 2545 mtx_unlock_spin(&tlbivax_mutex); 2546 2547 if (++count >= PMAP_TS_REFERENCED_MAX) { 2548 PMAP_UNLOCK(pv->pv_pmap); 2549 break; 2550 } 2551 } 2552 } 2553 PMAP_UNLOCK(pv->pv_pmap); 2554 } 2555 rw_wunlock(&pvh_global_lock); 2556 return (count); 2557 } 2558 2559 /* 2560 * Clear the wired attribute from the mappings for the specified range of 2561 * addresses in the given pmap. Every valid mapping within that range must 2562 * have the wired attribute set. In contrast, invalid mappings cannot have 2563 * the wired attribute set, so they are ignored. 2564 * 2565 * The wired attribute of the page table entry is not a hardware feature, so 2566 * there is no need to invalidate any TLB entries. 2567 */ 2568 static void 2569 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2570 { 2571 vm_offset_t va; 2572 pte_t *pte; 2573 2574 PMAP_LOCK(pmap); 2575 for (va = sva; va < eva; va += PAGE_SIZE) { 2576 if ((pte = pte_find(mmu, pmap, va)) != NULL && 2577 PTE_ISVALID(pte)) { 2578 if (!PTE_ISWIRED(pte)) 2579 panic("mmu_booke_unwire: pte %p isn't wired", 2580 pte); 2581 *pte &= ~PTE_WIRED; 2582 pmap->pm_stats.wired_count--; 2583 } 2584 } 2585 PMAP_UNLOCK(pmap); 2586 2587 } 2588 2589 /* 2590 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2591 * page. This count may be changed upwards or downwards in the future; it is 2592 * only necessary that true be returned for a small subset of pmaps for proper 2593 * page aging. 2594 */ 2595 static boolean_t 2596 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2597 { 2598 pv_entry_t pv; 2599 int loops; 2600 boolean_t rv; 2601 2602 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2603 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2604 loops = 0; 2605 rv = FALSE; 2606 rw_wlock(&pvh_global_lock); 2607 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2608 if (pv->pv_pmap == pmap) { 2609 rv = TRUE; 2610 break; 2611 } 2612 if (++loops >= 16) 2613 break; 2614 } 2615 rw_wunlock(&pvh_global_lock); 2616 return (rv); 2617 } 2618 2619 /* 2620 * Return the number of managed mappings to the given physical page that are 2621 * wired. 2622 */ 2623 static int 2624 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2625 { 2626 pv_entry_t pv; 2627 pte_t *pte; 2628 int count = 0; 2629 2630 if ((m->oflags & VPO_UNMANAGED) != 0) 2631 return (count); 2632 rw_wlock(&pvh_global_lock); 2633 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2634 PMAP_LOCK(pv->pv_pmap); 2635 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2636 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2637 count++; 2638 PMAP_UNLOCK(pv->pv_pmap); 2639 } 2640 rw_wunlock(&pvh_global_lock); 2641 return (count); 2642 } 2643 2644 static int 2645 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2646 { 2647 int i; 2648 vm_offset_t va; 2649 2650 /* 2651 * This currently does not work for entries that 2652 * overlap TLB1 entries. 2653 */ 2654 for (i = 0; i < TLB1_ENTRIES; i ++) { 2655 if (tlb1_iomapped(i, pa, size, &va) == 0) 2656 return (0); 2657 } 2658 2659 return (EFAULT); 2660 } 2661 2662 void 2663 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va) 2664 { 2665 vm_paddr_t ppa; 2666 vm_offset_t ofs; 2667 vm_size_t gran; 2668 2669 /* Minidumps are based on virtual memory addresses. */ 2670 if (do_minidump) { 2671 *va = (void *)(vm_offset_t)pa; 2672 return; 2673 } 2674 2675 /* Raw physical memory dumps don't have a virtual address. */ 2676 /* We always map a 256MB page at 256M. */ 2677 gran = 256 * 1024 * 1024; 2678 ppa = rounddown2(pa, gran); 2679 ofs = pa - ppa; 2680 *va = (void *)gran; 2681 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO); 2682 2683 if (sz > (gran - ofs)) 2684 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran, 2685 _TLB_ENTRY_IO); 2686 } 2687 2688 void 2689 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va) 2690 { 2691 vm_paddr_t ppa; 2692 vm_offset_t ofs; 2693 vm_size_t gran; 2694 tlb_entry_t e; 2695 int i; 2696 2697 /* Minidumps are based on virtual memory addresses. */ 2698 /* Nothing to do... */ 2699 if (do_minidump) 2700 return; 2701 2702 for (i = 0; i < TLB1_ENTRIES; i++) { 2703 tlb1_read_entry(&e, i); 2704 if (!(e.mas1 & MAS1_VALID)) 2705 break; 2706 } 2707 2708 /* Raw physical memory dumps don't have a virtual address. */ 2709 i--; 2710 e.mas1 = 0; 2711 e.mas2 = 0; 2712 e.mas3 = 0; 2713 tlb1_write_entry(&e, i); 2714 2715 gran = 256 * 1024 * 1024; 2716 ppa = rounddown2(pa, gran); 2717 ofs = pa - ppa; 2718 if (sz > (gran - ofs)) { 2719 i--; 2720 e.mas1 = 0; 2721 e.mas2 = 0; 2722 e.mas3 = 0; 2723 tlb1_write_entry(&e, i); 2724 } 2725 } 2726 2727 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1]; 2728 2729 void 2730 mmu_booke_scan_init(mmu_t mmu) 2731 { 2732 vm_offset_t va; 2733 pte_t *pte; 2734 int i; 2735 2736 if (!do_minidump) { 2737 /* Initialize phys. segments for dumpsys(). */ 2738 memset(&dump_map, 0, sizeof(dump_map)); 2739 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions, 2740 &availmem_regions_sz); 2741 for (i = 0; i < physmem_regions_sz; i++) { 2742 dump_map[i].pa_start = physmem_regions[i].mr_start; 2743 dump_map[i].pa_size = physmem_regions[i].mr_size; 2744 } 2745 return; 2746 } 2747 2748 /* Virtual segments for minidumps: */ 2749 memset(&dump_map, 0, sizeof(dump_map)); 2750 2751 /* 1st: kernel .data and .bss. */ 2752 dump_map[0].pa_start = trunc_page((uintptr_t)_etext); 2753 dump_map[0].pa_size = 2754 round_page((uintptr_t)_end) - dump_map[0].pa_start; 2755 2756 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2757 dump_map[1].pa_start = data_start; 2758 dump_map[1].pa_size = data_end - data_start; 2759 2760 /* 3rd: kernel VM. */ 2761 va = dump_map[1].pa_start + dump_map[1].pa_size; 2762 /* Find start of next chunk (from va). */ 2763 while (va < virtual_end) { 2764 /* Don't dump the buffer cache. */ 2765 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) { 2766 va = kmi.buffer_eva; 2767 continue; 2768 } 2769 pte = pte_find(mmu, kernel_pmap, va); 2770 if (pte != NULL && PTE_ISVALID(pte)) 2771 break; 2772 va += PAGE_SIZE; 2773 } 2774 if (va < virtual_end) { 2775 dump_map[2].pa_start = va; 2776 va += PAGE_SIZE; 2777 /* Find last page in chunk. */ 2778 while (va < virtual_end) { 2779 /* Don't run into the buffer cache. */ 2780 if (va == kmi.buffer_sva) 2781 break; 2782 pte = pte_find(mmu, kernel_pmap, va); 2783 if (pte == NULL || !PTE_ISVALID(pte)) 2784 break; 2785 va += PAGE_SIZE; 2786 } 2787 dump_map[2].pa_size = va - dump_map[2].pa_start; 2788 } 2789 } 2790 2791 /* 2792 * Map a set of physical memory pages into the kernel virtual address space. 2793 * Return a pointer to where it is mapped. This routine is intended to be used 2794 * for mapping device memory, NOT real memory. 2795 */ 2796 static void * 2797 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2798 { 2799 2800 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT)); 2801 } 2802 2803 static void * 2804 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma) 2805 { 2806 tlb_entry_t e; 2807 void *res; 2808 uintptr_t va, tmpva; 2809 vm_size_t sz; 2810 int i; 2811 2812 /* 2813 * Check if this is premapped in TLB1. Note: this should probably also 2814 * check whether a sequence of TLB1 entries exist that match the 2815 * requirement, but now only checks the easy case. 2816 */ 2817 if (ma == VM_MEMATTR_DEFAULT) { 2818 for (i = 0; i < TLB1_ENTRIES; i++) { 2819 tlb1_read_entry(&e, i); 2820 if (!(e.mas1 & MAS1_VALID)) 2821 continue; 2822 if (pa >= e.phys && 2823 (pa + size) <= (e.phys + e.size)) 2824 return (void *)(e.virt + 2825 (vm_offset_t)(pa - e.phys)); 2826 } 2827 } 2828 2829 size = roundup(size, PAGE_SIZE); 2830 2831 /* 2832 * The device mapping area is between VM_MAXUSER_ADDRESS and 2833 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing. 2834 */ 2835 #ifdef SPARSE_MAPDEV 2836 /* 2837 * With a sparse mapdev, align to the largest starting region. This 2838 * could feasibly be optimized for a 'best-fit' alignment, but that 2839 * calculation could be very costly. 2840 */ 2841 do { 2842 tmpva = tlb1_map_base; 2843 va = roundup(tlb1_map_base, 1 << flsl(size)); 2844 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size)); 2845 #else 2846 va = atomic_fetchadd_int(&tlb1_map_base, size); 2847 #endif 2848 res = (void *)va; 2849 2850 do { 2851 sz = 1 << (ilog2(size) & ~1); 2852 if (va % sz != 0) { 2853 do { 2854 sz >>= 2; 2855 } while (va % sz != 0); 2856 } 2857 if (bootverbose) 2858 printf("Wiring VA=%x to PA=%jx (size=%x)\n", 2859 va, (uintmax_t)pa, sz); 2860 tlb1_set_entry(va, pa, sz, 2861 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)); 2862 size -= sz; 2863 pa += sz; 2864 va += sz; 2865 } while (size > 0); 2866 2867 return (res); 2868 } 2869 2870 /* 2871 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2872 */ 2873 static void 2874 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2875 { 2876 #ifdef SUPPORTS_SHRINKING_TLB1 2877 vm_offset_t base, offset; 2878 2879 /* 2880 * Unmap only if this is inside kernel virtual space. 2881 */ 2882 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2883 base = trunc_page(va); 2884 offset = va & PAGE_MASK; 2885 size = roundup(offset + size, PAGE_SIZE); 2886 kva_free(base, size); 2887 } 2888 #endif 2889 } 2890 2891 /* 2892 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2893 * specified pmap. This eliminates the blast of soft faults on process startup 2894 * and immediately after an mmap. 2895 */ 2896 static void 2897 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2898 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2899 { 2900 2901 VM_OBJECT_ASSERT_WLOCKED(object); 2902 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2903 ("mmu_booke_object_init_pt: non-device object")); 2904 } 2905 2906 /* 2907 * Perform the pmap work for mincore. 2908 */ 2909 static int 2910 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2911 vm_paddr_t *locked_pa) 2912 { 2913 2914 /* XXX: this should be implemented at some point */ 2915 return (0); 2916 } 2917 2918 static int 2919 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz, 2920 vm_memattr_t mode) 2921 { 2922 vm_offset_t va; 2923 pte_t *pte; 2924 int i, j; 2925 tlb_entry_t e; 2926 2927 /* Check TLB1 mappings */ 2928 for (i = 0; i < TLB1_ENTRIES; i++) { 2929 tlb1_read_entry(&e, i); 2930 if (!(e.mas1 & MAS1_VALID)) 2931 continue; 2932 if (addr >= e.virt && addr < e.virt + e.size) 2933 break; 2934 } 2935 if (i < TLB1_ENTRIES) { 2936 /* Only allow full mappings to be modified for now. */ 2937 /* Validate the range. */ 2938 for (j = i, va = addr; va < addr + sz; va += e.size, j++) { 2939 tlb1_read_entry(&e, j); 2940 if (va != e.virt || (sz - (va - addr) < e.size)) 2941 return (EINVAL); 2942 } 2943 for (va = addr; va < addr + sz; va += e.size, i++) { 2944 tlb1_read_entry(&e, i); 2945 e.mas2 &= ~MAS2_WIMGE_MASK; 2946 e.mas2 |= tlb_calc_wimg(e.phys, mode); 2947 2948 /* 2949 * Write it out to the TLB. Should really re-sync with other 2950 * cores. 2951 */ 2952 tlb1_write_entry(&e, i); 2953 } 2954 return (0); 2955 } 2956 2957 /* Not in TLB1, try through pmap */ 2958 /* First validate the range. */ 2959 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2960 pte = pte_find(mmu, kernel_pmap, va); 2961 if (pte == NULL || !PTE_ISVALID(pte)) 2962 return (EINVAL); 2963 } 2964 2965 mtx_lock_spin(&tlbivax_mutex); 2966 tlb_miss_lock(); 2967 for (va = addr; va < addr + sz; va += PAGE_SIZE) { 2968 pte = pte_find(mmu, kernel_pmap, va); 2969 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT); 2970 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT; 2971 tlb0_flush_entry(va); 2972 } 2973 tlb_miss_unlock(); 2974 mtx_unlock_spin(&tlbivax_mutex); 2975 2976 return (0); 2977 } 2978 2979 /**************************************************************************/ 2980 /* TID handling */ 2981 /**************************************************************************/ 2982 2983 /* 2984 * Allocate a TID. If necessary, steal one from someone else. 2985 * The new TID is flushed from the TLB before returning. 2986 */ 2987 static tlbtid_t 2988 tid_alloc(pmap_t pmap) 2989 { 2990 tlbtid_t tid; 2991 int thiscpu; 2992 2993 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2994 2995 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2996 2997 thiscpu = PCPU_GET(cpuid); 2998 2999 tid = PCPU_GET(tid_next); 3000 if (tid > TID_MAX) 3001 tid = TID_MIN; 3002 PCPU_SET(tid_next, tid + 1); 3003 3004 /* If we are stealing TID then clear the relevant pmap's field */ 3005 if (tidbusy[thiscpu][tid] != NULL) { 3006 3007 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 3008 3009 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 3010 3011 /* Flush all entries from TLB0 matching this TID. */ 3012 tid_flush(tid); 3013 } 3014 3015 tidbusy[thiscpu][tid] = pmap; 3016 pmap->pm_tid[thiscpu] = tid; 3017 __asm __volatile("msync; isync"); 3018 3019 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 3020 PCPU_GET(tid_next)); 3021 3022 return (tid); 3023 } 3024 3025 /**************************************************************************/ 3026 /* TLB0 handling */ 3027 /**************************************************************************/ 3028 3029 static void 3030 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 3031 uint32_t mas7) 3032 { 3033 int as; 3034 char desc[3]; 3035 tlbtid_t tid; 3036 vm_size_t size; 3037 unsigned int tsize; 3038 3039 desc[2] = '\0'; 3040 if (mas1 & MAS1_VALID) 3041 desc[0] = 'V'; 3042 else 3043 desc[0] = ' '; 3044 3045 if (mas1 & MAS1_IPROT) 3046 desc[1] = 'P'; 3047 else 3048 desc[1] = ' '; 3049 3050 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 3051 tid = MAS1_GETTID(mas1); 3052 3053 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3054 size = 0; 3055 if (tsize) 3056 size = tsize2size(tsize); 3057 3058 debugf("%3d: (%s) [AS=%d] " 3059 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 3060 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 3061 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 3062 } 3063 3064 /* Convert TLB0 va and way number to tlb0[] table index. */ 3065 static inline unsigned int 3066 tlb0_tableidx(vm_offset_t va, unsigned int way) 3067 { 3068 unsigned int idx; 3069 3070 idx = (way * TLB0_ENTRIES_PER_WAY); 3071 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 3072 return (idx); 3073 } 3074 3075 /* 3076 * Invalidate TLB0 entry. 3077 */ 3078 static inline void 3079 tlb0_flush_entry(vm_offset_t va) 3080 { 3081 3082 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 3083 3084 mtx_assert(&tlbivax_mutex, MA_OWNED); 3085 3086 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 3087 __asm __volatile("isync; msync"); 3088 __asm __volatile("tlbsync; msync"); 3089 3090 CTR1(KTR_PMAP, "%s: e", __func__); 3091 } 3092 3093 /* Print out contents of the MAS registers for each TLB0 entry */ 3094 void 3095 tlb0_print_tlbentries(void) 3096 { 3097 uint32_t mas0, mas1, mas2, mas3, mas7; 3098 int entryidx, way, idx; 3099 3100 debugf("TLB0 entries:\n"); 3101 for (way = 0; way < TLB0_WAYS; way ++) 3102 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 3103 3104 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3105 mtspr(SPR_MAS0, mas0); 3106 __asm __volatile("isync"); 3107 3108 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 3109 mtspr(SPR_MAS2, mas2); 3110 3111 __asm __volatile("isync; tlbre"); 3112 3113 mas1 = mfspr(SPR_MAS1); 3114 mas2 = mfspr(SPR_MAS2); 3115 mas3 = mfspr(SPR_MAS3); 3116 mas7 = mfspr(SPR_MAS7); 3117 3118 idx = tlb0_tableidx(mas2, way); 3119 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 3120 } 3121 } 3122 3123 /**************************************************************************/ 3124 /* TLB1 handling */ 3125 /**************************************************************************/ 3126 3127 /* 3128 * TLB1 mapping notes: 3129 * 3130 * TLB1[0] Kernel text and data. 3131 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI 3132 * windows, other devices mappings. 3133 */ 3134 3135 /* 3136 * Read an entry from given TLB1 slot. 3137 */ 3138 void 3139 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot) 3140 { 3141 uint32_t mas0; 3142 3143 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__)); 3144 3145 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot); 3146 mtspr(SPR_MAS0, mas0); 3147 __asm __volatile("isync; tlbre"); 3148 3149 entry->mas1 = mfspr(SPR_MAS1); 3150 entry->mas2 = mfspr(SPR_MAS2); 3151 entry->mas3 = mfspr(SPR_MAS3); 3152 3153 switch ((mfpvr() >> 16) & 0xFFFF) { 3154 case FSL_E500v2: 3155 case FSL_E500mc: 3156 case FSL_E5500: 3157 case FSL_E6500: 3158 entry->mas7 = mfspr(SPR_MAS7); 3159 break; 3160 default: 3161 entry->mas7 = 0; 3162 break; 3163 } 3164 3165 entry->virt = entry->mas2 & MAS2_EPN_MASK; 3166 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) | 3167 (entry->mas3 & MAS3_RPN); 3168 entry->size = 3169 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT); 3170 } 3171 3172 /* 3173 * Write given entry to TLB1 hardware. 3174 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 3175 */ 3176 static void 3177 tlb1_write_entry(tlb_entry_t *e, unsigned int idx) 3178 { 3179 uint32_t mas0; 3180 3181 //debugf("tlb1_write_entry: s\n"); 3182 3183 /* Select entry */ 3184 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 3185 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 3186 3187 mtspr(SPR_MAS0, mas0); 3188 __asm __volatile("isync"); 3189 mtspr(SPR_MAS1, e->mas1); 3190 __asm __volatile("isync"); 3191 mtspr(SPR_MAS2, e->mas2); 3192 __asm __volatile("isync"); 3193 mtspr(SPR_MAS3, e->mas3); 3194 __asm __volatile("isync"); 3195 switch ((mfpvr() >> 16) & 0xFFFF) { 3196 case FSL_E500mc: 3197 case FSL_E5500: 3198 case FSL_E6500: 3199 mtspr(SPR_MAS8, 0); 3200 __asm __volatile("isync"); 3201 /* FALLTHROUGH */ 3202 case FSL_E500v2: 3203 mtspr(SPR_MAS7, e->mas7); 3204 __asm __volatile("isync"); 3205 break; 3206 default: 3207 break; 3208 } 3209 3210 __asm __volatile("tlbwe; isync; msync"); 3211 3212 //debugf("tlb1_write_entry: e\n"); 3213 } 3214 3215 /* 3216 * Return the largest uint value log such that 2^log <= num. 3217 */ 3218 static unsigned int 3219 ilog2(unsigned int num) 3220 { 3221 int lz; 3222 3223 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 3224 return (31 - lz); 3225 } 3226 3227 /* 3228 * Convert TLB TSIZE value to mapped region size. 3229 */ 3230 static vm_size_t 3231 tsize2size(unsigned int tsize) 3232 { 3233 3234 /* 3235 * size = 4^tsize KB 3236 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 3237 */ 3238 3239 return ((1 << (2 * tsize)) * 1024); 3240 } 3241 3242 /* 3243 * Convert region size (must be power of 4) to TLB TSIZE value. 3244 */ 3245 static unsigned int 3246 size2tsize(vm_size_t size) 3247 { 3248 3249 return (ilog2(size) / 2 - 5); 3250 } 3251 3252 /* 3253 * Register permanent kernel mapping in TLB1. 3254 * 3255 * Entries are created starting from index 0 (current free entry is 3256 * kept in tlb1_idx) and are not supposed to be invalidated. 3257 */ 3258 int 3259 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size, 3260 uint32_t flags) 3261 { 3262 tlb_entry_t e; 3263 uint32_t ts, tid; 3264 int tsize, index; 3265 3266 for (index = 0; index < TLB1_ENTRIES; index++) { 3267 tlb1_read_entry(&e, index); 3268 if ((e.mas1 & MAS1_VALID) == 0) 3269 break; 3270 /* Check if we're just updating the flags, and update them. */ 3271 if (e.phys == pa && e.virt == va && e.size == size) { 3272 e.mas2 = (va & MAS2_EPN_MASK) | flags; 3273 tlb1_write_entry(&e, index); 3274 return (0); 3275 } 3276 } 3277 if (index >= TLB1_ENTRIES) { 3278 printf("tlb1_set_entry: TLB1 full!\n"); 3279 return (-1); 3280 } 3281 3282 /* Convert size to TSIZE */ 3283 tsize = size2tsize(size); 3284 3285 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 3286 /* XXX TS is hard coded to 0 for now as we only use single address space */ 3287 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 3288 3289 e.phys = pa; 3290 e.virt = va; 3291 e.size = size; 3292 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 3293 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 3294 e.mas2 = (va & MAS2_EPN_MASK) | flags; 3295 3296 /* Set supervisor RWX permission bits */ 3297 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 3298 e.mas7 = (pa >> 32) & MAS7_RPN; 3299 3300 tlb1_write_entry(&e, index); 3301 3302 /* 3303 * XXX in general TLB1 updates should be propagated between CPUs, 3304 * since current design assumes to have the same TLB1 set-up on all 3305 * cores. 3306 */ 3307 return (0); 3308 } 3309 3310 /* 3311 * Map in contiguous RAM region into the TLB1 using maximum of 3312 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 3313 * 3314 * If necessary round up last entry size and return total size 3315 * used by all allocated entries. 3316 */ 3317 vm_size_t 3318 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 3319 { 3320 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 3321 vm_size_t mapped, pgsz, base, mask; 3322 int idx, nents; 3323 3324 /* Round up to the next 1M */ 3325 size = roundup2(size, 1 << 20); 3326 3327 mapped = 0; 3328 idx = 0; 3329 base = va; 3330 pgsz = 64*1024*1024; 3331 while (mapped < size) { 3332 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3333 while (pgsz > (size - mapped)) 3334 pgsz >>= 2; 3335 pgs[idx++] = pgsz; 3336 mapped += pgsz; 3337 } 3338 3339 /* We under-map. Correct for this. */ 3340 if (mapped < size) { 3341 while (pgs[idx - 1] == pgsz) { 3342 idx--; 3343 mapped -= pgsz; 3344 } 3345 /* XXX We may increase beyond out starting point. */ 3346 pgsz <<= 2; 3347 pgs[idx++] = pgsz; 3348 mapped += pgsz; 3349 } 3350 } 3351 3352 nents = idx; 3353 mask = pgs[0] - 1; 3354 /* Align address to the boundary */ 3355 if (va & mask) { 3356 va = (va + mask) & ~mask; 3357 pa = (pa + mask) & ~mask; 3358 } 3359 3360 for (idx = 0; idx < nents; idx++) { 3361 pgsz = pgs[idx]; 3362 debugf("%u: %llx -> %x, size=%x\n", idx, pa, va, pgsz); 3363 tlb1_set_entry(va, pa, pgsz, 3364 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM); 3365 pa += pgsz; 3366 va += pgsz; 3367 } 3368 3369 mapped = (va - base); 3370 #ifdef __powerpc64__ 3371 printf("mapped size 0x%016lx (wasted space 0x%16lx)\n", 3372 #else 3373 printf("mapped size 0x%08x (wasted space 0x%08x)\n", 3374 #endif 3375 mapped, mapped - size); 3376 return (mapped); 3377 } 3378 3379 /* 3380 * TLB1 initialization routine, to be called after the very first 3381 * assembler level setup done in locore.S. 3382 */ 3383 void 3384 tlb1_init() 3385 { 3386 uint32_t mas0, mas1, mas2, mas3, mas7; 3387 uint32_t tsz; 3388 3389 tlb1_get_tlbconf(); 3390 3391 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3392 mtspr(SPR_MAS0, mas0); 3393 __asm __volatile("isync; tlbre"); 3394 3395 mas1 = mfspr(SPR_MAS1); 3396 mas2 = mfspr(SPR_MAS2); 3397 mas3 = mfspr(SPR_MAS3); 3398 mas7 = mfspr(SPR_MAS7); 3399 3400 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) | 3401 (mas3 & MAS3_RPN); 3402 3403 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3404 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3405 3406 /* Setup TLB miss defaults */ 3407 set_mas4_defaults(); 3408 } 3409 3410 /* 3411 * pmap_early_io_unmap() should be used in short conjunction with 3412 * pmap_early_io_map(), as in the following snippet: 3413 * 3414 * x = pmap_early_io_map(...); 3415 * <do something with x> 3416 * pmap_early_io_unmap(x, size); 3417 * 3418 * And avoiding more allocations between. 3419 */ 3420 void 3421 pmap_early_io_unmap(vm_offset_t va, vm_size_t size) 3422 { 3423 int i; 3424 tlb_entry_t e; 3425 vm_size_t isize; 3426 3427 size = roundup(size, PAGE_SIZE); 3428 isize = size; 3429 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) { 3430 tlb1_read_entry(&e, i); 3431 if (!(e.mas1 & MAS1_VALID)) 3432 continue; 3433 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) { 3434 size -= e.size; 3435 e.mas1 &= ~MAS1_VALID; 3436 tlb1_write_entry(&e, i); 3437 } 3438 } 3439 if (tlb1_map_base == va + isize) 3440 tlb1_map_base -= isize; 3441 } 3442 3443 vm_offset_t 3444 pmap_early_io_map(vm_paddr_t pa, vm_size_t size) 3445 { 3446 vm_paddr_t pa_base; 3447 vm_offset_t va, sz; 3448 int i; 3449 tlb_entry_t e; 3450 3451 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!")); 3452 3453 for (i = 0; i < TLB1_ENTRIES; i++) { 3454 tlb1_read_entry(&e, i); 3455 if (!(e.mas1 & MAS1_VALID)) 3456 continue; 3457 if (pa >= e.phys && (pa + size) <= 3458 (e.phys + e.size)) 3459 return (e.virt + (pa - e.phys)); 3460 } 3461 3462 pa_base = rounddown(pa, PAGE_SIZE); 3463 size = roundup(size + (pa - pa_base), PAGE_SIZE); 3464 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1)); 3465 va = tlb1_map_base + (pa - pa_base); 3466 3467 do { 3468 sz = 1 << (ilog2(size) & ~1); 3469 tlb1_set_entry(tlb1_map_base, pa_base, sz, 3470 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO); 3471 size -= sz; 3472 pa_base += sz; 3473 tlb1_map_base += sz; 3474 } while (size > 0); 3475 3476 return (va); 3477 } 3478 3479 void 3480 pmap_track_page(pmap_t pmap, vm_offset_t va) 3481 { 3482 vm_paddr_t pa; 3483 vm_page_t page; 3484 struct pv_entry *pve; 3485 3486 va = trunc_page(va); 3487 pa = pmap_kextract(va); 3488 3489 rw_wlock(&pvh_global_lock); 3490 PMAP_LOCK(pmap); 3491 page = PHYS_TO_VM_PAGE(pa); 3492 3493 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) { 3494 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 3495 goto out; 3496 } 3497 } 3498 page->md.pv_tracked = true; 3499 pv_insert(pmap, va, page); 3500 out: 3501 PMAP_UNLOCK(pmap); 3502 rw_wunlock(&pvh_global_lock); 3503 } 3504 3505 3506 /* 3507 * Setup MAS4 defaults. 3508 * These values are loaded to MAS0-2 on a TLB miss. 3509 */ 3510 static void 3511 set_mas4_defaults(void) 3512 { 3513 uint32_t mas4; 3514 3515 /* Defaults: TLB0, PID0, TSIZED=4K */ 3516 mas4 = MAS4_TLBSELD0; 3517 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3518 #ifdef SMP 3519 mas4 |= MAS4_MD; 3520 #endif 3521 mtspr(SPR_MAS4, mas4); 3522 __asm __volatile("isync"); 3523 } 3524 3525 /* 3526 * Print out contents of the MAS registers for each TLB1 entry 3527 */ 3528 void 3529 tlb1_print_tlbentries(void) 3530 { 3531 uint32_t mas0, mas1, mas2, mas3, mas7; 3532 int i; 3533 3534 debugf("TLB1 entries:\n"); 3535 for (i = 0; i < TLB1_ENTRIES; i++) { 3536 3537 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3538 mtspr(SPR_MAS0, mas0); 3539 3540 __asm __volatile("isync; tlbre"); 3541 3542 mas1 = mfspr(SPR_MAS1); 3543 mas2 = mfspr(SPR_MAS2); 3544 mas3 = mfspr(SPR_MAS3); 3545 mas7 = mfspr(SPR_MAS7); 3546 3547 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3548 } 3549 } 3550 3551 /* 3552 * Return 0 if the physical IO range is encompassed by one of the 3553 * the TLB1 entries, otherwise return related error code. 3554 */ 3555 static int 3556 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3557 { 3558 uint32_t prot; 3559 vm_paddr_t pa_start; 3560 vm_paddr_t pa_end; 3561 unsigned int entry_tsize; 3562 vm_size_t entry_size; 3563 tlb_entry_t e; 3564 3565 *va = (vm_offset_t)NULL; 3566 3567 tlb1_read_entry(&e, i); 3568 /* Skip invalid entries */ 3569 if (!(e.mas1 & MAS1_VALID)) 3570 return (EINVAL); 3571 3572 /* 3573 * The entry must be cache-inhibited, guarded, and r/w 3574 * so it can function as an i/o page 3575 */ 3576 prot = e.mas2 & (MAS2_I | MAS2_G); 3577 if (prot != (MAS2_I | MAS2_G)) 3578 return (EPERM); 3579 3580 prot = e.mas3 & (MAS3_SR | MAS3_SW); 3581 if (prot != (MAS3_SR | MAS3_SW)) 3582 return (EPERM); 3583 3584 /* The address should be within the entry range. */ 3585 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3586 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3587 3588 entry_size = tsize2size(entry_tsize); 3589 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) | 3590 (e.mas3 & MAS3_RPN); 3591 pa_end = pa_start + entry_size; 3592 3593 if ((pa < pa_start) || ((pa + size) > pa_end)) 3594 return (ERANGE); 3595 3596 /* Return virtual address of this mapping. */ 3597 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3598 return (0); 3599 } 3600 3601 /* 3602 * Invalidate all TLB0 entries which match the given TID. Note this is 3603 * dedicated for cases when invalidations should NOT be propagated to other 3604 * CPUs. 3605 */ 3606 static void 3607 tid_flush(tlbtid_t tid) 3608 { 3609 register_t msr; 3610 uint32_t mas0, mas1, mas2; 3611 int entry, way; 3612 3613 3614 /* Don't evict kernel translations */ 3615 if (tid == TID_KERNEL) 3616 return; 3617 3618 msr = mfmsr(); 3619 __asm __volatile("wrteei 0"); 3620 3621 for (way = 0; way < TLB0_WAYS; way++) 3622 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) { 3623 3624 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 3625 mtspr(SPR_MAS0, mas0); 3626 __asm __volatile("isync"); 3627 3628 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT; 3629 mtspr(SPR_MAS2, mas2); 3630 3631 __asm __volatile("isync; tlbre"); 3632 3633 mas1 = mfspr(SPR_MAS1); 3634 3635 if (!(mas1 & MAS1_VALID)) 3636 continue; 3637 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid) 3638 continue; 3639 mas1 &= ~MAS1_VALID; 3640 mtspr(SPR_MAS1, mas1); 3641 __asm __volatile("isync; tlbwe; isync; msync"); 3642 } 3643 mtmsr(msr); 3644 } 3645