1 /* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)fpu_div.c 8.1 (Berkeley) 6/11/93 43 */ 44 45 /* 46 * Perform an FPU divide (return x / y). 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 55 #include <machine/fpu.h> 56 57 #include <powerpc/fpu/fpu_arith.h> 58 #include <powerpc/fpu/fpu_emu.h> 59 60 /* 61 * Division of normal numbers is done as follows: 62 * 63 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e. 64 * If X and Y are the mantissas (1.bbbb's), the quotient is then: 65 * 66 * q = (X / Y) * 2^((x exponent) - (y exponent)) 67 * 68 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y) 69 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only 70 * if X < Y. In that case, it will have to be shifted left one bit to 71 * become a normal number, and the exponent decremented. Thus, the 72 * desired exponent is: 73 * 74 * left_shift = x->fp_mant < y->fp_mant; 75 * result_exp = x->fp_exp - y->fp_exp - left_shift; 76 * 77 * The quotient mantissa X/Y can then be computed one bit at a time 78 * using the following algorithm: 79 * 80 * Q = 0; -- Initial quotient. 81 * R = X; -- Initial remainder, 82 * if (left_shift) -- but fixed up in advance. 83 * R *= 2; 84 * for (bit = FP_NMANT; --bit >= 0; R *= 2) { 85 * if (R >= Y) { 86 * Q |= 1 << bit; 87 * R -= Y; 88 * } 89 * } 90 * 91 * The subtraction R -= Y always removes the uppermost bit from R (and 92 * can sometimes remove additional lower-order 1 bits); this proof is 93 * left to the reader. 94 * 95 * This loop correctly calculates the guard and round bits since they are 96 * included in the expanded internal representation. The sticky bit 97 * is to be set if and only if any other bits beyond guard and round 98 * would be set. From the above it is obvious that this is true if and 99 * only if the remainder R is nonzero when the loop terminates. 100 * 101 * Examining the loop above, we can see that the quotient Q is built 102 * one bit at a time ``from the top down''. This means that we can 103 * dispense with the multi-word arithmetic and just build it one word 104 * at a time, writing each result word when it is done. 105 * 106 * Furthermore, since X and Y are both in [1.0,2.0), we know that, 107 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and 108 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1 109 * set, and R can be set initially to either X - Y (when X >= Y) or 110 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult, 111 * so we will simply calculate R - Y and see if that underflows. 112 * This leads to the following revised version of the algorithm: 113 * 114 * R = X; 115 * bit = FP_1; 116 * D = R - Y; 117 * if (D >= 0) { 118 * result_exp = x->fp_exp - y->fp_exp; 119 * R = D; 120 * q = bit; 121 * bit >>= 1; 122 * } else { 123 * result_exp = x->fp_exp - y->fp_exp - 1; 124 * q = 0; 125 * } 126 * R <<= 1; 127 * do { 128 * D = R - Y; 129 * if (D >= 0) { 130 * q |= bit; 131 * R = D; 132 * } 133 * R <<= 1; 134 * } while ((bit >>= 1) != 0); 135 * Q[0] = q; 136 * for (i = 1; i < 4; i++) { 137 * q = 0, bit = 1 << 31; 138 * do { 139 * D = R - Y; 140 * if (D >= 0) { 141 * q |= bit; 142 * R = D; 143 * } 144 * R <<= 1; 145 * } while ((bit >>= 1) != 0); 146 * Q[i] = q; 147 * } 148 * 149 * This can be refined just a bit further by moving the `R <<= 1' 150 * calculations to the front of the do-loops and eliding the first one. 151 * The process can be terminated immediately whenever R becomes 0, but 152 * this is relatively rare, and we do not bother. 153 */ 154 155 struct fpn * 156 fpu_div(struct fpemu *fe) 157 { 158 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 159 u_int q, bit; 160 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3; 161 FPU_DECL_CARRY 162 163 /* 164 * Since divide is not commutative, we cannot just use ORDER. 165 * Check either operand for NaN first; if there is at least one, 166 * order the signalling one (if only one) onto the right, then 167 * return it. Otherwise we have the following cases: 168 * 169 * Inf / Inf = NaN, plus NV exception 170 * Inf / num = Inf [i.e., return x] 171 * Inf / 0 = Inf [i.e., return x] 172 * 0 / Inf = 0 [i.e., return x] 173 * 0 / num = 0 [i.e., return x] 174 * 0 / 0 = NaN, plus NV exception 175 * num / Inf = 0 176 * num / num = num (do the divide) 177 * num / 0 = Inf, plus DZ exception 178 */ 179 DPRINTF(FPE_REG, ("fpu_div:\n")); 180 DUMPFPN(FPE_REG, x); 181 DUMPFPN(FPE_REG, y); 182 DPRINTF(FPE_REG, ("=>\n")); 183 if (ISNAN(x) || ISNAN(y)) { 184 ORDER(x, y); 185 fe->fe_cx |= FPSCR_VXSNAN; 186 DUMPFPN(FPE_REG, y); 187 return (y); 188 } 189 /* 190 * Need to split the following out cause they generate different 191 * exceptions. 192 */ 193 if (ISINF(x)) { 194 if (x->fp_class == y->fp_class) { 195 fe->fe_cx |= FPSCR_VXIDI; 196 return (fpu_newnan(fe)); 197 } 198 DUMPFPN(FPE_REG, x); 199 return (x); 200 } 201 if (ISZERO(x)) { 202 fe->fe_cx |= FPSCR_ZX; 203 if (x->fp_class == y->fp_class) { 204 fe->fe_cx |= FPSCR_VXZDZ; 205 return (fpu_newnan(fe)); 206 } 207 DUMPFPN(FPE_REG, x); 208 return (x); 209 } 210 211 /* all results at this point use XOR of operand signs */ 212 x->fp_sign ^= y->fp_sign; 213 if (ISINF(y)) { 214 x->fp_class = FPC_ZERO; 215 DUMPFPN(FPE_REG, x); 216 return (x); 217 } 218 if (ISZERO(y)) { 219 fe->fe_cx = FPSCR_ZX; 220 x->fp_class = FPC_INF; 221 DUMPFPN(FPE_REG, x); 222 return (x); 223 } 224 225 /* 226 * Macros for the divide. See comments at top for algorithm. 227 * Note that we expand R, D, and Y here. 228 */ 229 230 #define SUBTRACT /* D = R - Y */ \ 231 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \ 232 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0) 233 234 #define NONNEGATIVE /* D >= 0 */ \ 235 ((int)d0 >= 0) 236 237 #ifdef FPU_SHL1_BY_ADD 238 #define SHL1 /* R <<= 1 */ \ 239 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \ 240 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0) 241 #else 242 #define SHL1 \ 243 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \ 244 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1 245 #endif 246 247 #define LOOP /* do ... while (bit >>= 1) */ \ 248 do { \ 249 SHL1; \ 250 SUBTRACT; \ 251 if (NONNEGATIVE) { \ 252 q |= bit; \ 253 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \ 254 } \ 255 } while ((bit >>= 1) != 0) 256 257 #define WORD(r, i) /* calculate r->fp_mant[i] */ \ 258 q = 0; \ 259 bit = 1 << 31; \ 260 LOOP; \ 261 (x)->fp_mant[i] = q 262 263 /* Setup. Note that we put our result in x. */ 264 r0 = x->fp_mant[0]; 265 r1 = x->fp_mant[1]; 266 r2 = x->fp_mant[2]; 267 r3 = x->fp_mant[3]; 268 y0 = y->fp_mant[0]; 269 y1 = y->fp_mant[1]; 270 y2 = y->fp_mant[2]; 271 y3 = y->fp_mant[3]; 272 273 bit = FP_1; 274 SUBTRACT; 275 if (NONNEGATIVE) { 276 x->fp_exp -= y->fp_exp; 277 r0 = d0, r1 = d1, r2 = d2, r3 = d3; 278 q = bit; 279 bit >>= 1; 280 } else { 281 x->fp_exp -= y->fp_exp + 1; 282 q = 0; 283 } 284 LOOP; 285 x->fp_mant[0] = q; 286 WORD(x, 1); 287 WORD(x, 2); 288 WORD(x, 3); 289 x->fp_sticky = r0 | r1 | r2 | r3; 290 291 DUMPFPN(FPE_REG, x); 292 return (x); 293 } 294