1fe48da3fSRafal Jaworowski /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 371e3c308SPedro F. Giffuni * 4fe48da3fSRafal Jaworowski * Copyright (C) 2008 Semihalf, Rafal Jaworowski 5d1d3233eSRafal Jaworowski * Copyright 2006 by Juniper Networks. 6fe48da3fSRafal Jaworowski * All rights reserved. 7fe48da3fSRafal Jaworowski * 8fe48da3fSRafal Jaworowski * Redistribution and use in source and binary forms, with or without 9fe48da3fSRafal Jaworowski * modification, are permitted provided that the following conditions 10fe48da3fSRafal Jaworowski * are met: 11fe48da3fSRafal Jaworowski * 1. Redistributions of source code must retain the above copyright 12fe48da3fSRafal Jaworowski * notice, this list of conditions and the following disclaimer. 13fe48da3fSRafal Jaworowski * 2. Redistributions in binary form must reproduce the above copyright 14fe48da3fSRafal Jaworowski * notice, this list of conditions and the following disclaimer in the 15fe48da3fSRafal Jaworowski * documentation and/or other materials provided with the distribution. 16fe48da3fSRafal Jaworowski * 17fe48da3fSRafal Jaworowski * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18fe48da3fSRafal Jaworowski * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19fe48da3fSRafal Jaworowski * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20fe48da3fSRafal Jaworowski * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21fe48da3fSRafal Jaworowski * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22fe48da3fSRafal Jaworowski * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23fe48da3fSRafal Jaworowski * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24fe48da3fSRafal Jaworowski * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25fe48da3fSRafal Jaworowski * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26fe48da3fSRafal Jaworowski * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27fe48da3fSRafal Jaworowski * SUCH DAMAGE. 28fe48da3fSRafal Jaworowski */ 29fe48da3fSRafal Jaworowski 30fe48da3fSRafal Jaworowski #ifndef _MPC85XX_H_ 31fe48da3fSRafal Jaworowski #define _MPC85XX_H_ 32fe48da3fSRafal Jaworowski 33fa7a1ca7SJustin Hibbits #include <machine/platformvar.h> 34fa7a1ca7SJustin Hibbits 35d1d3233eSRafal Jaworowski /* 36d1d3233eSRafal Jaworowski * Configuration control and status registers 37d1d3233eSRafal Jaworowski */ 3852cfe485SNathan Whitehorn extern vm_offset_t ccsrbar_va; 39b2f831c0SJustin Hibbits extern vm_paddr_t ccsrbar_pa; 40b2f831c0SJustin Hibbits extern vm_size_t ccsrbar_size; 4152cfe485SNathan Whitehorn #define CCSRBAR_VA ccsrbar_va 42d1d3233eSRafal Jaworowski #define OCP85XX_CCSRBAR (CCSRBAR_VA + 0x0) 43d1d3233eSRafal Jaworowski #define OCP85XX_BPTR (CCSRBAR_VA + 0x20) 44d1d3233eSRafal Jaworowski 453f068cbfSJustin Hibbits #define OCP85XX_BSTRH (CCSRBAR_VA + 0x20) 463f068cbfSJustin Hibbits #define OCP85XX_BSTRL (CCSRBAR_VA + 0x24) 473f068cbfSJustin Hibbits #define OCP85XX_BSTAR (CCSRBAR_VA + 0x28) 483f068cbfSJustin Hibbits 493f068cbfSJustin Hibbits #define OCP85XX_COREDISR (CCSRBAR_VA + 0xE0094) 503f068cbfSJustin Hibbits #define OCP85XX_BRR (CCSRBAR_VA + 0xE00E4) 513f068cbfSJustin Hibbits 523f068cbfSJustin Hibbits /* 533f068cbfSJustin Hibbits * Run Control and Power Management registers 543f068cbfSJustin Hibbits */ 553f068cbfSJustin Hibbits #define CCSR_CTBENR (CCSRBAR_VA + 0xE2084) 563f068cbfSJustin Hibbits #define CCSR_CTBCKSELR (CCSRBAR_VA + 0xE208C) 573f068cbfSJustin Hibbits #define CCSR_CTBCHLTCR (CCSRBAR_VA + 0xE2094) 583f068cbfSJustin Hibbits 593f068cbfSJustin Hibbits /* 603f068cbfSJustin Hibbits * DDR Memory controller. 613f068cbfSJustin Hibbits */ 623f068cbfSJustin Hibbits #define OCP85XX_DDR1_CS0_CONFIG (CCSRBAR_VA + 0x8080) 633f068cbfSJustin Hibbits 64d1d3233eSRafal Jaworowski /* 65d1d3233eSRafal Jaworowski * E500 Coherency Module registers 66d1d3233eSRafal Jaworowski */ 67d1d3233eSRafal Jaworowski #define OCP85XX_EEBPCR (CCSRBAR_VA + 0x1010) 68d1d3233eSRafal Jaworowski 69d1d3233eSRafal Jaworowski /* 70d1d3233eSRafal Jaworowski * Local access registers 71d1d3233eSRafal Jaworowski */ 725d89896cSJustin Hibbits /* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */ 735d89896cSJustin Hibbits #define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n)) 745d89896cSJustin Hibbits #define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n)) 756cedae09SJustin Hibbits #define OCP85XX_LAWSR_QORIQ(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) 765d89896cSJustin Hibbits #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) 776cedae09SJustin Hibbits #define OCP85XX_LAWSR_85XX(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n)) 786cedae09SJustin Hibbits #define OCP85XX_LAWSR(n) (mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \ 796cedae09SJustin Hibbits OCP85XX_LAWSR_85XX(n)) 80d1d3233eSRafal Jaworowski 815d89896cSJustin Hibbits /* Attribute register */ 825d89896cSJustin Hibbits #define OCP85XX_ENA_MASK 0x80000000 835d89896cSJustin Hibbits #define OCP85XX_DIS_MASK 0x7fffffff 845d89896cSJustin Hibbits 856cedae09SJustin Hibbits #define OCP85XX_TGTIF_LBC_QORIQ 0x1f 866cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM_INTL_QORIQ 0x14 876cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM1_QORIQ 0x10 886cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM2_QORIQ 0x11 895d89896cSJustin Hibbits #define OCP85XX_TGTIF_BMAN 0x18 903f068cbfSJustin Hibbits #define OCP85XX_TGTIF_DCSR 0x1D 915d89896cSJustin Hibbits #define OCP85XX_TGTIF_QMAN 0x3C 926cedae09SJustin Hibbits #define OCP85XX_TRGT_SHIFT_QORIQ 20 936cedae09SJustin Hibbits 946cedae09SJustin Hibbits #define OCP85XX_TGTIF_LBC_85XX 0x04 956cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM_INTL_85XX 0x0b 966cedae09SJustin Hibbits #define OCP85XX_TGTIF_RIO_85XX 0x0c 976cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM1_85XX 0x0f 986cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM2_85XX 0x16 996cedae09SJustin Hibbits 1006cedae09SJustin Hibbits #define OCP85XX_TGTIF_LBC \ 1016cedae09SJustin Hibbits (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX) 1026cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM_INTL \ 1036cedae09SJustin Hibbits (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX) 1046cedae09SJustin Hibbits #define OCP85XX_TGTIF_RIO \ 1056cedae09SJustin Hibbits (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX) 1066cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM1 \ 1076cedae09SJustin Hibbits (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX) 1086cedae09SJustin Hibbits #define OCP85XX_TGTIF_RAM2 \ 1096cedae09SJustin Hibbits (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX) 110d1d3233eSRafal Jaworowski 111d1d3233eSRafal Jaworowski /* 112d1d3233eSRafal Jaworowski * L2 cache registers 113d1d3233eSRafal Jaworowski */ 114d1d3233eSRafal Jaworowski #define OCP85XX_L2CTL (CCSRBAR_VA + 0x20000) 115d1d3233eSRafal Jaworowski 116d1d3233eSRafal Jaworowski /* 1173f068cbfSJustin Hibbits * L3 CoreNet platform cache (CPC) registers 1183f068cbfSJustin Hibbits */ 1193f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0 (CCSRBAR_VA + 0x10000) 1203f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0_CE 0x80000000 1213f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0_PE 0x40000000 1223f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0_FI 0x00200000 1233f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0_WT 0x00080000 1243f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0_FL 0x00000800 1253f068cbfSJustin Hibbits #define OCP85XX_CPC_CSR0_LFC 0x00000400 1263f068cbfSJustin Hibbits #define OCP85XX_CPC_CFG0 (CCSRBAR_VA + 0x10008) 1273f068cbfSJustin Hibbits #define OCP85XX_CPC_CFG_SZ_MASK 0x00003fff 1283f068cbfSJustin Hibbits #define OCP85XX_CPC_CFG0_SZ_K(x) (((x) & OCP85XX_CPC_CFG_SZ_MASK) << 6) 1293f068cbfSJustin Hibbits 1303f068cbfSJustin Hibbits /* 131d1d3233eSRafal Jaworowski * Power-On Reset configuration 132d1d3233eSRafal Jaworowski */ 133d1d3233eSRafal Jaworowski #define OCP85XX_PORDEVSR (CCSRBAR_VA + 0xe000c) 134d1d3233eSRafal Jaworowski #define OCP85XX_PORDEVSR_IO_SEL 0x00780000 135d1d3233eSRafal Jaworowski #define OCP85XX_PORDEVSR_IO_SEL_SHIFT 19 136d1d3233eSRafal Jaworowski 137d1d3233eSRafal Jaworowski #define OCP85XX_PORDEVSR2 (CCSRBAR_VA + 0xe0014) 138d1d3233eSRafal Jaworowski 139d1d3233eSRafal Jaworowski /* 140d1d3233eSRafal Jaworowski * Status Registers. 141d1d3233eSRafal Jaworowski */ 142d1d3233eSRafal Jaworowski #define OCP85XX_RSTCR (CCSRBAR_VA + 0xe00b0) 143d1d3233eSRafal Jaworowski 1441e6afa0eSJustin Hibbits #define OCP85XX_CLKDVDR (CCSRBAR_VA + 0xe0800) 1451e6afa0eSJustin Hibbits #define OCP85XX_CLKDVDR_PXCKEN 0x80000000 1461e6afa0eSJustin Hibbits #define OCP85XX_CLKDVDR_SSICKEN 0x20000000 1471e6afa0eSJustin Hibbits #define OCP85XX_CLKDVDR_PXCKINV 0x10000000 1481e6afa0eSJustin Hibbits #define OCP85XX_CLKDVDR_PXCLK_MASK 0x00FF0000 1491e6afa0eSJustin Hibbits #define OCP85XX_CLKDVDR_SSICLK_MASK 0x000000FF 1501e6afa0eSJustin Hibbits 151d1d3233eSRafal Jaworowski /* 152637f34cbSJustin Hibbits * Run Control/Power Management Registers. 153637f34cbSJustin Hibbits */ 154637f34cbSJustin Hibbits #define OCP85XX_RCPM_CDOZSR (CCSRBAR_VA + 0xe2004) 155637f34cbSJustin Hibbits #define OCP85XX_RCPM_CDOZCR (CCSRBAR_VA + 0xe200c) 156637f34cbSJustin Hibbits 157637f34cbSJustin Hibbits /* 158d1d3233eSRafal Jaworowski * Prototypes. 159d1d3233eSRafal Jaworowski */ 160fe48da3fSRafal Jaworowski uint32_t ccsr_read4(uintptr_t addr); 161fe48da3fSRafal Jaworowski void ccsr_write4(uintptr_t addr, uint32_t val); 1625d89896cSJustin Hibbits int law_enable(int trgt, uint64_t bar, uint32_t size); 1635d89896cSJustin Hibbits int law_disable(int trgt, uint64_t bar, uint32_t size); 164389e4721SRafal Jaworowski int law_getmax(void); 165d1d3233eSRafal Jaworowski int law_pci_target(struct resource *, int *, int *); 166fe48da3fSRafal Jaworowski 167fa7a1ca7SJustin Hibbits DECLARE_CLASS(mpc85xx_platform); 168fa7a1ca7SJustin Hibbits int mpc85xx_attach(platform_t); 169fa7a1ca7SJustin Hibbits 1703f068cbfSJustin Hibbits void mpc85xx_enable_l3_cache(void); 1716cedae09SJustin Hibbits int mpc85xx_is_qoriq(void); 17237ea599bSJustin Hibbits uint32_t mpc85xx_get_platform_clock(void); 173bba2d2bdSJustin Hibbits uint32_t mpc85xx_get_system_clock(void); 1743f068cbfSJustin Hibbits 175fe48da3fSRafal Jaworowski #endif /* _MPC85XX_H_ */ 176