1 /*- 2 * Copyright (c) 2008-2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/platform.h> 42 #include <machine/platformvar.h> 43 #include <machine/smp.h> 44 #include <machine/spr.h> 45 #include <machine/vmparam.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/ofw/openfirm.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 55 #include <powerpc/mpc85xx/mpc85xx.h> 56 57 #include "platform_if.h" 58 59 #ifdef SMP 60 extern void *ap_pcpu; 61 extern vm_paddr_t kernload; /* Kernel physical load address */ 62 extern uint8_t __boot_page[]; /* Boot page body */ 63 extern uint32_t bp_ntlb1s; 64 extern uint32_t bp_tlb1[]; 65 extern uint32_t bp_tlb1_end[]; 66 #endif 67 68 extern uint32_t *bootinfo; 69 vm_offset_t ccsrbar_va; 70 71 static int cpu, maxcpu; 72 73 static int mpc85xx_probe(platform_t); 74 static void mpc85xx_mem_regions(platform_t, struct mem_region *phys, 75 int *physsz, struct mem_region *avail, int *availsz); 76 static u_long mpc85xx_timebase_freq(platform_t, struct cpuref *cpuref); 77 static int mpc85xx_smp_first_cpu(platform_t, struct cpuref *cpuref); 78 static int mpc85xx_smp_next_cpu(platform_t, struct cpuref *cpuref); 79 static int mpc85xx_smp_get_bsp(platform_t, struct cpuref *cpuref); 80 static int mpc85xx_smp_start_cpu(platform_t, struct pcpu *cpu); 81 82 static void mpc85xx_reset(platform_t); 83 84 static platform_method_t mpc85xx_methods[] = { 85 PLATFORMMETHOD(platform_probe, mpc85xx_probe), 86 PLATFORMMETHOD(platform_attach, mpc85xx_attach), 87 PLATFORMMETHOD(platform_mem_regions, mpc85xx_mem_regions), 88 PLATFORMMETHOD(platform_timebase_freq, mpc85xx_timebase_freq), 89 90 PLATFORMMETHOD(platform_smp_first_cpu, mpc85xx_smp_first_cpu), 91 PLATFORMMETHOD(platform_smp_next_cpu, mpc85xx_smp_next_cpu), 92 PLATFORMMETHOD(platform_smp_get_bsp, mpc85xx_smp_get_bsp), 93 PLATFORMMETHOD(platform_smp_start_cpu, mpc85xx_smp_start_cpu), 94 95 PLATFORMMETHOD(platform_reset, mpc85xx_reset), 96 97 PLATFORMMETHOD_END 98 }; 99 100 DEFINE_CLASS_0(mpc85xx, mpc85xx_platform, mpc85xx_methods, 0); 101 102 PLATFORM_DEF(mpc85xx_platform); 103 104 static int 105 mpc85xx_probe(platform_t plat) 106 { 107 u_int pvr = mfpvr() >> 16; 108 109 if ((pvr & 0xfff0) == FSL_E500v1) 110 return (BUS_PROBE_DEFAULT); 111 112 return (ENXIO); 113 } 114 115 int 116 mpc85xx_attach(platform_t plat) 117 { 118 phandle_t cpus, child, ccsr; 119 const char *soc_name_guesses[] = {"/soc", "soc", NULL}; 120 const char **name; 121 pcell_t ranges[6], acells, pacells, scells; 122 uint32_t sr; 123 uint64_t ccsrbar, ccsrsize; 124 int i, law_max, tgt; 125 126 if ((cpus = OF_finddevice("/cpus")) != -1) { 127 for (maxcpu = 0, child = OF_child(cpus); child != 0; 128 child = OF_peer(child), maxcpu++) 129 ; 130 } else 131 maxcpu = 1; 132 133 /* 134 * Locate CCSR region. Irritatingly, there is no way to find it 135 * unless you already know where it is. Try to infer its location 136 * from the device tree. 137 */ 138 139 ccsr = -1; 140 for (name = soc_name_guesses; *name != NULL && ccsr == -1; name++) 141 ccsr = OF_finddevice(*name); 142 if (ccsr == -1) { 143 char type[64]; 144 145 /* That didn't work. Search for devices of type "soc" */ 146 child = OF_child(OF_peer(0)); 147 for (OF_child(child); child != 0; child = OF_peer(child)) { 148 if (OF_getprop(child, "device_type", type, sizeof(type)) 149 <= 0) 150 continue; 151 152 if (strcmp(type, "soc") == 0) { 153 ccsr = child; 154 break; 155 } 156 } 157 } 158 159 if (ccsr == -1) 160 panic("Could not locate CCSR window!"); 161 162 OF_getprop(ccsr, "#size-cells", &scells, sizeof(scells)); 163 OF_getprop(ccsr, "#address-cells", &acells, sizeof(acells)); 164 OF_searchprop(OF_parent(ccsr), "#address-cells", &pacells, 165 sizeof(pacells)); 166 OF_getprop(ccsr, "ranges", ranges, sizeof(ranges)); 167 ccsrbar = ccsrsize = 0; 168 for (i = acells; i < acells + pacells; i++) { 169 ccsrbar <<= 32; 170 ccsrbar |= ranges[i]; 171 } 172 for (i = acells + pacells; i < acells + pacells + scells; i++) { 173 ccsrsize <<= 32; 174 ccsrsize |= ranges[i]; 175 } 176 ccsrbar_va = pmap_early_io_map(ccsrbar, ccsrsize); 177 178 /* 179 * Clear local access windows. Skip DRAM entries, so we don't shoot 180 * ourselves in the foot. 181 */ 182 law_max = law_getmax(); 183 for (i = 0; i < law_max; i++) { 184 sr = ccsr_read4(OCP85XX_LAWSR(i)); 185 if ((sr & 0x80000000) == 0) 186 continue; 187 tgt = (sr & 0x01f00000) >> 20; 188 if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 189 tgt == OCP85XX_TGTIF_RAM_INTL) 190 continue; 191 192 ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 193 } 194 195 return (0); 196 } 197 198 void 199 mpc85xx_mem_regions(platform_t plat, struct mem_region *phys, int *physsz, 200 struct mem_region *avail, int *availsz) 201 { 202 203 ofw_mem_regions(phys, physsz, avail, availsz); 204 } 205 206 static u_long 207 mpc85xx_timebase_freq(platform_t plat, struct cpuref *cpuref) 208 { 209 u_long ticks; 210 phandle_t cpus, child; 211 pcell_t freq; 212 213 if (bootinfo != NULL) { 214 if (bootinfo[0] == 1) { 215 /* Backward compatibility. See 8-STABLE. */ 216 ticks = bootinfo[3] >> 3; 217 } else { 218 /* Compatibility with Juniper's loader. */ 219 ticks = bootinfo[5] >> 3; 220 } 221 } else 222 ticks = 0; 223 224 if ((cpus = OF_finddevice("/cpus")) == -1) 225 goto out; 226 227 if ((child = OF_child(cpus)) == 0) 228 goto out; 229 230 switch (OF_getproplen(child, "timebase-frequency")) { 231 case 4: 232 { 233 uint32_t tbase; 234 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); 235 ticks = tbase; 236 return (ticks); 237 } 238 case 8: 239 { 240 uint64_t tbase; 241 OF_getprop(child, "timebase-frequency", &tbase, sizeof(tbase)); 242 ticks = tbase; 243 return (ticks); 244 } 245 default: 246 break; 247 } 248 249 freq = 0; 250 if (OF_getprop(child, "bus-frequency", (void *)&freq, 251 sizeof(freq)) <= 0) 252 goto out; 253 254 /* 255 * Time Base and Decrementer are updated every 8 CCB bus clocks. 256 * HID0[SEL_TBCLK] = 0 257 */ 258 if (freq != 0) 259 ticks = freq / 8; 260 261 out: 262 if (ticks <= 0) 263 panic("Unable to determine timebase frequency!"); 264 265 return (ticks); 266 } 267 268 static int 269 mpc85xx_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 270 { 271 272 cpu = 0; 273 cpuref->cr_cpuid = cpu; 274 cpuref->cr_hwref = cpuref->cr_cpuid; 275 if (bootverbose) 276 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 277 cpu++; 278 279 return (0); 280 } 281 282 static int 283 mpc85xx_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 284 { 285 286 if (cpu >= maxcpu) 287 return (ENOENT); 288 289 cpuref->cr_cpuid = cpu++; 290 cpuref->cr_hwref = cpuref->cr_cpuid; 291 if (bootverbose) 292 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 293 294 return (0); 295 } 296 297 static int 298 mpc85xx_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 299 { 300 301 cpuref->cr_cpuid = mfspr(SPR_PIR); 302 cpuref->cr_hwref = cpuref->cr_cpuid; 303 304 return (0); 305 } 306 307 static int 308 mpc85xx_smp_start_cpu(platform_t plat, struct pcpu *pc) 309 { 310 #ifdef SMP 311 uint32_t *tlb1; 312 uint32_t bptr, eebpcr; 313 int i, timeout; 314 315 eebpcr = ccsr_read4(OCP85XX_EEBPCR); 316 if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) { 317 printf("SMP: CPU %d already out of hold-off state!\n", 318 pc->pc_cpuid); 319 return (ENXIO); 320 } 321 322 ap_pcpu = pc; 323 324 i = 0; 325 tlb1 = bp_tlb1; 326 while (i < bp_ntlb1s && tlb1 < bp_tlb1_end) { 327 mtspr(SPR_MAS0, MAS0_TLBSEL(1) | MAS0_ESEL(i)); 328 __asm __volatile("isync; tlbre"); 329 tlb1[0] = mfspr(SPR_MAS1); 330 tlb1[1] = mfspr(SPR_MAS2); 331 tlb1[2] = mfspr(SPR_MAS3); 332 i++; 333 tlb1 += 3; 334 } 335 if (i < bp_ntlb1s) 336 bp_ntlb1s = i; 337 338 /* 339 * Set BPTR to the physical address of the boot page 340 */ 341 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 342 KASSERT((bptr & 0xfff) == 0, 343 ("%s: boot page is not aligned (%#x)", __func__, bptr)); 344 bptr = (bptr >> 12) | 0x80000000u; 345 ccsr_write4(OCP85XX_BPTR, bptr); 346 __asm __volatile("isync; msync"); 347 348 /* Flush caches to have our changes hit DRAM. */ 349 cpu_flush_dcache(__boot_page, 4096); 350 351 /* 352 * Release AP from hold-off state 353 */ 354 eebpcr |= (1 << (pc->pc_cpuid + 24)); 355 ccsr_write4(OCP85XX_EEBPCR, eebpcr); 356 __asm __volatile("isync; msync"); 357 358 timeout = 500; 359 while (!pc->pc_awake && timeout--) 360 DELAY(1000); /* wait 1ms */ 361 362 /* 363 * Disable boot page translation so that the 4K page at the default 364 * address (= 0xfffff000) isn't permanently remapped and thus not 365 * usable otherwise. 366 */ 367 ccsr_write4(OCP85XX_BPTR, 0); 368 __asm __volatile("isync; msync"); 369 370 if (!pc->pc_awake) 371 printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid); 372 return ((pc->pc_awake) ? 0 : EBUSY); 373 #else 374 /* No SMP support */ 375 return (ENXIO); 376 #endif 377 } 378 379 static void 380 mpc85xx_reset(platform_t plat) 381 { 382 383 /* 384 * Try the dedicated reset register first. 385 * If the SoC doesn't have one, we'll fall 386 * back to using the debug control register. 387 */ 388 ccsr_write4(OCP85XX_RSTCR, 2); 389 390 /* Clear DBCR0, disables debug interrupts and events. */ 391 mtspr(SPR_DBCR0, 0); 392 __asm __volatile("isync"); 393 394 /* Enable Debug Interrupts in MSR. */ 395 mtmsr(mfmsr() | PSL_DE); 396 397 /* Enable debug interrupts and issue reset. */ 398 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 399 400 printf("Reset failed...\n"); 401 while (1) 402 ; 403 } 404 405