1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2002 Benno Rice. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 41 #include <dev/ofw/openfirm.h> 42 #include <dev/ofw/ofw_pci.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #include <dev/ofw/ofwpci.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include <machine/bus.h> 51 #include <machine/intr_machdep.h> 52 #include <machine/md_var.h> 53 #include <machine/pio.h> 54 #include <machine/resource.h> 55 56 #include <powerpc/powermac/uninorthvar.h> 57 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 61 #include "pcib_if.h" 62 63 #define UNINORTH_DEBUG 0 64 65 /* 66 * Device interface. 67 */ 68 static int uninorth_probe(device_t); 69 static int uninorth_attach(device_t); 70 71 /* 72 * pcib interface. 73 */ 74 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int, 75 u_int, int); 76 static void uninorth_write_config(device_t, u_int, u_int, u_int, 77 u_int, u_int32_t, int); 78 79 /* 80 * Local routines. 81 */ 82 static int uninorth_enable_config(struct uninorth_softc *, u_int, 83 u_int, u_int, u_int); 84 85 /* 86 * Driver methods. 87 */ 88 static device_method_t uninorth_methods[] = { 89 /* Device interface */ 90 DEVMETHOD(device_probe, uninorth_probe), 91 DEVMETHOD(device_attach, uninorth_attach), 92 93 /* pcib interface */ 94 DEVMETHOD(pcib_read_config, uninorth_read_config), 95 DEVMETHOD(pcib_write_config, uninorth_write_config), 96 97 DEVMETHOD_END 98 }; 99 100 static devclass_t uninorth_devclass; 101 102 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods, 103 sizeof(struct uninorth_softc), ofw_pci_driver); 104 DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0); 105 106 static int 107 uninorth_probe(device_t dev) 108 { 109 const char *type, *compatible; 110 111 type = ofw_bus_get_type(dev); 112 compatible = ofw_bus_get_compat(dev); 113 114 if (type == NULL || compatible == NULL) 115 return (ENXIO); 116 117 if (strcmp(type, "pci") != 0) 118 return (ENXIO); 119 120 if (strcmp(compatible, "uni-north") == 0) { 121 device_set_desc(dev, "Apple UniNorth Host-PCI bridge"); 122 return (0); 123 } else if (strcmp(compatible, "u3-agp") == 0) { 124 device_set_desc(dev, "Apple U3 Host-AGP bridge"); 125 return (0); 126 } else if (strcmp(compatible, "u4-pcie") == 0) { 127 device_set_desc(dev, "IBM CPC945 PCI Express Root"); 128 return (0); 129 } 130 131 return (ENXIO); 132 } 133 134 static int 135 uninorth_attach(device_t dev) 136 { 137 struct uninorth_softc *sc; 138 const char *compatible; 139 const char *name; 140 phandle_t node; 141 uint32_t reg[3]; 142 uint64_t regbase; 143 cell_t acells; 144 int unit; 145 146 node = ofw_bus_get_node(dev); 147 sc = device_get_softc(dev); 148 name = device_get_name(dev); 149 unit = device_get_unit(dev); 150 151 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 152 return (ENXIO); 153 154 sc->sc_ver = 0; 155 compatible = ofw_bus_get_compat(dev); 156 if (strcmp(compatible, "u3-agp") == 0) 157 sc->sc_ver = 3; 158 if (strcmp(compatible, "u4-pcie") == 0) 159 sc->sc_ver = 4; 160 161 acells = 1; 162 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells)); 163 164 regbase = reg[0]; 165 if (acells == 2) { 166 regbase <<= 32; 167 regbase |= reg[1]; 168 } 169 170 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE); 171 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE); 172 173 if (resource_int_value(name, unit, "skipslot", &sc->sc_skipslot) != 0) 174 sc->sc_skipslot = -1; 175 176 mtx_init(&sc->sc_cfg_mtx, "uninorth pcicfg", NULL, MTX_SPIN); 177 178 return (ofw_pci_attach(dev)); 179 } 180 181 static u_int32_t 182 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 183 int width) 184 { 185 struct uninorth_softc *sc; 186 vm_offset_t caoff; 187 u_int32_t val; 188 189 sc = device_get_softc(dev); 190 caoff = sc->sc_data + (reg & 0x07); 191 val = 0xffffffff; 192 193 mtx_lock_spin(&sc->sc_cfg_mtx); 194 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) { 195 switch (width) { 196 case 1: 197 val = in8rb(caoff); 198 break; 199 case 2: 200 val = in16rb(caoff); 201 break; 202 case 4: 203 val = in32rb(caoff); 204 break; 205 } 206 } 207 mtx_unlock_spin(&sc->sc_cfg_mtx); 208 209 return (val); 210 } 211 212 static void 213 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func, 214 u_int reg, u_int32_t val, int width) 215 { 216 struct uninorth_softc *sc; 217 vm_offset_t caoff; 218 219 sc = device_get_softc(dev); 220 caoff = sc->sc_data + (reg & 0x07); 221 222 mtx_lock_spin(&sc->sc_cfg_mtx); 223 if (uninorth_enable_config(sc, bus, slot, func, reg)) { 224 switch (width) { 225 case 1: 226 out8rb(caoff, val); 227 break; 228 case 2: 229 out16rb(caoff, val); 230 break; 231 case 4: 232 out32rb(caoff, val); 233 break; 234 } 235 } 236 mtx_unlock_spin(&sc->sc_cfg_mtx); 237 } 238 239 static int 240 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot, 241 u_int func, u_int reg) 242 { 243 uint32_t cfgval; 244 245 mtx_assert(&sc->sc_cfg_mtx, MA_OWNED); 246 247 if (sc->sc_skipslot == slot) 248 return (0); 249 250 /* 251 * Issue type 0 configuration space accesses for the root bus. 252 * 253 * NOTE: On U4, issue only type 1 accesses. There is a secret 254 * PCI Express <-> PCI Express bridge not present in the device tree, 255 * and we need to route all of our configuration space through it. 256 */ 257 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) { 258 /* 259 * No slots less than 11 on the primary bus on U3 and lower 260 */ 261 if (slot < 11) 262 return (0); 263 264 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc); 265 } else { 266 cfgval = (bus << 16) | (slot << 11) | (func << 8) | 267 (reg & 0xfc) | 1; 268 } 269 270 /* Set extended register bits on U4 */ 271 if (sc->sc_ver == 4) 272 cfgval |= (reg >> 8) << 28; 273 274 do { 275 out32rb(sc->sc_addr, cfgval); 276 } while (in32rb(sc->sc_addr) != cfgval); 277 278 return (1); 279 } 280 281