160727d8bSWarner Losh /*- 298f8e6c0SBenno Rice * Copyright (C) 2002 Benno Rice. 398f8e6c0SBenno Rice * All rights reserved. 498f8e6c0SBenno Rice * 598f8e6c0SBenno Rice * Redistribution and use in source and binary forms, with or without 698f8e6c0SBenno Rice * modification, are permitted provided that the following conditions 798f8e6c0SBenno Rice * are met: 898f8e6c0SBenno Rice * 1. Redistributions of source code must retain the above copyright 998f8e6c0SBenno Rice * notice, this list of conditions and the following disclaimer. 1098f8e6c0SBenno Rice * 2. Redistributions in binary form must reproduce the above copyright 1198f8e6c0SBenno Rice * notice, this list of conditions and the following disclaimer in the 1298f8e6c0SBenno Rice * documentation and/or other materials provided with the distribution. 1398f8e6c0SBenno Rice * 1498f8e6c0SBenno Rice * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 1598f8e6c0SBenno Rice * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1698f8e6c0SBenno Rice * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1798f8e6c0SBenno Rice * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 1898f8e6c0SBenno Rice * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1998f8e6c0SBenno Rice * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2098f8e6c0SBenno Rice * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2198f8e6c0SBenno Rice * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2298f8e6c0SBenno Rice * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2398f8e6c0SBenno Rice * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2498f8e6c0SBenno Rice * 2598f8e6c0SBenno Rice * $FreeBSD$ 2698f8e6c0SBenno Rice */ 2798f8e6c0SBenno Rice 2898f8e6c0SBenno Rice #ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_ 2998f8e6c0SBenno Rice #define _POWERPC_POWERMAC_UNINORTHVAR_H_ 3098f8e6c0SBenno Rice 314702d987SJustin Hibbits #include <dev/ofw/ofw_bus_subr.h> 324702d987SJustin Hibbits #include <dev/ofw/ofw_pci.h> 339a35e64eSNathan Whitehorn #include <powerpc/ofw/ofw_pci.h> 3451d163d3SNathan Whitehorn 3598f8e6c0SBenno Rice struct uninorth_softc { 369a35e64eSNathan Whitehorn struct ofw_pci_softc pci_sc; 3798f8e6c0SBenno Rice vm_offset_t sc_addr; 3898f8e6c0SBenno Rice vm_offset_t sc_data; 39ca2c1931SNathan Whitehorn int sc_ver; 4098f8e6c0SBenno Rice }; 4198f8e6c0SBenno Rice 4251478d84SPeter Grehan struct unin_chip_softc { 434ee63553SNathan Whitehorn uint64_t sc_physaddr; 444ee63553SNathan Whitehorn uint64_t sc_size; 4551478d84SPeter Grehan vm_offset_t sc_addr; 46ca2c1931SNathan Whitehorn struct rman sc_mem_rman; 4751478d84SPeter Grehan int sc_version; 4851478d84SPeter Grehan }; 4951478d84SPeter Grehan 5051478d84SPeter Grehan /* 51ca2c1931SNathan Whitehorn * Format of a unin reg property entry. 52ca2c1931SNathan Whitehorn */ 53ca2c1931SNathan Whitehorn struct unin_chip_reg { 54ca2c1931SNathan Whitehorn u_int32_t mr_base; 55ca2c1931SNathan Whitehorn u_int32_t mr_size; 56ca2c1931SNathan Whitehorn }; 57ca2c1931SNathan Whitehorn 58ca2c1931SNathan Whitehorn /* 59ca2c1931SNathan Whitehorn * Per unin device structure. 60ca2c1931SNathan Whitehorn */ 61ca2c1931SNathan Whitehorn struct unin_chip_devinfo { 62ca2c1931SNathan Whitehorn int udi_interrupts[6]; 63ca2c1931SNathan Whitehorn int udi_ninterrupts; 64ca2c1931SNathan Whitehorn int udi_base; 65ca2c1931SNathan Whitehorn struct ofw_bus_devinfo udi_obdinfo; 66ca2c1931SNathan Whitehorn struct resource_list udi_resources; 67ca2c1931SNathan Whitehorn }; 68ca2c1931SNathan Whitehorn 69ca2c1931SNathan Whitehorn /* 7051478d84SPeter Grehan * Version register 7151478d84SPeter Grehan */ 7251478d84SPeter Grehan #define UNIN_VERS 0x0 7351478d84SPeter Grehan 7451478d84SPeter Grehan /* 7551478d84SPeter Grehan * Clock-control register 7651478d84SPeter Grehan */ 7751478d84SPeter Grehan #define UNIN_CLOCKCNTL 0x20 7851478d84SPeter Grehan #define UNIN_CLOCKCNTL_GMAC 0x2 7951478d84SPeter Grehan 80ca2c1931SNathan Whitehorn /* 814702d987SJustin Hibbits * Power management register 824702d987SJustin Hibbits */ 834702d987SJustin Hibbits #define UNIN_PWR_MGMT 0x30 844702d987SJustin Hibbits #define UNIN_PWR_NORMAL 0x00 854702d987SJustin Hibbits #define UNIN_PWR_IDLE2 0x01 864702d987SJustin Hibbits #define UNIN_PWR_SLEEP 0x02 874702d987SJustin Hibbits #define UNIN_PWR_SAVE 0x03 884702d987SJustin Hibbits #define UNIN_PWR_MASK 0x03 894702d987SJustin Hibbits 904702d987SJustin Hibbits /* 914702d987SJustin Hibbits * Hardware initialization state register 924702d987SJustin Hibbits */ 934702d987SJustin Hibbits #define UNIN_HWINIT_STATE 0x70 944702d987SJustin Hibbits #define UNIN_SLEEPING 0x01 954702d987SJustin Hibbits #define UNIN_RUNNING 0x02 964702d987SJustin Hibbits 974702d987SJustin Hibbits 984702d987SJustin Hibbits /* 99ca2c1931SNathan Whitehorn * Toggle registers 100ca2c1931SNathan Whitehorn */ 101ca2c1931SNathan Whitehorn #define UNIN_TOGGLE_REG 0xe0 102ca2c1931SNathan Whitehorn #define UNIN_MPIC_RESET 0x2 103ca2c1931SNathan Whitehorn #define UNIN_MPIC_OUTPUT_ENABLE 0x4 104ca2c1931SNathan Whitehorn 1054702d987SJustin Hibbits extern int unin_chip_sleep(device_t dev, int idle); 1064702d987SJustin Hibbits extern int unin_chip_wake(device_t dev); 10798f8e6c0SBenno Rice #endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */ 108