160727d8bSWarner Losh /*- 298f8e6c0SBenno Rice * Copyright (C) 2002 Benno Rice. 398f8e6c0SBenno Rice * All rights reserved. 498f8e6c0SBenno Rice * 598f8e6c0SBenno Rice * Redistribution and use in source and binary forms, with or without 698f8e6c0SBenno Rice * modification, are permitted provided that the following conditions 798f8e6c0SBenno Rice * are met: 898f8e6c0SBenno Rice * 1. Redistributions of source code must retain the above copyright 998f8e6c0SBenno Rice * notice, this list of conditions and the following disclaimer. 1098f8e6c0SBenno Rice * 2. Redistributions in binary form must reproduce the above copyright 1198f8e6c0SBenno Rice * notice, this list of conditions and the following disclaimer in the 1298f8e6c0SBenno Rice * documentation and/or other materials provided with the distribution. 1398f8e6c0SBenno Rice * 1498f8e6c0SBenno Rice * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 1598f8e6c0SBenno Rice * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1698f8e6c0SBenno Rice * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1798f8e6c0SBenno Rice * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 1898f8e6c0SBenno Rice * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1998f8e6c0SBenno Rice * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2098f8e6c0SBenno Rice * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2198f8e6c0SBenno Rice * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2298f8e6c0SBenno Rice * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2398f8e6c0SBenno Rice * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2498f8e6c0SBenno Rice * 2598f8e6c0SBenno Rice * $FreeBSD$ 2698f8e6c0SBenno Rice */ 2798f8e6c0SBenno Rice 2898f8e6c0SBenno Rice #ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_ 2998f8e6c0SBenno Rice #define _POWERPC_POWERMAC_UNINORTHVAR_H_ 3098f8e6c0SBenno Rice 3198f8e6c0SBenno Rice struct uninorth_range { 3298f8e6c0SBenno Rice u_int32_t pci_hi; 3398f8e6c0SBenno Rice u_int32_t pci_mid; 3498f8e6c0SBenno Rice u_int32_t pci_lo; 3598f8e6c0SBenno Rice u_int32_t host; 3698f8e6c0SBenno Rice u_int32_t size_hi; 3798f8e6c0SBenno Rice u_int32_t size_lo; 3898f8e6c0SBenno Rice }; 3998f8e6c0SBenno Rice 4051d163d3SNathan Whitehorn struct uninorth_range64 { 4151d163d3SNathan Whitehorn u_int32_t pci_hi; 4251d163d3SNathan Whitehorn u_int32_t pci_mid; 4351d163d3SNathan Whitehorn u_int32_t pci_lo; 4451d163d3SNathan Whitehorn u_int32_t host_hi; 4551d163d3SNathan Whitehorn u_int32_t host_lo; 4651d163d3SNathan Whitehorn u_int32_t size_hi; 4751d163d3SNathan Whitehorn u_int32_t size_lo; 4851d163d3SNathan Whitehorn }; 4951d163d3SNathan Whitehorn 5098f8e6c0SBenno Rice struct uninorth_softc { 5198f8e6c0SBenno Rice device_t sc_dev; 5298f8e6c0SBenno Rice phandle_t sc_node; 5398f8e6c0SBenno Rice vm_offset_t sc_addr; 5498f8e6c0SBenno Rice vm_offset_t sc_data; 5598f8e6c0SBenno Rice int sc_bus; 5698f8e6c0SBenno Rice struct uninorth_range sc_range[6]; 5798f8e6c0SBenno Rice int sc_nrange; 58e237071fSAndrew Gallatin int sc_iostart; 5998f8e6c0SBenno Rice struct rman sc_io_rman; 6098f8e6c0SBenno Rice struct rman sc_mem_rman; 6198f8e6c0SBenno Rice bus_space_tag_t sc_iot; 6298f8e6c0SBenno Rice bus_space_tag_t sc_memt; 6398f8e6c0SBenno Rice bus_dma_tag_t sc_dmat; 6494b4a038SNathan Whitehorn struct ofw_bus_iinfo sc_pci_iinfo; 6551d163d3SNathan Whitehorn 66ca2c1931SNathan Whitehorn int sc_ver; 6798f8e6c0SBenno Rice }; 6898f8e6c0SBenno Rice 6951478d84SPeter Grehan struct unin_chip_softc { 70ca2c1931SNathan Whitehorn u_int32_t sc_physaddr; 7151478d84SPeter Grehan vm_offset_t sc_addr; 72ca2c1931SNathan Whitehorn u_int32_t sc_size; 73ca2c1931SNathan Whitehorn struct rman sc_mem_rman; 7451478d84SPeter Grehan int sc_version; 7551478d84SPeter Grehan }; 7651478d84SPeter Grehan 7751478d84SPeter Grehan /* 78ca2c1931SNathan Whitehorn * Format of a unin reg property entry. 79ca2c1931SNathan Whitehorn */ 80ca2c1931SNathan Whitehorn struct unin_chip_reg { 81ca2c1931SNathan Whitehorn u_int32_t mr_base; 82ca2c1931SNathan Whitehorn u_int32_t mr_size; 83ca2c1931SNathan Whitehorn }; 84ca2c1931SNathan Whitehorn 85ca2c1931SNathan Whitehorn /* 86ca2c1931SNathan Whitehorn * Per unin device structure. 87ca2c1931SNathan Whitehorn */ 88ca2c1931SNathan Whitehorn struct unin_chip_devinfo { 89ca2c1931SNathan Whitehorn int udi_interrupts[6]; 90ca2c1931SNathan Whitehorn int udi_ninterrupts; 91ca2c1931SNathan Whitehorn int udi_base; 92ca2c1931SNathan Whitehorn struct ofw_bus_devinfo udi_obdinfo; 93ca2c1931SNathan Whitehorn struct resource_list udi_resources; 94ca2c1931SNathan Whitehorn }; 95ca2c1931SNathan Whitehorn 96ca2c1931SNathan Whitehorn /* 9751478d84SPeter Grehan * Version register 9851478d84SPeter Grehan */ 9951478d84SPeter Grehan #define UNIN_VERS 0x0 10051478d84SPeter Grehan 10151478d84SPeter Grehan /* 10251478d84SPeter Grehan * Clock-control register 10351478d84SPeter Grehan */ 10451478d84SPeter Grehan #define UNIN_CLOCKCNTL 0x20 10551478d84SPeter Grehan #define UNIN_CLOCKCNTL_GMAC 0x2 10651478d84SPeter Grehan 107ca2c1931SNathan Whitehorn /* 108ca2c1931SNathan Whitehorn * Toggle registers 109ca2c1931SNathan Whitehorn */ 110ca2c1931SNathan Whitehorn #define UNIN_TOGGLE_REG 0xe0 111ca2c1931SNathan Whitehorn #define UNIN_MPIC_RESET 0x2 112ca2c1931SNathan Whitehorn #define UNIN_MPIC_OUTPUT_ENABLE 0x4 113ca2c1931SNathan Whitehorn 11498f8e6c0SBenno Rice #endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */ 115