1 /*- 2 * Copyright (c) 2015-2016 Nathan Whitehorn 3 * Copyright (c) 2017-2018 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/module.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/kernel.h> 35 #include <sys/pciio.h> 36 #include <sys/endian.h> 37 #include <sys/rman.h> 38 #include <sys/vmem.h> 39 40 #include <dev/ofw/openfirm.h> 41 #include <dev/ofw/ofw_pci.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #include <dev/ofw/ofwpci.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <machine/bus.h> 50 #include <machine/intr_machdep.h> 51 #include <machine/md_var.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 56 #include "pcib_if.h" 57 #include "pic_if.h" 58 #include "iommu_if.h" 59 #include "opal.h" 60 61 #define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL) 62 #define OPAL_PCI_TCE_DEFAULT_SEG_SIZE (16*1024*1024UL) 63 #define OPAL_PCI_TCE_R (1UL << 0) 64 #define OPAL_PCI_TCE_W (1UL << 1) 65 #define PHB3_TCE_KILL_INVAL_ALL (1UL << 63) 66 67 /* 68 * Device interface. 69 */ 70 static int opalpci_probe(device_t); 71 static int opalpci_attach(device_t); 72 73 /* 74 * pcib interface. 75 */ 76 static uint32_t opalpci_read_config(device_t, u_int, u_int, u_int, 77 u_int, int); 78 static void opalpci_write_config(device_t, u_int, u_int, u_int, 79 u_int, u_int32_t, int); 80 static int opalpci_alloc_msi(device_t dev, device_t child, 81 int count, int maxcount, int *irqs); 82 static int opalpci_release_msi(device_t dev, device_t child, 83 int count, int *irqs); 84 static int opalpci_alloc_msix(device_t dev, device_t child, 85 int *irq); 86 static int opalpci_release_msix(device_t dev, device_t child, 87 int irq); 88 static int opalpci_map_msi(device_t dev, device_t child, 89 int irq, uint64_t *addr, uint32_t *data); 90 static int opalpci_route_interrupt(device_t bus, device_t dev, int pin); 91 92 /* 93 * MSI PIC interface. 94 */ 95 static void opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **); 96 static void opalpic_pic_eoi(device_t dev, u_int irq, void *); 97 98 /* Bus interface */ 99 static bus_dma_tag_t opalpci_get_dma_tag(device_t dev, device_t child); 100 101 /* 102 * Commands 103 */ 104 #define OPAL_M32_WINDOW_TYPE 1 105 #define OPAL_M64_WINDOW_TYPE 2 106 #define OPAL_IO_WINDOW_TYPE 3 107 108 #define OPAL_RESET_PHB_COMPLETE 1 109 #define OPAL_RESET_PCI_IODA_TABLE 6 110 111 #define OPAL_DISABLE_M64 0 112 #define OPAL_ENABLE_M64_SPLIT 1 113 #define OPAL_ENABLE_M64_NON_SPLIT 2 114 115 #define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1 116 #define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2 117 #define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3 118 119 #define OPAL_EEH_STOPPED_NOT_FROZEN 0 120 121 /* 122 * Constants 123 */ 124 #define OPAL_PCI_DEFAULT_PE 1 125 126 #define OPAL_PCI_BUS_SPACE_LOWADDR_32BIT 0x7FFFFFFFUL 127 128 /* 129 * Driver methods. 130 */ 131 static device_method_t opalpci_methods[] = { 132 /* Device interface */ 133 DEVMETHOD(device_probe, opalpci_probe), 134 DEVMETHOD(device_attach, opalpci_attach), 135 136 /* pcib interface */ 137 DEVMETHOD(pcib_read_config, opalpci_read_config), 138 DEVMETHOD(pcib_write_config, opalpci_write_config), 139 140 DEVMETHOD(pcib_alloc_msi, opalpci_alloc_msi), 141 DEVMETHOD(pcib_release_msi, opalpci_release_msi), 142 DEVMETHOD(pcib_alloc_msix, opalpci_alloc_msix), 143 DEVMETHOD(pcib_release_msix, opalpci_release_msix), 144 DEVMETHOD(pcib_map_msi, opalpci_map_msi), 145 DEVMETHOD(pcib_route_interrupt, opalpci_route_interrupt), 146 147 /* PIC interface for MSIs */ 148 DEVMETHOD(pic_enable, opalpic_pic_enable), 149 DEVMETHOD(pic_eoi, opalpic_pic_eoi), 150 151 /* Bus interface */ 152 DEVMETHOD(bus_get_dma_tag, opalpci_get_dma_tag), 153 DEVMETHOD(bus_get_cpus, ofw_pcibus_get_cpus), 154 DEVMETHOD(bus_get_domain, ofw_pcibus_get_domain), 155 156 DEVMETHOD_END 157 }; 158 159 struct opalpci_softc { 160 struct ofw_pci_softc ofw_sc; 161 uint64_t phb_id; 162 vmem_t *msi_vmem; 163 int msi_base; /* Base XIVE number */ 164 int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */ 165 uint64_t *tce; /* TCE table for 1:1 mapping */ 166 struct resource *r_reg; 167 }; 168 169 DEFINE_CLASS_1(pcib, opalpci_driver, opalpci_methods, 170 sizeof(struct opalpci_softc), ofw_pcib_driver); 171 EARLY_DRIVER_MODULE(opalpci, ofwbus, opalpci_driver, 0, 0, BUS_PASS_BUS); 172 173 static int 174 opalpci_probe(device_t dev) 175 { 176 const char *type; 177 178 if (opal_check() != 0) 179 return (ENXIO); 180 181 type = ofw_bus_get_type(dev); 182 183 if (type == NULL || (strcmp(type, "pci") != 0 && 184 strcmp(type, "pciex") != 0)) 185 return (ENXIO); 186 187 if (!OF_hasprop(ofw_bus_get_node(dev), "ibm,opal-phbid")) 188 return (ENXIO); 189 190 device_set_desc(dev, "OPAL Host-PCI bridge"); 191 return (BUS_PROBE_GENERIC); 192 } 193 194 static void 195 pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc) 196 { 197 198 mb(); 199 bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL); 200 mb(); 201 } 202 203 /* Simple function to round to a power of 2 */ 204 static uint64_t 205 round_pow2(uint64_t val) 206 { 207 208 return (1 << (flsl(val + (val - 1)) - 1)); 209 } 210 211 /* 212 * Starting with skiboot 5.10 PCIe nodes have a new property, 213 * "ibm,supported-tce-sizes", to denote the TCE sizes available. This allows us 214 * to avoid hard-coding the maximum TCE size allowed, and instead provide a sane 215 * default (however, the "sane" default, which works for all targets, is 64k, 216 * limiting us to 64GB if we have 1M entries. 217 */ 218 static uint64_t 219 max_tce_size(device_t dev) 220 { 221 phandle_t node; 222 cell_t sizes[64]; /* Property is a list of bit-widths, up to 64-bits */ 223 int count; 224 225 node = ofw_bus_get_node(dev); 226 227 count = OF_getencprop(node, "ibm,supported-tce-sizes", 228 sizes, sizeof(sizes)); 229 if (count < (int) sizeof(cell_t)) 230 return OPAL_PCI_TCE_DEFAULT_SEG_SIZE; 231 232 count /= sizeof(cell_t); 233 234 return (1ULL << sizes[count - 1]); 235 } 236 237 static int 238 opalpci_attach(device_t dev) 239 { 240 struct opalpci_softc *sc; 241 cell_t id[2], m64ranges[2], m64window[6], npe; 242 phandle_t node; 243 int i, err; 244 uint64_t maxmem; 245 uint64_t entries; 246 uint64_t tce_size; 247 uint64_t tce_tbl_size; 248 int m64bar; 249 int rid; 250 251 sc = device_get_softc(dev); 252 node = ofw_bus_get_node(dev); 253 254 switch (OF_getproplen(node, "ibm,opal-phbid")) { 255 case 8: 256 OF_getencprop(node, "ibm,opal-phbid", id, 8); 257 sc->phb_id = ((uint64_t)id[0] << 32) | id[1]; 258 break; 259 case 4: 260 OF_getencprop(node, "ibm,opal-phbid", id, 4); 261 sc->phb_id = id[0]; 262 break; 263 default: 264 device_printf(dev, "PHB ID property had wrong length (%zd)\n", 265 OF_getproplen(node, "ibm,opal-phbid")); 266 return (ENXIO); 267 } 268 269 if (bootverbose) 270 device_printf(dev, "OPAL ID %#lx\n", sc->phb_id); 271 272 rid = 0; 273 sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 274 &rid, RF_ACTIVE | RF_SHAREABLE); 275 if (sc->r_reg == NULL) { 276 device_printf(dev, "Failed to allocate PHB[%jd] registers\n", 277 (uintmax_t)sc->phb_id); 278 return (ENXIO); 279 } 280 281 #if 0 282 /* 283 * Reset PCI IODA table 284 */ 285 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PCI_IODA_TABLE, 286 1); 287 if (err != 0) { 288 device_printf(dev, "IODA table reset failed: %d\n", err); 289 return (ENXIO); 290 } 291 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 292 1); 293 if (err < 0) { 294 device_printf(dev, "PHB reset failed: %d\n", err); 295 return (ENXIO); 296 } 297 if (err > 0) { 298 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) { 299 DELAY(1000*(err + 1)); /* Returns expected delay in ms */ 300 } 301 } 302 if (err < 0) { 303 device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err); 304 } 305 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE, 306 0); 307 if (err < 0) { 308 device_printf(dev, "PHB reset failed: %d\n", err); 309 return (ENXIO); 310 } 311 if (err > 0) { 312 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) { 313 DELAY(1000*(err + 1)); /* Returns expected delay in ms */ 314 } 315 } 316 #endif 317 318 /* 319 * Map all devices on the bus to partitionable endpoint one until 320 * such time as we start wanting to do things like bhyve. 321 */ 322 err = opal_call(OPAL_PCI_SET_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, 323 0, OPAL_PCI_BUS_ANY, OPAL_IGNORE_RID_DEVICE_NUMBER, 324 OPAL_IGNORE_RID_FUNC_NUMBER, OPAL_MAP_PE); 325 if (err != 0) { 326 device_printf(dev, "PE mapping failed: %d\n", err); 327 return (ENXIO); 328 } 329 330 /* 331 * Turn on MMIO, mapped to PE 1 332 */ 333 if (OF_getencprop(node, "ibm,opal-num-pes", &npe, 4) != 4) 334 npe = 1; 335 for (i = 0; i < npe; i++) { 336 err = opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id, 337 OPAL_PCI_DEFAULT_PE, OPAL_M32_WINDOW_TYPE, 0, i); 338 if (err != 0) 339 device_printf(dev, "MMIO %d map failed: %d\n", i, err); 340 } 341 342 if (OF_getencprop(node, "ibm,opal-available-m64-ranges", 343 m64ranges, sizeof(m64ranges)) == sizeof(m64ranges)) 344 m64bar = m64ranges[0]; 345 else 346 m64bar = 0; 347 348 /* XXX: multiple M64 windows? */ 349 if (OF_getencprop(node, "ibm,opal-m64-window", 350 m64window, sizeof(m64window)) == sizeof(m64window)) { 351 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id, 352 OPAL_M64_WINDOW_TYPE, m64bar, 0); 353 opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id, 354 OPAL_M64_WINDOW_TYPE, m64bar /* index */, 355 ((uint64_t)m64window[2] << 32) | m64window[3], 0, 356 ((uint64_t)m64window[4] << 32) | m64window[5]); 357 opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id, 358 OPAL_PCI_DEFAULT_PE, OPAL_M64_WINDOW_TYPE, 359 m64bar /* index */, 0); 360 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id, 361 OPAL_M64_WINDOW_TYPE, m64bar, OPAL_ENABLE_M64_NON_SPLIT); 362 } 363 364 /* 365 * Enable IOMMU for PE1 - map everything 1:1 using 366 * segments of max_tce_size size 367 */ 368 tce_size = max_tce_size(dev); 369 maxmem = roundup2(powerpc_ptob(Maxmem), tce_size); 370 entries = round_pow2(maxmem / tce_size); 371 tce_tbl_size = MAX(entries * sizeof(uint64_t), 4096); 372 if (entries > OPAL_PCI_TCE_MAX_ENTRIES) 373 panic("POWERNV supports only %jdGB of memory space\n", 374 (uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * tce_size) >> 30)); 375 if (bootverbose) 376 device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem); 377 sc->tce = contigmalloc(tce_tbl_size, 378 M_DEVBUF, M_NOWAIT | M_ZERO, 0, 379 BUS_SPACE_MAXADDR, tce_tbl_size, 0); 380 if (sc->tce == NULL) 381 panic("Failed to allocate TCE memory for PHB %jd\n", 382 (uintmax_t)sc->phb_id); 383 384 for (i = 0; i < entries; i++) 385 sc->tce[i] = htobe64((i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W); 386 387 /* Map TCE for every PE. It seems necessary for Power8 */ 388 for (i = 0; i < npe; i++) { 389 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id, 390 i, (i << 1), 391 1, pmap_kextract((uint64_t)&sc->tce[0]), 392 tce_tbl_size, tce_size); 393 if (err != 0) { 394 device_printf(dev, "DMA IOMMU mapping failed: %d\n", err); 395 return (ENXIO); 396 } 397 398 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id, 399 i, (i << 1) + 1, 400 (1UL << 59), maxmem); 401 if (err != 0) { 402 device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err); 403 return (ENXIO); 404 } 405 } 406 407 /* 408 * Invalidate all previous TCE entries. 409 */ 410 if (ofw_bus_is_compatible(dev, "power8-pciex")) 411 pci_phb3_tce_invalidate_entire(sc); 412 else 413 opal_call(OPAL_PCI_TCE_KILL, sc->phb_id, OPAL_PCI_TCE_KILL_ALL, 414 OPAL_PCI_DEFAULT_PE, 0, 0, 0); 415 416 /* 417 * Get MSI properties 418 */ 419 sc->msi_vmem = NULL; 420 if (OF_getproplen(node, "ibm,opal-msi-ranges") > 0) { 421 cell_t msi_ranges[2]; 422 OF_getencprop(node, "ibm,opal-msi-ranges", 423 msi_ranges, sizeof(msi_ranges)); 424 sc->msi_base = msi_ranges[0]; 425 426 sc->msi_vmem = vmem_create("OPAL MSI", msi_ranges[0], 427 msi_ranges[1], 1, 0, M_BESTFIT | M_WAITOK); 428 429 sc->base_msi_irq = powerpc_register_pic(dev, 430 OF_xref_from_node(node), 431 msi_ranges[0] + msi_ranges[1], 0, FALSE); 432 433 if (bootverbose) 434 device_printf(dev, "Supports %d MSIs starting at %d\n", 435 msi_ranges[1], msi_ranges[0]); 436 } 437 438 /* Create the parent DMA tag */ 439 /* 440 * Constrain it to POWER8 PHB (ioda2) for now. It seems to mess up on 441 * POWER9 systems. 442 */ 443 if (ofw_bus_is_compatible(dev, "ibm,ioda2-phb")) { 444 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 445 1, 0, /* alignment, bounds */ 446 OPAL_PCI_BUS_SPACE_LOWADDR_32BIT, /* lowaddr */ 447 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 448 NULL, NULL, /* filter, filterarg */ 449 BUS_SPACE_MAXSIZE, /* maxsize */ 450 BUS_SPACE_UNRESTRICTED, /* nsegments */ 451 BUS_SPACE_MAXSIZE, /* maxsegsize */ 452 0, /* flags */ 453 NULL, NULL, /* lockfunc, lockarg */ 454 &sc->ofw_sc.sc_dmat); 455 if (err != 0) { 456 device_printf(dev, "Failed to create DMA tag\n"); 457 return (err); 458 } 459 } 460 461 /* 462 * General OFW PCI attach 463 */ 464 err = ofw_pcib_init(dev); 465 if (err != 0) 466 return (err); 467 468 /* 469 * Unfreeze non-config-space PCI operations. Let this fail silently 470 * if e.g. there is no current freeze. 471 */ 472 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE, 473 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 474 475 /* 476 * OPAL stores 64-bit BARs in a special property rather than "ranges" 477 */ 478 if (OF_getencprop(node, "ibm,opal-m64-window", 479 m64window, sizeof(m64window)) == sizeof(m64window)) { 480 struct ofw_pci_range *rp; 481 482 sc->ofw_sc.sc_nrange++; 483 sc->ofw_sc.sc_range = realloc(sc->ofw_sc.sc_range, 484 sc->ofw_sc.sc_nrange * sizeof(sc->ofw_sc.sc_range[0]), 485 M_DEVBUF, M_WAITOK); 486 rp = &sc->ofw_sc.sc_range[sc->ofw_sc.sc_nrange-1]; 487 rp->pci_hi = OFW_PCI_PHYS_HI_SPACE_MEM64 | 488 OFW_PCI_PHYS_HI_PREFETCHABLE; 489 rp->pci = ((uint64_t)m64window[0] << 32) | m64window[1]; 490 rp->host = ((uint64_t)m64window[2] << 32) | m64window[3]; 491 rp->size = ((uint64_t)m64window[4] << 32) | m64window[5]; 492 rman_manage_region(&sc->ofw_sc.sc_mem_rman, rp->pci, 493 rp->pci + rp->size - 1); 494 } 495 496 return (ofw_pcib_attach(dev)); 497 } 498 499 static uint32_t 500 opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 501 int width) 502 { 503 struct opalpci_softc *sc; 504 uint64_t config_addr; 505 uint8_t byte, eeh_state; 506 uint16_t half; 507 uint32_t word; 508 int error; 509 uint16_t err_type; 510 511 sc = device_get_softc(dev); 512 513 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7); 514 515 switch (width) { 516 case 1: 517 error = opal_call(OPAL_PCI_CONFIG_READ_BYTE, sc->phb_id, 518 config_addr, reg, vtophys(&byte)); 519 word = byte; 520 break; 521 case 2: 522 error = opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, sc->phb_id, 523 config_addr, reg, vtophys(&half)); 524 word = be16toh(half); 525 break; 526 case 4: 527 error = opal_call(OPAL_PCI_CONFIG_READ_WORD, sc->phb_id, 528 config_addr, reg, vtophys(&word)); 529 word = be32toh(word); 530 break; 531 default: 532 error = OPAL_SUCCESS; 533 word = 0xffffffff; 534 width = 4; 535 } 536 537 /* 538 * Poking config state for non-existant devices can make 539 * the host bridge hang up. Clear any errors. 540 */ 541 542 if (error != OPAL_SUCCESS || 543 (word == ((1UL << (8 * width)) - 1))) { 544 if (error != OPAL_HARDWARE) { 545 opal_call(OPAL_PCI_EEH_FREEZE_STATUS, sc->phb_id, 546 OPAL_PCI_DEFAULT_PE, vtophys(&eeh_state), 547 vtophys(&err_type), NULL); 548 err_type = be16toh(err_type); /* XXX unused */ 549 if (eeh_state != OPAL_EEH_STOPPED_NOT_FROZEN) 550 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, 551 sc->phb_id, OPAL_PCI_DEFAULT_PE, 552 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 553 } 554 if (error != OPAL_SUCCESS) 555 word = 0xffffffff; 556 } 557 558 return (word); 559 } 560 561 static void 562 opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 563 u_int reg, uint32_t val, int width) 564 { 565 struct opalpci_softc *sc; 566 uint64_t config_addr; 567 int error = OPAL_SUCCESS; 568 569 sc = device_get_softc(dev); 570 571 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7); 572 573 switch (width) { 574 case 1: 575 error = opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, sc->phb_id, 576 config_addr, reg, val); 577 break; 578 case 2: 579 error = opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, sc->phb_id, 580 config_addr, reg, val); 581 break; 582 case 4: 583 error = opal_call(OPAL_PCI_CONFIG_WRITE_WORD, sc->phb_id, 584 config_addr, reg, val); 585 break; 586 } 587 588 if (error != OPAL_SUCCESS) { 589 /* 590 * Poking config state for non-existant devices can make 591 * the host bridge hang up. Clear any errors. 592 */ 593 if (error != OPAL_HARDWARE) { 594 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, 595 sc->phb_id, OPAL_PCI_DEFAULT_PE, 596 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 597 } 598 } 599 } 600 601 static int 602 opalpci_route_interrupt(device_t bus, device_t dev, int pin) 603 { 604 605 return (pin); 606 } 607 608 static int 609 opalpci_alloc_msi(device_t dev, device_t child, int count, int maxcount, 610 int *irqs) 611 { 612 struct opalpci_softc *sc; 613 vmem_addr_t start; 614 phandle_t xref; 615 int err, i; 616 617 sc = device_get_softc(dev); 618 if (sc->msi_vmem == NULL) 619 return (ENODEV); 620 621 err = vmem_xalloc(sc->msi_vmem, count, powerof2(count), 0, 0, 622 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start); 623 624 if (err) 625 return (err); 626 627 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 628 for (i = 0; i < count; i++) 629 irqs[i] = MAP_IRQ(xref, start + i); 630 631 return (0); 632 } 633 634 static int 635 opalpci_release_msi(device_t dev, device_t child, int count, int *irqs) 636 { 637 struct opalpci_softc *sc; 638 639 sc = device_get_softc(dev); 640 if (sc->msi_vmem == NULL) 641 return (ENODEV); 642 643 vmem_xfree(sc->msi_vmem, irqs[0] - sc->base_msi_irq, count); 644 return (0); 645 } 646 647 static int 648 opalpci_alloc_msix(device_t dev, device_t child, int *irq) 649 { 650 return (opalpci_alloc_msi(dev, child, 1, 1, irq)); 651 } 652 653 static int 654 opalpci_release_msix(device_t dev, device_t child, int irq) 655 { 656 return (opalpci_release_msi(dev, child, 1, &irq)); 657 } 658 659 static int 660 opalpci_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 661 uint32_t *data) 662 { 663 struct opalpci_softc *sc; 664 struct pci_devinfo *dinfo; 665 int err, xive; 666 667 sc = device_get_softc(dev); 668 if (sc->msi_vmem == NULL) 669 return (ENODEV); 670 671 xive = irq - sc->base_msi_irq - sc->msi_base; 672 opal_call(OPAL_PCI_SET_XIVE_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, xive); 673 674 dinfo = device_get_ivars(child); 675 if (dinfo->cfg.msi.msi_alloc > 0 && 676 (dinfo->cfg.msi.msi_ctrl & PCIM_MSICTRL_64BIT) == 0) { 677 uint32_t msi32; 678 err = opal_call(OPAL_GET_MSI_32, sc->phb_id, 679 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(&msi32), 680 vtophys(data)); 681 *addr = be32toh(msi32); 682 } else { 683 err = opal_call(OPAL_GET_MSI_64, sc->phb_id, 684 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(addr), vtophys(data)); 685 *addr = be64toh(*addr); 686 } 687 *data = be32toh(*data); 688 689 if (bootverbose && err != 0) 690 device_printf(child, "OPAL MSI mapping error: %d\n", err); 691 692 return ((err == 0) ? 0 : ENXIO); 693 } 694 695 static void 696 opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **priv) 697 { 698 struct opalpci_softc *sc = device_get_softc(dev); 699 700 PIC_ENABLE(root_pic, irq, vector, priv); 701 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq, priv); 702 } 703 704 static void opalpic_pic_eoi(device_t dev, u_int irq, void *priv) 705 { 706 struct opalpci_softc *sc; 707 708 sc = device_get_softc(dev); 709 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq); 710 711 PIC_EOI(root_pic, irq, priv); 712 } 713 714 static bus_dma_tag_t 715 opalpci_get_dma_tag(device_t dev, device_t child) 716 { 717 struct opalpci_softc *sc; 718 719 sc = device_get_softc(dev); 720 return (sc->ofw_sc.sc_dmat); 721 } 722