1 /*- 2 * Copyright (c) 2015 Nathan Whitehorn 3 * Copyright (c) 2017-2018 Semihalf 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/pcpu.h> 36 #include <sys/proc.h> 37 #include <sys/smp.h> 38 #include <vm/vm.h> 39 #include <vm/pmap.h> 40 41 #include <machine/bus.h> 42 #include <machine/cpu.h> 43 #include <machine/hid.h> 44 #include <machine/platformvar.h> 45 #include <machine/pmap.h> 46 #include <machine/rtas.h> 47 #include <machine/smp.h> 48 #include <machine/spr.h> 49 #include <machine/trap.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 #include <machine/ofw_machdep.h> 55 #include <powerpc/aim/mmu_oea64.h> 56 57 #include "platform_if.h" 58 #include "opal.h" 59 60 #ifdef SMP 61 extern void *ap_pcpu; 62 #endif 63 64 void (*powernv_smp_ap_extra_init)(void); 65 66 static int powernv_probe(platform_t); 67 static int powernv_attach(platform_t); 68 void powernv_mem_regions(platform_t, struct mem_region *phys, int *physsz, 69 struct mem_region *avail, int *availsz); 70 static void powernv_numa_mem_regions(platform_t plat, struct numa_mem_region *phys, int *physsz); 71 static u_long powernv_timebase_freq(platform_t, struct cpuref *cpuref); 72 static int powernv_smp_first_cpu(platform_t, struct cpuref *cpuref); 73 static int powernv_smp_next_cpu(platform_t, struct cpuref *cpuref); 74 static int powernv_smp_get_bsp(platform_t, struct cpuref *cpuref); 75 static void powernv_smp_ap_init(platform_t); 76 #ifdef SMP 77 static int powernv_smp_start_cpu(platform_t, struct pcpu *cpu); 78 static void powernv_smp_probe_threads(platform_t); 79 static struct cpu_group *powernv_smp_topo(platform_t plat); 80 #endif 81 static void powernv_reset(platform_t); 82 static void powernv_cpu_idle(sbintime_t sbt); 83 static int powernv_cpuref_init(void); 84 static int powernv_node_numa_domain(platform_t platform, phandle_t node); 85 86 static platform_method_t powernv_methods[] = { 87 PLATFORMMETHOD(platform_probe, powernv_probe), 88 PLATFORMMETHOD(platform_attach, powernv_attach), 89 PLATFORMMETHOD(platform_mem_regions, powernv_mem_regions), 90 PLATFORMMETHOD(platform_numa_mem_regions, powernv_numa_mem_regions), 91 PLATFORMMETHOD(platform_timebase_freq, powernv_timebase_freq), 92 93 PLATFORMMETHOD(platform_smp_ap_init, powernv_smp_ap_init), 94 PLATFORMMETHOD(platform_smp_first_cpu, powernv_smp_first_cpu), 95 PLATFORMMETHOD(platform_smp_next_cpu, powernv_smp_next_cpu), 96 PLATFORMMETHOD(platform_smp_get_bsp, powernv_smp_get_bsp), 97 #ifdef SMP 98 PLATFORMMETHOD(platform_smp_start_cpu, powernv_smp_start_cpu), 99 PLATFORMMETHOD(platform_smp_probe_threads, powernv_smp_probe_threads), 100 PLATFORMMETHOD(platform_smp_topo, powernv_smp_topo), 101 #endif 102 PLATFORMMETHOD(platform_node_numa_domain, powernv_node_numa_domain), 103 104 PLATFORMMETHOD(platform_reset, powernv_reset), 105 106 { 0, 0 } 107 }; 108 109 static platform_def_t powernv_platform = { 110 "powernv", 111 powernv_methods, 112 0 113 }; 114 115 static struct cpuref platform_cpuref[MAXCPU]; 116 static int platform_cpuref_cnt; 117 static int platform_cpuref_valid; 118 static int platform_associativity; 119 120 PLATFORM_DEF(powernv_platform); 121 122 static uint64_t powernv_boot_pir; 123 124 static int 125 powernv_probe(platform_t plat) 126 { 127 if (opal_check() == 0) 128 return (BUS_PROBE_SPECIFIC); 129 130 return (ENXIO); 131 } 132 133 static int 134 powernv_attach(platform_t plat) 135 { 136 uint32_t nptlp, shift = 0, slb_encoding = 0; 137 int32_t lp_size, lp_encoding; 138 char buf[255]; 139 pcell_t refpoints[3]; 140 pcell_t prop; 141 phandle_t cpu; 142 phandle_t opal; 143 int res, len, idx; 144 register_t msr; 145 146 /* Ping OPAL again just to make sure */ 147 opal_check(); 148 149 #if BYTE_ORDER == LITTLE_ENDIAN 150 opal_call(OPAL_REINIT_CPUS, 2 /* Little endian */); 151 #else 152 opal_call(OPAL_REINIT_CPUS, 1 /* Big endian */); 153 #endif 154 opal = OF_finddevice("/ibm,opal"); 155 156 platform_associativity = 4; /* Skiboot default. */ 157 if (OF_getencprop(opal, "ibm,associativity-reference-points", refpoints, 158 sizeof(refpoints)) > 0) { 159 platform_associativity = refpoints[0]; 160 } 161 162 if (cpu_idle_hook == NULL) 163 cpu_idle_hook = powernv_cpu_idle; 164 165 powernv_boot_pir = mfspr(SPR_PIR); 166 167 /* LPID must not be altered when PSL_DR or PSL_IR is set */ 168 msr = mfmsr(); 169 mtmsr(msr & ~(PSL_DR | PSL_IR)); 170 171 /* Direct interrupts to SRR instead of HSRR and reset LPCR otherwise */ 172 mtspr(SPR_LPID, 0); 173 isync(); 174 175 if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) 176 lpcr |= LPCR_HVICE; 177 178 mtspr(SPR_LPCR, lpcr); 179 isync(); 180 181 mtmsr(msr); 182 183 powernv_cpuref_init(); 184 185 /* Set SLB count from device tree */ 186 cpu = OF_peer(0); 187 cpu = OF_child(cpu); 188 while (cpu != 0) { 189 res = OF_getprop(cpu, "name", buf, sizeof(buf)); 190 if (res > 0 && strcmp(buf, "cpus") == 0) 191 break; 192 cpu = OF_peer(cpu); 193 } 194 if (cpu == 0) 195 goto out; 196 197 cpu = OF_child(cpu); 198 while (cpu != 0) { 199 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 200 if (res > 0 && strcmp(buf, "cpu") == 0) 201 break; 202 cpu = OF_peer(cpu); 203 } 204 if (cpu == 0) 205 goto out; 206 207 res = OF_getencprop(cpu, "ibm,slb-size", &prop, sizeof(prop)); 208 if (res > 0) 209 n_slbs = prop; 210 211 /* 212 * Scan the large page size property for PAPR compatible machines. 213 * See PAPR D.5 Changes to Section 5.1.4, 'CPU Node Properties' 214 * for the encoding of the property. 215 */ 216 217 len = OF_getproplen(cpu, "ibm,segment-page-sizes"); 218 if (len > 0) { 219 /* 220 * We have to use a variable length array on the stack 221 * since we have very limited stack space. 222 */ 223 pcell_t arr[len/sizeof(cell_t)]; 224 res = OF_getencprop(cpu, "ibm,segment-page-sizes", arr, 225 sizeof(arr)); 226 len /= 4; 227 idx = 0; 228 while (len > 0) { 229 shift = arr[idx]; 230 slb_encoding = arr[idx + 1]; 231 nptlp = arr[idx + 2]; 232 idx += 3; 233 len -= 3; 234 while (len > 0 && nptlp) { 235 lp_size = arr[idx]; 236 lp_encoding = arr[idx+1]; 237 if (slb_encoding == SLBV_L && lp_encoding == 0) 238 break; 239 240 idx += 2; 241 len -= 2; 242 nptlp--; 243 } 244 if (nptlp && slb_encoding == SLBV_L && lp_encoding == 0) 245 break; 246 } 247 248 if (len == 0) 249 panic("Standard large pages (SLB[L] = 1, PTE[LP] = 0) " 250 "not supported by this system."); 251 252 moea64_large_page_shift = shift; 253 moea64_large_page_size = 1ULL << lp_size; 254 } 255 256 out: 257 return (0); 258 } 259 260 261 void 262 powernv_mem_regions(platform_t plat, struct mem_region *phys, int *physsz, 263 struct mem_region *avail, int *availsz) 264 { 265 266 ofw_mem_regions(phys, physsz, avail, availsz); 267 } 268 269 static void 270 powernv_numa_mem_regions(platform_t plat, struct numa_mem_region *phys, int *physsz) 271 { 272 273 ofw_numa_mem_regions(phys, physsz); 274 } 275 276 static u_long 277 powernv_timebase_freq(platform_t plat, struct cpuref *cpuref) 278 { 279 char buf[8]; 280 phandle_t cpu, dev, root; 281 int res; 282 int32_t ticks = -1; 283 284 root = OF_peer(0); 285 dev = OF_child(root); 286 while (dev != 0) { 287 res = OF_getprop(dev, "name", buf, sizeof(buf)); 288 if (res > 0 && strcmp(buf, "cpus") == 0) 289 break; 290 dev = OF_peer(dev); 291 } 292 293 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { 294 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 295 if (res > 0 && strcmp(buf, "cpu") == 0) 296 break; 297 } 298 if (cpu == 0) 299 return (512000000); 300 301 OF_getencprop(cpu, "timebase-frequency", &ticks, sizeof(ticks)); 302 303 if (ticks <= 0) 304 panic("Unable to determine timebase frequency!"); 305 306 return (ticks); 307 308 } 309 310 static int 311 powernv_cpuref_init(void) 312 { 313 phandle_t cpu, dev; 314 char buf[32]; 315 int a, res, tmp_cpuref_cnt; 316 static struct cpuref tmp_cpuref[MAXCPU]; 317 cell_t interrupt_servers[32]; 318 uint64_t bsp; 319 320 if (platform_cpuref_valid) 321 return (0); 322 323 dev = OF_peer(0); 324 dev = OF_child(dev); 325 while (dev != 0) { 326 res = OF_getprop(dev, "name", buf, sizeof(buf)); 327 if (res > 0 && strcmp(buf, "cpus") == 0) 328 break; 329 dev = OF_peer(dev); 330 } 331 332 bsp = 0; 333 tmp_cpuref_cnt = 0; 334 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { 335 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 336 if (res > 0 && strcmp(buf, "cpu") == 0) { 337 if (!ofw_bus_node_status_okay(cpu)) 338 continue; 339 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s"); 340 if (res > 0) { 341 OF_getencprop(cpu, "ibm,ppc-interrupt-server#s", 342 interrupt_servers, res); 343 344 for (a = 0; a < res/sizeof(cell_t); a++) { 345 tmp_cpuref[tmp_cpuref_cnt].cr_hwref = interrupt_servers[a]; 346 tmp_cpuref[tmp_cpuref_cnt].cr_cpuid = tmp_cpuref_cnt; 347 tmp_cpuref[tmp_cpuref_cnt].cr_domain = 348 powernv_node_numa_domain(NULL, cpu); 349 if (interrupt_servers[a] == (uint32_t)powernv_boot_pir) 350 bsp = tmp_cpuref_cnt; 351 352 tmp_cpuref_cnt++; 353 } 354 } 355 } 356 } 357 358 /* Map IDs, so BSP has CPUID 0 regardless of hwref */ 359 for (a = bsp; a < tmp_cpuref_cnt; a++) { 360 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref; 361 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt; 362 platform_cpuref[platform_cpuref_cnt].cr_domain = tmp_cpuref[a].cr_domain; 363 platform_cpuref_cnt++; 364 } 365 for (a = 0; a < bsp; a++) { 366 platform_cpuref[platform_cpuref_cnt].cr_hwref = tmp_cpuref[a].cr_hwref; 367 platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt; 368 platform_cpuref[platform_cpuref_cnt].cr_domain = tmp_cpuref[a].cr_domain; 369 platform_cpuref_cnt++; 370 } 371 372 platform_cpuref_valid = 1; 373 374 return (0); 375 } 376 377 static int 378 powernv_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 379 { 380 if (platform_cpuref_valid == 0) 381 return (EINVAL); 382 383 cpuref->cr_cpuid = 0; 384 cpuref->cr_hwref = platform_cpuref[0].cr_hwref; 385 cpuref->cr_domain = platform_cpuref[0].cr_domain; 386 387 return (0); 388 } 389 390 static int 391 powernv_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 392 { 393 int id; 394 395 if (platform_cpuref_valid == 0) 396 return (EINVAL); 397 398 id = cpuref->cr_cpuid + 1; 399 if (id >= platform_cpuref_cnt) 400 return (ENOENT); 401 402 cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid; 403 cpuref->cr_hwref = platform_cpuref[id].cr_hwref; 404 cpuref->cr_domain = platform_cpuref[id].cr_domain; 405 406 return (0); 407 } 408 409 static int 410 powernv_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 411 { 412 413 cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid; 414 cpuref->cr_hwref = platform_cpuref[0].cr_hwref; 415 cpuref->cr_domain = platform_cpuref[0].cr_domain; 416 return (0); 417 } 418 419 #ifdef SMP 420 static int 421 powernv_smp_start_cpu(platform_t plat, struct pcpu *pc) 422 { 423 int result; 424 425 ap_pcpu = pc; 426 powerpc_sync(); 427 428 result = opal_call(OPAL_START_CPU, pc->pc_hwref, EXC_RST); 429 if (result != OPAL_SUCCESS) { 430 printf("OPAL error (%d): unable to start AP %d\n", 431 result, (int)pc->pc_hwref); 432 return (ENXIO); 433 } 434 435 return (0); 436 } 437 438 static void 439 powernv_smp_probe_threads(platform_t plat) 440 { 441 char buf[8]; 442 phandle_t cpu, dev, root; 443 int res, nthreads; 444 445 root = OF_peer(0); 446 447 dev = OF_child(root); 448 while (dev != 0) { 449 res = OF_getprop(dev, "name", buf, sizeof(buf)); 450 if (res > 0 && strcmp(buf, "cpus") == 0) 451 break; 452 dev = OF_peer(dev); 453 } 454 455 nthreads = 1; 456 for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { 457 res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); 458 if (res <= 0 || strcmp(buf, "cpu") != 0) 459 continue; 460 461 res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s"); 462 463 if (res >= 0) 464 nthreads = res / sizeof(cell_t); 465 else 466 nthreads = 1; 467 break; 468 } 469 470 smp_threads_per_core = nthreads; 471 if (mp_ncpus % nthreads == 0) 472 mp_ncores = mp_ncpus / nthreads; 473 } 474 475 static struct cpu_group * 476 powernv_smp_topo(platform_t plat) 477 { 478 if (mp_ncpus % smp_threads_per_core != 0) { 479 printf("WARNING: Irregular SMP topology. Performance may be " 480 "suboptimal (%d threads, %d on first core)\n", 481 mp_ncpus, smp_threads_per_core); 482 return (smp_topo_none()); 483 } 484 485 /* Don't do anything fancier for non-threaded SMP */ 486 if (smp_threads_per_core == 1) 487 return (smp_topo_none()); 488 489 return (smp_topo_1level(CG_SHARE_L1, smp_threads_per_core, 490 CG_FLAG_SMT)); 491 } 492 493 #endif 494 495 static void 496 powernv_reset(platform_t platform) 497 { 498 499 opal_call(OPAL_CEC_REBOOT); 500 } 501 502 static void 503 powernv_smp_ap_init(platform_t platform) 504 { 505 506 if (powernv_smp_ap_extra_init != NULL) 507 powernv_smp_ap_extra_init(); 508 } 509 510 static void 511 powernv_cpu_idle(sbintime_t sbt) 512 { 513 } 514 515 static int 516 powernv_node_numa_domain(platform_t platform, phandle_t node) 517 { 518 /* XXX: Is locking necessary in here? */ 519 static int numa_domains[MAXMEMDOM]; 520 static int numa_max_domain; 521 cell_t associativity[5]; 522 int i, res; 523 524 #ifndef NUMA 525 return (0); 526 #endif 527 if (vm_ndomains == 1) 528 return (0); 529 530 res = OF_getencprop(node, "ibm,associativity", 531 associativity, sizeof(associativity)); 532 533 /* 534 * If this node doesn't have associativity, or if there are not 535 * enough elements in it, check its parent. 536 */ 537 if (res < (int)(sizeof(cell_t) * (platform_associativity + 1))) { 538 node = OF_parent(node); 539 /* If already at the root, use default domain. */ 540 if (node == 0) 541 return (0); 542 return (powernv_node_numa_domain(platform, node)); 543 } 544 545 for (i = 0; i < numa_max_domain; i++) { 546 if (numa_domains[i] == associativity[platform_associativity]) 547 return (i); 548 } 549 if (i < MAXMEMDOM) 550 numa_domains[numa_max_domain++] = 551 associativity[platform_associativity]; 552 else 553 i = 0; 554 555 return (i); 556 } 557 558 /* Set up the Nest MMU on POWER9 relatively early, but after pmap is setup. */ 559 static void 560 powernv_setup_nmmu(void *unused) 561 { 562 if (opal_check() != 0) 563 return; 564 opal_call(OPAL_NMMU_SET_PTCR, -1, mfspr(SPR_PTCR)); 565 } 566 567 SYSINIT(powernv_setup_nmmu, SI_SUB_CPU, SI_ORDER_ANY, powernv_setup_nmmu, NULL); 568