1 /*- 2 * Copyright (c) 2001 Matt Thomas. 3 * Copyright (c) 2001 Tsubai Masanari. 4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by 18 * Internet Research Institute, Inc. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (C) 2003 Benno Rice. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 * 57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $ 58 * $FreeBSD$ 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/bus.h> 64 #include <sys/conf.h> 65 #include <sys/cpu.h> 66 #include <sys/kernel.h> 67 #include <sys/proc.h> 68 #include <sys/sysctl.h> 69 70 #include <machine/bus.h> 71 #include <machine/cpu.h> 72 #include <machine/hid.h> 73 #include <machine/md_var.h> 74 #include <machine/smp.h> 75 #include <machine/spr.h> 76 77 #include <dev/ofw/openfirm.h> 78 79 static void cpu_6xx_setup(int cpuid, uint16_t vers); 80 static void cpu_970_setup(int cpuid, uint16_t vers); 81 static void cpu_booke_setup(int cpuid, uint16_t vers); 82 83 int powerpc_pow_enabled; 84 void (*cpu_idle_hook)(sbintime_t) = NULL; 85 static void cpu_idle_60x(sbintime_t); 86 static void cpu_idle_booke(sbintime_t); 87 88 struct cputab { 89 const char *name; 90 uint16_t version; 91 uint16_t revfmt; 92 int features; /* Do not include PPC_FEATURE_32 or 93 * PPC_FEATURE_HAS_MMU */ 94 int features2; 95 void (*cpu_setup)(int cpuid, uint16_t vers); 96 }; 97 #define REVFMT_MAJMIN 1 /* %u.%u */ 98 #define REVFMT_HEX 2 /* 0x%04x */ 99 #define REVFMT_DEC 3 /* %u */ 100 static const struct cputab models[] = { 101 { "Motorola PowerPC 601", MPC601, REVFMT_DEC, 102 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup }, 103 { "Motorola PowerPC 602", MPC602, REVFMT_DEC, 104 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 105 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN, 106 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 107 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN, 108 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 109 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN, 110 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 111 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN, 112 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 113 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN, 114 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 115 { "Motorola PowerPC 620", MPC620, REVFMT_HEX, 116 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL }, 117 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN, 118 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 119 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN, 120 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 121 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN, 122 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 123 0, cpu_970_setup }, 124 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN, 125 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 126 0, cpu_970_setup }, 127 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN, 128 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 129 0, cpu_970_setup }, 130 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN, 131 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 132 0, cpu_970_setup }, 133 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN, 134 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL }, 135 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN, 136 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL }, 137 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN, 138 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL }, 139 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN, 140 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL }, 141 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN, 142 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 143 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05, 0, NULL }, 144 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN, 145 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 146 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 | 147 PPC_FEATURE_HAS_VSX, 0, NULL }, 148 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN, 149 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 150 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 | 151 PPC_FEATURE_HAS_VSX, 0, NULL }, 152 { "IBM POWER8E", IBMPOWER8E, REVFMT_MAJMIN, 153 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 154 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 | 155 PPC_FEATURE_HAS_VSX, 156 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | 157 PPC_FEATURE2_HAS_VCRYPTO, NULL }, 158 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN, 159 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 160 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 | 161 PPC_FEATURE_HAS_VSX, 162 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM | 163 PPC_FEATURE2_HAS_VCRYPTO, NULL }, 164 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN, 165 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 166 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN, 167 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 168 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN, 169 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 170 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN, 171 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 172 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN, 173 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 174 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN, 175 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 176 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN, 177 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 178 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN, 179 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 180 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN, 181 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 182 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN, 183 PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE, 184 0, cpu_booke_setup }, 185 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN, 186 PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | 187 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 0, 188 cpu_booke_setup }, 189 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN, 190 PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_FPU, 0, cpu_booke_setup }, 191 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN, 192 PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, 193 cpu_booke_setup }, 194 { "Freescale e6500 core", FSL_E6500, REVFMT_MAJMIN, 195 PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | 196 PPC_FEATURE_HAS_FPU, 0, cpu_booke_setup }, 197 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN, 198 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 199 PPC_FEATURE_SMT, 0, NULL}, 200 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, 0, NULL }, 201 }; 202 203 static void cpu_6xx_print_cacheinfo(u_int, uint16_t); 204 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS); 205 206 static char model[64]; 207 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, ""); 208 209 int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU; 210 int cpu_features2 = 0; 211 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD, 212 &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features"); 213 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD, 214 &cpu_features2, sizeof(cpu_features2), "IX", "PowerPC CPU features 2"); 215 216 /* Provide some user-friendly aliases for bits in cpu_features */ 217 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD, 218 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I", 219 "Floating point instructions executed in hardware"); 220 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD, 221 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec"); 222 223 void 224 cpu_setup(u_int cpuid) 225 { 226 u_int pvr, maj, min; 227 uint16_t vers, rev, revfmt; 228 uint64_t cps; 229 const struct cputab *cp; 230 const char *name; 231 232 pvr = mfpvr(); 233 vers = pvr >> 16; 234 rev = pvr; 235 switch (vers) { 236 case MPC7410: 237 min = (pvr >> 0) & 0xff; 238 maj = min <= 4 ? 1 : 2; 239 break; 240 case FSL_E500v1: 241 case FSL_E500v2: 242 case FSL_E500mc: 243 case FSL_E5500: 244 maj = (pvr >> 4) & 0xf; 245 min = (pvr >> 0) & 0xf; 246 break; 247 default: 248 maj = (pvr >> 8) & 0xf; 249 min = (pvr >> 0) & 0xf; 250 } 251 252 for (cp = models; cp->version != 0; cp++) { 253 if (cp->version == vers) 254 break; 255 } 256 257 revfmt = cp->revfmt; 258 name = cp->name; 259 if (rev == MPC750 && pvr == 15) { 260 name = "Motorola MPC755"; 261 revfmt = REVFMT_HEX; 262 } 263 strncpy(model, name, sizeof(model) - 1); 264 265 printf("cpu%d: %s revision ", cpuid, name); 266 267 switch (revfmt) { 268 case REVFMT_MAJMIN: 269 printf("%u.%u", maj, min); 270 break; 271 case REVFMT_HEX: 272 printf("0x%04x", rev); 273 break; 274 case REVFMT_DEC: 275 printf("%u", rev); 276 break; 277 } 278 279 if (cpu_est_clockrate(0, &cps) == 0) 280 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100); 281 printf("\n"); 282 283 cpu_features |= cp->features; 284 cpu_features2 |= cp->features2; 285 printf("cpu%d: Features %b\n", cpuid, cpu_features, 286 PPC_FEATURE_BITMASK); 287 if (cpu_features2 != 0) 288 printf("cpu%d: Features2 %b\n", cpuid, cpu_features2, 289 PPC_FEATURE2_BITMASK); 290 291 /* 292 * Configure CPU 293 */ 294 if (cp->cpu_setup != NULL) 295 cp->cpu_setup(cpuid, vers); 296 } 297 298 /* Get current clock frequency for the given cpu id. */ 299 int 300 cpu_est_clockrate(int cpu_id, uint64_t *cps) 301 { 302 uint16_t vers; 303 register_t msr; 304 phandle_t cpu, dev, root; 305 int res = 0; 306 char buf[8]; 307 308 vers = mfpvr() >> 16; 309 msr = mfmsr(); 310 mtmsr(msr & ~PSL_EE); 311 312 switch (vers) { 313 case MPC7450: 314 case MPC7455: 315 case MPC7457: 316 case MPC750: 317 case IBM750FX: 318 case MPC7400: 319 case MPC7410: 320 case MPC7447A: 321 case MPC7448: 322 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 323 mtspr(SPR_PMC1, 0); 324 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 325 DELAY(1000); 326 *cps = (mfspr(SPR_PMC1) * 1000) + 4999; 327 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 328 329 mtmsr(msr); 330 return (0); 331 case IBM970: 332 case IBM970FX: 333 case IBM970MP: 334 isync(); 335 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 336 isync(); 337 mtspr(SPR_970MMCR1, 0); 338 mtspr(SPR_970MMCRA, 0); 339 mtspr(SPR_970PMC1, 0); 340 mtspr(SPR_970MMCR0, 341 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES)); 342 isync(); 343 DELAY(1000); 344 powerpc_sync(); 345 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 346 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; 347 348 mtmsr(msr); 349 return (0); 350 351 default: 352 root = OF_peer(0); 353 if (root == 0) 354 return (ENXIO); 355 356 dev = OF_child(root); 357 while (dev != 0) { 358 res = OF_getprop(dev, "name", buf, sizeof(buf)); 359 if (res > 0 && strcmp(buf, "cpus") == 0) 360 break; 361 dev = OF_peer(dev); 362 } 363 cpu = OF_child(dev); 364 while (cpu != 0) { 365 res = OF_getprop(cpu, "device_type", buf, 366 sizeof(buf)); 367 if (res > 0 && strcmp(buf, "cpu") == 0) 368 break; 369 cpu = OF_peer(cpu); 370 } 371 if (cpu == 0) 372 return (ENOENT); 373 if (OF_getprop(cpu, "ibm,extended-clock-frequency", 374 cps, sizeof(*cps)) >= 0) { 375 return (0); 376 } else if (OF_getprop(cpu, "clock-frequency", cps, 377 sizeof(cell_t)) >= 0) { 378 *cps >>= 32; 379 return (0); 380 } else { 381 return (ENOENT); 382 } 383 } 384 } 385 386 void 387 cpu_6xx_setup(int cpuid, uint16_t vers) 388 { 389 register_t hid0, pvr; 390 const char *bitmask; 391 392 hid0 = mfspr(SPR_HID0); 393 pvr = mfpvr(); 394 395 /* 396 * Configure power-saving mode. 397 */ 398 switch (vers) { 399 case MPC603: 400 case MPC603e: 401 case MPC603ev: 402 case MPC604ev: 403 case MPC750: 404 case IBM750FX: 405 case MPC7400: 406 case MPC7410: 407 case MPC8240: 408 case MPC8245: 409 /* Select DOZE mode. */ 410 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 411 hid0 |= HID0_DOZE | HID0_DPM; 412 powerpc_pow_enabled = 1; 413 break; 414 415 case MPC7448: 416 case MPC7447A: 417 case MPC7457: 418 case MPC7455: 419 case MPC7450: 420 /* Enable the 7450 branch caches */ 421 hid0 |= HID0_SGE | HID0_BTIC; 422 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 423 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ 424 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 425 || (pvr >> 16) == MPC7457) 426 hid0 &= ~HID0_BTIC; 427 /* Select NAP mode. */ 428 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 429 hid0 |= HID0_NAP | HID0_DPM; 430 powerpc_pow_enabled = 1; 431 break; 432 433 default: 434 /* No power-saving mode is available. */ ; 435 } 436 437 switch (vers) { 438 case IBM750FX: 439 case MPC750: 440 hid0 &= ~HID0_DBP; /* XXX correct? */ 441 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 442 break; 443 444 case MPC7400: 445 case MPC7410: 446 hid0 &= ~HID0_SPD; 447 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 448 hid0 |= HID0_EIEC; 449 break; 450 451 } 452 453 mtspr(SPR_HID0, hid0); 454 455 if (bootverbose) 456 cpu_6xx_print_cacheinfo(cpuid, vers); 457 458 switch (vers) { 459 case MPC7447A: 460 case MPC7448: 461 case MPC7450: 462 case MPC7455: 463 case MPC7457: 464 bitmask = HID0_7450_BITMASK; 465 break; 466 default: 467 bitmask = HID0_BITMASK; 468 break; 469 } 470 471 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask); 472 473 if (cpu_idle_hook == NULL) 474 cpu_idle_hook = cpu_idle_60x; 475 } 476 477 478 static void 479 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers) 480 { 481 register_t hid; 482 483 hid = mfspr(SPR_HID0); 484 printf("cpu%u: ", cpuid); 485 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis"); 486 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis"); 487 488 printf("cpu%u: ", cpuid); 489 if (mfspr(SPR_L2CR) & L2CR_L2E) { 490 switch (vers) { 491 case MPC7450: 492 case MPC7455: 493 case MPC7457: 494 printf("256KB L2 cache, "); 495 if (mfspr(SPR_L3CR) & L3CR_L3E) 496 printf("%cMB L3 backside cache", 497 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1'); 498 else 499 printf("L3 cache disabled"); 500 printf("\n"); 501 break; 502 case IBM750FX: 503 printf("512KB L2 cache\n"); 504 break; 505 default: 506 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { 507 case L2SIZ_256K: 508 printf("256KB "); 509 break; 510 case L2SIZ_512K: 511 printf("512KB "); 512 break; 513 case L2SIZ_1M: 514 printf("1MB "); 515 break; 516 } 517 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) 518 ? "through" : "back"); 519 if (mfspr(SPR_L2CR) & L2CR_L2PE) 520 printf(", with parity"); 521 printf(" backside cache\n"); 522 break; 523 } 524 } else 525 printf("L2 cache disabled\n"); 526 } 527 528 static void 529 cpu_booke_setup(int cpuid, uint16_t vers) 530 { 531 #ifdef BOOKE_E500 532 register_t hid0; 533 534 hid0 = mfspr(SPR_HID0); 535 536 /* Programe power-management mode. */ 537 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 538 hid0 |= HID0_DOZE; 539 540 mtspr(SPR_HID0, hid0); 541 542 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK); 543 #endif 544 545 if (cpu_idle_hook == NULL) 546 cpu_idle_hook = cpu_idle_booke; 547 } 548 549 static void 550 cpu_970_setup(int cpuid, uint16_t vers) 551 { 552 #ifdef AIM 553 uint32_t hid0_hi, hid0_lo; 554 555 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;" 556 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0)); 557 558 /* Configure power-saving mode */ 559 switch (vers) { 560 case IBM970MP: 561 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM); 562 hid0_hi &= ~HID0_DOZE; 563 break; 564 default: 565 hid0_hi |= (HID0_NAP | HID0_DPM); 566 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP); 567 break; 568 } 569 powerpc_pow_enabled = 1; 570 571 __asm __volatile (" \ 572 sync; isync; \ 573 sldi %0,%0,32; or %0,%0,%1; \ 574 mtspr %2, %0; \ 575 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \ 576 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \ 577 sync; isync" 578 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0)); 579 580 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;" 581 : "=r" (hid0_hi) : "K" (SPR_HID0)); 582 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK); 583 #endif 584 585 cpu_idle_hook = cpu_idle_60x; 586 } 587 588 static int 589 cpu_feature_bit(SYSCTL_HANDLER_ARGS) 590 { 591 int result; 592 593 result = (cpu_features & arg2) ? 1 : 0; 594 595 return (sysctl_handle_int(oidp, &result, 0, req)); 596 } 597 598 void 599 cpu_idle(int busy) 600 { 601 sbintime_t sbt = -1; 602 603 #ifdef INVARIANTS 604 if ((mfmsr() & PSL_EE) != PSL_EE) { 605 struct thread *td = curthread; 606 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr); 607 panic("ints disabled in idleproc!"); 608 } 609 #endif 610 611 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 612 busy, curcpu); 613 614 if (cpu_idle_hook != NULL) { 615 if (!busy) { 616 critical_enter(); 617 sbt = cpu_idleclock(); 618 } 619 cpu_idle_hook(sbt); 620 if (!busy) { 621 cpu_activeclock(); 622 critical_exit(); 623 } 624 } 625 626 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 627 busy, curcpu); 628 } 629 630 static void 631 cpu_idle_60x(sbintime_t sbt) 632 { 633 register_t msr; 634 uint16_t vers; 635 636 if (!powerpc_pow_enabled) 637 return; 638 639 msr = mfmsr(); 640 vers = mfpvr() >> 16; 641 642 #ifdef AIM 643 switch (vers) { 644 case IBM970: 645 case IBM970FX: 646 case IBM970MP: 647 case MPC7447A: 648 case MPC7448: 649 case MPC7450: 650 case MPC7455: 651 case MPC7457: 652 __asm __volatile("\ 653 dssall; sync; mtmsr %0; isync" 654 :: "r"(msr | PSL_POW)); 655 break; 656 default: 657 powerpc_sync(); 658 mtmsr(msr | PSL_POW); 659 isync(); 660 break; 661 } 662 #endif 663 } 664 665 static void 666 cpu_idle_booke(sbintime_t sbt) 667 { 668 669 #ifdef BOOKE_E500 670 platform_cpu_idle(PCPU_GET(cpuid)); 671 #endif 672 } 673 674