1 /* $NetBSD: db_disasm.c,v 1.28 2013/07/04 23:00:23 joerg Exp $ */ 2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 3 4 #include <sys/param.h> 5 #include <sys/proc.h> 6 #include <sys/systm.h> 7 8 #include <machine/db_machdep.h> 9 10 #include <ddb/ddb.h> 11 #include <ddb/db_access.h> 12 #include <ddb/db_sym.h> 13 #include <ddb/db_variables.h> 14 #include <ddb/db_output.h> 15 16 enum function_mask { 17 Op_A = 0x00000001, 18 Op_B = 0x00000002, 19 Op_BI = 0x00000004, 20 Op_BO = 0x00000008, 21 Op_BC = Op_BI | Op_BO, 22 Op_CRM = 0x00000010, 23 Op_D = 0x00000020, 24 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ 25 Op_S = 0x00000040, /* S-field is swapped with A-field */ 26 Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */ 27 Op_dA = 0x00000080, 28 Op_LK = 0x00000100, 29 Op_Rc = 0x00000200, 30 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 31 Op_LKM = Op_AA, 32 Op_RcM = Op_AA, 33 Op_OE = 0x00000400, 34 Op_SR = 0x00000800, 35 Op_TO = 0x00001000, 36 Op_sign = 0x00002000, 37 Op_const = 0x00004000, 38 Op_SIMM = Op_const | Op_sign, 39 Op_UIMM = Op_const, 40 Op_crbA = 0x00008000, 41 Op_crbB = 0x00010000, 42 Op_WS = Op_crbB, /* kludge, same field as crbB */ 43 Op_rSH = Op_crbB, /* kludge, same field as crbB */ 44 Op_crbD = 0x00020000, 45 Op_crfD = 0x00040000, 46 Op_crfS = 0x00080000, 47 Op_ds = 0x00100000, 48 Op_me = 0x00200000, 49 Op_spr = 0x00400000, 50 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 51 Op_tbr = 0x00800000, 52 53 Op_BP = 0x01000000, 54 Op_BD = 0x02000000, 55 Op_LI = 0x04000000, 56 Op_C = 0x08000000, 57 58 Op_NB = 0x10000000, 59 60 Op_sh_mb_sh = 0x20000000, 61 Op_sh = 0x40000000, 62 Op_SH = Op_sh | Op_sh_mb_sh, 63 Op_mb = 0x80000000, 64 Op_MB = Op_mb | Op_sh_mb_sh, 65 Op_ME = Op_MB, 66 67 }; 68 69 struct opcode { 70 const char *name; 71 u_int32_t mask; 72 u_int32_t code; 73 enum function_mask func; 74 }; 75 76 typedef u_int32_t instr_t; 77 typedef void (op_class_func) (instr_t, vm_offset_t); 78 79 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 80 void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 81 char *disasm_str, size_t slen); 82 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); 83 84 op_class_func op_ill, op_base; 85 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 86 op_class_func op_cl_x3a, op_cl_x3b; 87 op_class_func op_cl_x3e, op_cl_x3f; 88 89 op_class_func *opcodes_base[] = { 90 /*x00*/ op_ill, op_ill, op_base, op_ill, 91 /*x04*/ op_ill, op_ill, op_ill, op_base, 92 /*x08*/ op_base, op_base, op_base, op_base, 93 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 94 /*x10*/ op_base, op_base, op_base, op_cl_x13, 95 /*x14*/ op_base, op_base, op_ill, op_base, 96 /*x18*/ op_base, op_base, op_base, op_base, 97 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 98 /*x20*/ op_base, op_base, op_base, op_base, 99 /*x24*/ op_base, op_base, op_base, op_base, 100 /*x28*/ op_base, op_base, op_base, op_base, 101 /*x2C*/ op_base, op_base, op_base, op_base, 102 /*x30*/ op_base, op_base, op_base, op_base, 103 /*x34*/ op_base, op_base, op_base, op_base, 104 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 105 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 106 }; 107 108 /* This table could be modified to make significant the "reserved" fields 109 * of the opcodes, But I didn't feel like it when typing in the table, 110 * I would recommend that this table be looked over for errors, 111 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 112 * PowerPC Microprocessor Family: The Programming Environments 113 */ 114 115 const struct opcode opcodes[] = { 116 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 117 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 118 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 119 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 120 { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM }, 121 { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM }, 122 { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM }, 123 { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM }, 124 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 125 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 126 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 127 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 128 { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */ 129 { "sc", 0xffffffff, 0x44000002, 0 }, 130 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 131 132 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 133 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 134 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 135 136 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 137 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 138 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 139 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 140 141 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 142 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 143 144 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA }, 145 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA }, 146 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA }, 147 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA }, 148 { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA }, 149 { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA }, 150 { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA }, 151 { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA }, 152 153 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA }, 154 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA }, 155 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA }, 156 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA }, 157 { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA }, 158 { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA }, 159 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA }, 160 { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA }, 161 162 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA }, 163 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA }, 164 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA }, 165 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA }, 166 167 { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA }, 168 { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA }, 169 { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA }, 170 { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA }, 171 { "", 0x0, 0x0, 0 } 172 173 }; 174 /* 13 * 4 = 4c */ 175 const struct opcode opcodes_13[] = { 176 /* 0x13 << 2 */ 177 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 178 { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */ 179 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 180 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 181 { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB }, 182 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 183 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 184 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 185 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 186 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 187 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 188 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 189 { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */ 190 { "", 0x0, 0x0, 0 } 191 }; 192 193 /* 1e * 4 = 78 */ 194 const struct opcode opcodes_1e[] = { 195 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 196 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 197 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 198 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 199 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 200 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 201 { "", 0x0, 0x0, 0 } 202 }; 203 204 /* 1f * 4 = 7c */ 205 const struct opcode opcodes_1f[] = { 206 /* 1f << 2 */ 207 { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B }, 208 { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B }, 209 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 210 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 211 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 212 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 213 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 214 { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B }, 215 { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B }, 216 { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B }, 217 218 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 219 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 220 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 221 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 222 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 223 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_S | Op_A | Op_Rc }, 224 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 225 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 226 { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B }, 227 { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B }, 228 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 229 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 230 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 231 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 232 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 233 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 234 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 235 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 236 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 237 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 238 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 239 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 240 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 241 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 242 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 243 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 244 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 245 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 246 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 247 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 248 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 249 { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B }, 250 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B }, 251 { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B }, 252 { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */ 253 { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B }, 254 { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B }, 255 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 256 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 257 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 258 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B }, 259 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B }, 260 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 261 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 262 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 263 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 264 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 265 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 266 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B }, 267 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 268 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 269 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 270 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 271 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 272 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 273 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 274 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 275 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 276 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 277 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 278 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 279 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 280 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 281 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 282 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 283 { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B }, 284 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 285 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc }, 286 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 287 { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B }, 288 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 289 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 290 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 291 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 292 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 293 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 294 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 295 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 296 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 297 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 298 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 299 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 300 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 301 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 302 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 303 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 304 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 305 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 306 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 307 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 308 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 309 { "sync", 0xfc6007fe, 0x7c0004ac, 0 }, 310 { "lwsync", 0xfc6007fe, 0x7c2004ac, 0 }, 311 { "ptesync", 0xfc6007fe, 0x7c4004ac, 0 }, 312 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 313 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 314 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 315 { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B }, 316 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B }, 317 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B }, 318 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B }, 319 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB }, 320 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B }, 321 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B }, 322 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 323 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 324 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 325 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc }, 326 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 327 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 328 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 329 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B }, 330 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc }, 331 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 332 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 333 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 334 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 335 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B }, 336 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 337 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 338 { "", 0x0, 0x0, 0 } 339 }; 340 341 /* 3a * 4 = e8 */ 342 const struct opcode opcodes_3a[] = { 343 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 344 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 345 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 346 { "", 0x0, 0x0, 0 } 347 }; 348 /* 3b * 4 = ec */ 349 const struct opcode opcodes_3b[] = { 350 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 351 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 352 353 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 354 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 355 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 356 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 357 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 358 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 359 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 360 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 361 { "", 0x0, 0x0, 0 } 362 }; 363 /* 3e * 4 = f8 */ 364 const struct opcode opcodes_3e[] = { 365 { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds }, 366 { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds }, 367 { "", 0x0, 0x0, 0 } 368 }; 369 370 /* 3f * 4 = fc */ 371 const struct opcode opcodes_3f[] = { 372 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 373 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 374 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 375 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 376 377 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 378 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 379 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 380 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 381 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 382 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 383 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 384 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 385 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 386 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 387 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 388 389 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 390 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 391 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 392 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 393 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 394 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 395 { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */ 396 397 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 398 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 399 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 400 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 401 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 402 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 403 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 404 { "", 0x0, 0x0, 0 } 405 }; 406 407 struct specialreg { 408 int reg; 409 const char *name; 410 }; 411 412 const struct specialreg sprregs[] = { 413 { 0x000, "mq" }, 414 { 0x001, "xer" }, 415 { 0x008, "lr" }, 416 { 0x009, "ctr" }, 417 { 0x012, "dsisr" }, 418 { 0x013, "dar" }, 419 { 0x016, "dec" }, 420 { 0x019, "sdr1" }, 421 { 0x01a, "srr0" }, 422 { 0x01b, "srr1" }, 423 { 0x100, "vrsave" }, 424 { 0x110, "sprg0" }, 425 { 0x111, "sprg1" }, 426 { 0x112, "sprg2" }, 427 { 0x113, "sprg3" }, 428 { 0x114, "sprg4" }, 429 { 0x115, "sprg5" }, 430 { 0x116, "sprg6" }, 431 { 0x117, "sprg7" }, 432 { 0x118, "asr" }, 433 { 0x11a, "aer" }, 434 { 0x11c, "tbl" }, 435 { 0x11d, "tbu" }, 436 { 0x11f, "pvr" }, 437 { 0x210, "ibat0u" }, 438 { 0x211, "ibat0l" }, 439 { 0x212, "ibat1u" }, 440 { 0x213, "ibat1l" }, 441 { 0x214, "ibat2u" }, 442 { 0x215, "ibat2l" }, 443 { 0x216, "ibat3u" }, 444 { 0x217, "ibat3l" }, 445 { 0x218, "dbat0u" }, 446 { 0x219, "dbat0l" }, 447 { 0x21a, "dbat1u" }, 448 { 0x21b, "dbat1l" }, 449 { 0x21c, "dbat2u" }, 450 { 0x21d, "dbat2l" }, 451 { 0x21e, "dbat3u" }, 452 { 0x21f, "dbat3l" }, 453 { 0x230, "ibat4u" }, 454 { 0x231, "ibat4l" }, 455 { 0x232, "ibat5u" }, 456 { 0x233, "ibat5l" }, 457 { 0x234, "ibat6u" }, 458 { 0x235, "ibat6l" }, 459 { 0x236, "ibat7u" }, 460 { 0x237, "ibat7l" }, 461 { 0x238, "dbat4u" }, 462 { 0x239, "dbat4l" }, 463 { 0x23a, "dbat5u" }, 464 { 0x23b, "dbat5l" }, 465 { 0x23c, "dbat6u" }, 466 { 0x23d, "dbat6l" }, 467 { 0x23e, "dbat7u" }, 468 { 0x23f, "dbat7l" }, 469 { 0x3b0, "zpr" }, 470 { 0x3b1, "pid" }, 471 { 0x3b3, "ccr0" }, 472 { 0x3b4, "iac3" }, 473 { 0x3b5, "iac4" }, 474 { 0x3b6, "dvc1" }, 475 { 0x3b7, "dvc2" }, 476 { 0x3b9, "sgr" }, 477 { 0x3ba, "dcwr" }, 478 { 0x3bb, "sler" }, 479 { 0x3bc, "su0r" }, 480 { 0x3bd, "dbcr1" }, 481 { 0x3d3, "icdbdr" }, 482 { 0x3d4, "esr" }, 483 { 0x3d5, "dear" }, 484 { 0x3d6, "evpr" }, 485 { 0x3d8, "tsr" }, 486 { 0x3da, "tcr" }, 487 { 0x3db, "pit" }, 488 { 0x3de, "srr2" }, 489 { 0x3df, "srr3" }, 490 { 0x3f0, "hid0" }, 491 { 0x3f1, "hid1" }, 492 { 0x3f2, "iabr" }, 493 { 0x3f3, "hid2" }, 494 { 0x3f5, "dabr" }, 495 { 0x3f6, "msscr0" }, 496 { 0x3f7, "msscr1" }, 497 { 0x3f9, "l2cr" }, 498 { 0x3fa, "dccr" }, 499 { 0x3fb, "iccr" }, 500 { 0x3ff, "pir" }, 501 { 0, NULL } 502 }; 503 504 const struct specialreg dcrregs[] = { 505 { 0x010, "sdram0_cfgaddr" }, 506 { 0x011, "sdram0_cfgdata" }, 507 { 0x012, "ebc0_cfgaddr" }, 508 { 0x013, "ebc0_cfgdata" }, 509 { 0x014, "dcp0_cfgaddr" }, 510 { 0x015, "dcp0_cfgdata" }, 511 { 0x018, "ocm0_isarc" }, 512 { 0x019, "ocm0_iscntl" }, 513 { 0x01a, "ocm0_dsarc" }, 514 { 0x01b, "ocm0_dscntl" }, 515 { 0x084, "plb0_besr" }, 516 { 0x086, "plb0_bear" }, 517 { 0x087, "plb0_acr" }, 518 { 0x0a0, "pob0_besr0" }, 519 { 0x0a2, "pob0_bear" }, 520 { 0x0a4, "pob0_besr1" }, 521 { 0x0b0, "cpc0_pllmr" }, 522 { 0x0b1, "cpc0_cr0" }, 523 { 0x0b2, "cpc0_cr1" }, 524 { 0x0b4, "cpc0_psr" }, 525 { 0x0b5, "cpc0_jtagid" }, 526 { 0x0b8, "cpc0_sr" }, 527 { 0x0b9, "cpc0_er" }, 528 { 0x0ba, "cpc0_fr" }, 529 { 0x0c0, "uic0_sr" }, 530 { 0x0c2, "uic0_er" }, 531 { 0x0c3, "uic0_cr" }, 532 { 0x0c4, "uic0_pr" }, 533 { 0x0c5, "uic0_tr" }, 534 { 0x0c6, "uic0_msr" }, 535 { 0x0c7, "uic0_vr" }, 536 { 0x0c8, "uic0_vcr" }, 537 { 0x100, "dma0_cr0" }, 538 { 0x101, "dma0_ct0" }, 539 { 0x102, "dma0_da0" }, 540 { 0x103, "dma0_sa0" }, 541 { 0x104, "dma0_sg0" }, 542 { 0x108, "dma0_cr1" }, 543 { 0x109, "dma0_ct1" }, 544 { 0x10a, "dma0_da1" }, 545 { 0x10b, "dma0_sa1" }, 546 { 0x10c, "dma0_sg1" }, 547 { 0x110, "dma0_cr2" }, 548 { 0x111, "dma0_ct2" }, 549 { 0x112, "dma0_da2" }, 550 { 0x113, "dma0_sa2" }, 551 { 0x114, "dma0_sg2" }, 552 { 0x118, "dma0_cr3" }, 553 { 0x119, "dma0_ct3" }, 554 { 0x11a, "dma0_da3" }, 555 { 0x11b, "dma0_sa3" }, 556 { 0x11c, "dma0_sg3" }, 557 { 0x120, "dma0_sr" }, 558 { 0x123, "dma0_sgc" }, 559 { 0x125, "dma0_slp" }, 560 { 0x126, "dma0_pol" }, 561 { 0x180, "mal0_cfg" }, 562 { 0x181, "mal0_esr" }, 563 { 0x182, "mal0_ier" }, 564 { 0x184, "mal0_txcasr" }, 565 { 0x185, "mal0_txcarr" }, 566 { 0x186, "mal0_txeobisr" }, 567 { 0x187, "mal0_txdeir" }, 568 { 0x190, "mal0_rxcasr" }, 569 { 0x191, "mal0_rxcarr" }, 570 { 0x192, "mal0_rxeobisr" }, 571 { 0x193, "mal0_rxdeir" }, 572 { 0x1a0, "mal0_txctp0r" }, 573 { 0x1a1, "mal0_txctp1r" }, 574 { 0x1a2, "mal0_txctp2r" }, 575 { 0x1a3, "mal0_txctp3r" }, 576 { 0x1c0, "mal0_rxctp0r" }, 577 { 0x1e0, "mal0_rcbs0" }, 578 { 0, NULL } 579 }; 580 581 static const char *condstr[8] = { 582 "ge", "le", "ne", "ns", "lt", "gt", "eq", "so" 583 }; 584 585 void 586 op_ill(instr_t instr, vm_offset_t loc) 587 { 588 db_printf("illegal instruction %x\n", instr); 589 } 590 591 u_int32_t 592 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 593 { 594 u_int32_t mask = (1 << width) - 1; 595 return ((value >> base) & mask); 596 } 597 598 const struct opcode * search_op(const struct opcode *); 599 600 void 601 disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 602 char *disasm_str, size_t slen) 603 { 604 char * pstr; 605 enum function_mask func; 606 int len; 607 608 #define ADD_LEN(s) do { \ 609 len = (s); \ 610 slen -= len; \ 611 pstr += len; \ 612 } while(0) 613 #define APP_PSTR(fmt, arg) ADD_LEN(snprintf(pstr, slen, (fmt), (arg))) 614 #define APP_PSTRS(fmt) ADD_LEN(snprintf(pstr, slen, "%s", (fmt))) 615 616 pstr = disasm_str; 617 618 func = popcode->func; 619 if (func & Op_BC) { 620 u_int BO, BI; 621 BO = extract_field(instr, 31 - 10, 5); 622 BI = extract_field(instr, 31 - 15, 5); 623 func &= ~Op_BC; 624 if (BO & 4) { 625 /* standard, no decrement */ 626 if (BO & 16) { 627 if (popcode->code == 0x40000000) { 628 APP_PSTRS("c"); 629 func |= Op_BO | Op_BI; 630 } 631 } 632 else { 633 APP_PSTRS(condstr[((BO & 8) >> 1) + (BI & 3)]); 634 if (BI >= 4) 635 func |= Op_crfS; 636 } 637 } 638 else { 639 /* decrement and branch */ 640 if (BO & 2) 641 APP_PSTRS("dz"); 642 else 643 APP_PSTRS("dnz"); 644 if ((BO & 24) == 0) 645 APP_PSTRS("f"); 646 else if ((BO & 24) == 8) 647 APP_PSTRS("t"); 648 else 649 func |= Op_BI; 650 } 651 if (popcode->code == 0x4c000020) 652 APP_PSTRS("lr"); 653 else if (popcode->code == 0x4c000420) 654 APP_PSTRS("ctr"); 655 if ((BO & 20) != 20 && (func & Op_BO) == 0) 656 func |= Op_BP; /* branch prediction hint */ 657 } 658 if (func & Op_OE) { 659 u_int OE; 660 OE = extract_field(instr, 31 - 21, 1); 661 if (OE) { 662 APP_PSTRS("o"); 663 } 664 func &= ~Op_OE; 665 } 666 switch (func & Op_LKM) { 667 case Op_Rc: 668 if (instr & 0x1) 669 APP_PSTRS("."); 670 break; 671 case Op_AA: 672 if (instr & 0x1) 673 APP_PSTRS("l"); 674 if (instr & 0x2) { 675 APP_PSTRS("a"); 676 loc = 0; /* Absolute address */ 677 } 678 break; 679 case Op_LK: 680 if (instr & 0x1) 681 APP_PSTRS("l"); 682 break; 683 default: 684 func &= ~Op_LKM; 685 } 686 if (func & Op_BP) { 687 int y; 688 y = (instr & 0x200000) != 0; 689 if (popcode->code == 0x40000000) { 690 int BD; 691 BD = extract_field(instr, 31 - 29, 14); 692 BD = BD << 18; 693 BD = BD >> 16; 694 BD += loc; 695 if ((vm_offset_t)BD < loc) 696 y ^= 1; 697 } 698 APP_PSTR("%c", y ? '+' : '-'); 699 func &= ~Op_BP; 700 } 701 APP_PSTRS("\t"); 702 703 /* XXX: special cases here, out of flags in a 32bit word. */ 704 if (strcmp(popcode->name, "wrteei") == 0) { 705 int E; 706 E = extract_field(instr, 31 - 16, 5); 707 APP_PSTR("%d", E); 708 return; 709 } 710 else if (strcmp(popcode->name, "mtfsfi") == 0) { 711 u_int UI; 712 UI = extract_field(instr, 31 - 8, 3); 713 APP_PSTR("crf%u, ", UI); 714 UI = extract_field(instr, 31 - 19, 4); 715 APP_PSTR("0x%x", UI); 716 } 717 /* XXX: end of special cases here. */ 718 719 if ((func & Op_FM) == Op_FM) { 720 u_int FM; 721 FM = extract_field(instr, 31 - 14, 8); 722 APP_PSTR("0x%x, ", FM); 723 func &= ~Op_FM; 724 } 725 if (func & Op_D) { /* Op_ST is the same */ 726 u_int D; 727 D = extract_field(instr, 31 - 10, 5); 728 APP_PSTR("r%d, ", D); 729 func &= ~Op_D; 730 } 731 if (func & Op_crbD) { 732 u_int crbD; 733 crbD = extract_field(instr, 31 - 10, 5); 734 APP_PSTR("crb%d, ", crbD); 735 func &= ~Op_crbD; 736 } 737 if (func & Op_crfD) { 738 u_int crfD; 739 crfD = extract_field(instr, 31 - 8, 3); 740 APP_PSTR("crf%d, ", crfD); 741 func &= ~Op_crfD; 742 } 743 if (func & Op_TO) { 744 u_int TO; 745 TO = extract_field(instr, 31 - 10, 1); 746 APP_PSTR("%d, ", TO); 747 func &= ~Op_TO; 748 } 749 if (func & Op_crfS) { 750 u_int crfS; 751 crfS = extract_field(instr, 31 - 13, 3); 752 APP_PSTR("crf%d, ", crfS); 753 func &= ~Op_crfS; 754 } 755 if (func & Op_CRM) { 756 u_int CRM; 757 CRM = extract_field(instr, 31 - 19, 8); 758 APP_PSTR("0x%x, ", CRM); 759 func &= ~Op_CRM; 760 } 761 if (func & Op_BO) { 762 u_int BO; 763 BO = extract_field(instr, 31 - 10, 5); 764 APP_PSTR("%d, ", BO); 765 func &= ~Op_BO; 766 } 767 if (func & Op_BI) { 768 u_int BI; 769 BI = extract_field(instr, 31 - 15, 5); 770 APP_PSTR("%d, ", BI); 771 func &= ~Op_BI; 772 } 773 if (func & Op_dA) { /* register A indirect with displacement */ 774 u_int A; 775 A = extract_field(instr, 31 - 31, 16); 776 if (A & 0x8000) { 777 APP_PSTRS("-"); 778 A = 0x10000-A; 779 } 780 APP_PSTR("0x%x", A); 781 A = extract_field(instr, 31 - 15, 5); 782 APP_PSTR("(r%d)", A); 783 func &= ~Op_dA; 784 } 785 if (func & Op_spr) { 786 u_int spr; 787 u_int sprl; 788 u_int sprh; 789 const struct specialreg *regs; 790 int i; 791 sprl = extract_field(instr, 31 - 15, 5); 792 sprh = extract_field(instr, 31 - 20, 5); 793 spr = sprh << 5 | sprl; 794 795 /* ugly hack - out of bitfields in the function mask */ 796 if (popcode->name[2] == 'd') /* m.Dcr */ 797 regs = dcrregs; 798 else 799 regs = sprregs; 800 for (i = 0; regs[i].name != NULL; i++) 801 if (spr == regs[i].reg) 802 break; 803 if (regs[i].name == NULL) 804 APP_PSTR("[unknown special reg (%d)]", spr); 805 else 806 APP_PSTR("%s", regs[i].name); 807 808 if (popcode->name[1] == 't') /* spr is destination */ 809 APP_PSTRS(", "); 810 func &= ~Op_spr; 811 } 812 if (func & Op_SR) { 813 u_int SR; 814 SR = extract_field(instr, 31 - 15, 3); 815 APP_PSTR("sr%d", SR); 816 if (popcode->name[1] == 't') /* SR is destination */ 817 APP_PSTRS(", "); 818 func &= ~Op_SR; 819 } 820 if (func & Op_A) { 821 u_int A; 822 A = extract_field(instr, 31 - 15, 5); 823 APP_PSTR("r%d, ", A); 824 func &= ~Op_A; 825 } 826 if (func & Op_S) { 827 u_int D; 828 D = extract_field(instr, 31 - 10, 5); 829 APP_PSTR("r%d, ", D); 830 func &= ~Op_S; 831 } 832 if (func & Op_C) { 833 u_int C; 834 C = extract_field(instr, 31 - 25, 5); 835 APP_PSTR("r%d, ", C); 836 func &= ~Op_C; 837 } 838 if (func & Op_B) { 839 u_int B; 840 B = extract_field(instr, 31 - 20, 5); 841 APP_PSTR("r%d", B); 842 func &= ~Op_B; 843 } 844 if (func & Op_crbA) { 845 u_int crbA; 846 crbA = extract_field(instr, 31 - 15, 5); 847 APP_PSTR("%d, ", crbA); 848 func &= ~Op_crbA; 849 } 850 if (func & Op_crbB) { 851 u_int crbB; 852 crbB = extract_field(instr, 31 - 20, 5); 853 APP_PSTR("%d, ", crbB); 854 func &= ~Op_crbB; 855 } 856 if (func & Op_LI) { 857 int LI; 858 LI = extract_field(instr, 31 - 29, 24); 859 LI = LI << 8; 860 LI = LI >> 6; 861 LI += loc; 862 APP_PSTR("0x%x", LI); 863 func &= ~Op_LI; 864 } 865 switch (func & Op_SIMM) { 866 u_int IMM; 867 case Op_SIMM: /* same as Op_d */ 868 IMM = extract_field(instr, 31 - 31, 16); 869 if (IMM & 0x8000) { 870 APP_PSTRS("-"); 871 IMM = 0x10000-IMM; 872 } 873 func &= ~Op_SIMM; 874 goto common; 875 case Op_UIMM: 876 IMM = extract_field(instr, 31 - 31, 16); 877 func &= ~Op_UIMM; 878 goto common; 879 common: 880 APP_PSTR("0x%x", IMM); 881 break; 882 default: 883 ; 884 } 885 if (func & Op_BD) { 886 int BD; 887 BD = extract_field(instr, 31 - 29, 14); 888 BD = BD << 18; 889 BD = BD >> 16; 890 BD += loc; 891 /* Need to sign extend and shift up 2, then add addr */ 892 APP_PSTR("0x%x", BD); 893 func &= ~Op_BD; 894 } 895 if (func & Op_ds) { 896 u_int ds; 897 ds = extract_field(instr, 31 - 29, 14) << 2; 898 APP_PSTR("0x%x", ds); 899 func &= ~Op_ds; 900 } 901 if (func & Op_me) { 902 u_int me, mel, meh; 903 mel = extract_field(instr, 31 - 25, 4); 904 meh = extract_field(instr, 31 - 26, 1); 905 me = meh << 4 | mel; 906 APP_PSTR(", 0x%x", me); 907 func &= ~Op_me; 908 } 909 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 910 u_int SH; 911 SH = extract_field(instr, 31 - 20, 5); 912 APP_PSTR("%d", SH); 913 } 914 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 915 u_int MB; 916 u_int ME; 917 MB = extract_field(instr, 31 - 25, 5); 918 APP_PSTR(", %d", MB); 919 ME = extract_field(instr, 31 - 30, 5); 920 APP_PSTR(", %d", ME); 921 } 922 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 923 u_int sh, shl, shh; 924 shl = extract_field(instr, 31 - 19, 4); 925 shh = extract_field(instr, 31 - 20, 1); 926 sh = shh << 4 | shl; 927 APP_PSTR(", %d", sh); 928 } 929 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 930 u_int mb, mbl, mbh; 931 mbl = extract_field(instr, 31 - 25, 4); 932 mbh = extract_field(instr, 31 - 26, 1); 933 mb = mbh << 4 | mbl; 934 APP_PSTR(", %d", mb); 935 } 936 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 937 u_int me, mel, meh; 938 mel = extract_field(instr, 31 - 25, 4); 939 meh = extract_field(instr, 31 - 26, 1); 940 me = meh << 4 | mel; 941 APP_PSTR(", %d", me); 942 } 943 if (func & Op_tbr) { 944 u_int tbr; 945 u_int tbrl; 946 u_int tbrh; 947 const char *reg; 948 tbrl = extract_field(instr, 31 - 15, 5); 949 tbrh = extract_field(instr, 31 - 20, 5); 950 tbr = tbrh << 5 | tbrl; 951 952 switch (tbr) { 953 case 268: 954 reg = "tbl"; 955 break; 956 case 269: 957 reg = "tbu"; 958 break; 959 default: 960 reg = NULL; 961 } 962 if (reg == NULL) 963 APP_PSTR(", [unknown tbr %d ]", tbr); 964 else 965 APP_PSTR(", %s", reg); 966 func &= ~Op_tbr; 967 } 968 if (func & Op_NB) { 969 u_int NB; 970 NB = extract_field(instr, 31 - 20, 5); 971 if (NB == 0) 972 NB = 32; 973 APP_PSTR(", %d", NB); 974 func &= ~Op_SR; 975 } 976 #undef ADD_LEN 977 #undef APP_PSTR 978 #undef APP_PSTRS 979 } 980 981 void 982 op_base(instr_t instr, vm_offset_t loc) 983 { 984 dis_ppc(opcodes, instr, loc); 985 } 986 987 void 988 op_cl_x13(instr_t instr, vm_offset_t loc) 989 { 990 dis_ppc(opcodes_13, instr, loc); 991 } 992 993 void 994 op_cl_x1e(instr_t instr, vm_offset_t loc) 995 { 996 dis_ppc(opcodes_1e, instr, loc); 997 } 998 999 void 1000 op_cl_x1f(instr_t instr, vm_offset_t loc) 1001 { 1002 dis_ppc(opcodes_1f, instr, loc); 1003 } 1004 1005 void 1006 op_cl_x3a(instr_t instr, vm_offset_t loc) 1007 { 1008 dis_ppc(opcodes_3a, instr, loc); 1009 } 1010 1011 void 1012 op_cl_x3b(instr_t instr, vm_offset_t loc) 1013 { 1014 dis_ppc(opcodes_3b, instr, loc); 1015 } 1016 1017 void 1018 op_cl_x3e(instr_t instr, vm_offset_t loc) 1019 { 1020 dis_ppc(opcodes_3e, instr, loc); 1021 } 1022 1023 void 1024 op_cl_x3f(instr_t instr, vm_offset_t loc) 1025 { 1026 dis_ppc(opcodes_3f, instr, loc); 1027 } 1028 1029 void 1030 dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) 1031 { 1032 const struct opcode *op; 1033 int found = 0; 1034 int i; 1035 char disasm_str[80]; 1036 1037 for (i = 0, op = &opcodeset[0]; 1038 found == 0 && op->mask != 0; 1039 i++, op = &opcodeset[i]) { 1040 if ((instr & op->mask) == op->code) { 1041 found = 1; 1042 disasm_fields(op, instr, loc, disasm_str, 1043 sizeof disasm_str); 1044 db_printf("%s%s\n", op->name, disasm_str); 1045 return; 1046 } 1047 } 1048 op_ill(instr, loc); 1049 } 1050 1051 db_addr_t 1052 db_disasm(db_addr_t loc, bool extended) 1053 { 1054 int class; 1055 instr_t opcode; 1056 opcode = *(instr_t *)(loc); 1057 if (extended) 1058 db_printf("|%08x| ", opcode); 1059 class = opcode >> 26; 1060 (opcodes_base[class])(opcode, loc); 1061 1062 return (loc + 4); 1063 } 1064 1065 vm_offset_t opc_disasm(vm_offset_t loc, int); 1066 1067 vm_offset_t 1068 opc_disasm(vm_offset_t loc, int xin) 1069 { 1070 int class; 1071 instr_t opcode; 1072 opcode = xin; 1073 class = opcode >> 26; 1074 (opcodes_base[class])(opcode, loc); 1075 1076 return (loc + 4); 1077 } 1078