1 /* $NetBSD: db_disasm.c,v 1.28 2013/07/04 23:00:23 joerg Exp $ */ 2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 3 4 #include <sys/cdefs.h> 5 #include <sys/param.h> 6 #include <sys/proc.h> 7 #include <sys/systm.h> 8 9 #include <machine/db_machdep.h> 10 11 #include <ddb/ddb.h> 12 #include <ddb/db_access.h> 13 #include <ddb/db_sym.h> 14 #include <ddb/db_variables.h> 15 #include <ddb/db_output.h> 16 17 enum function_mask { 18 Op_A = 0x00000001, 19 Op_B = 0x00000002, 20 Op_BI = 0x00000004, 21 Op_BO = 0x00000008, 22 Op_BC = Op_BI | Op_BO, 23 Op_CRM = 0x00000010, 24 Op_D = 0x00000020, 25 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ 26 Op_S = 0x00000040, /* S-field is swapped with A-field */ 27 Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */ 28 Op_dA = 0x00000080, 29 Op_LK = 0x00000100, 30 Op_Rc = 0x00000200, 31 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 32 Op_LKM = Op_AA, 33 Op_RcM = Op_AA, 34 Op_OE = 0x00000400, 35 Op_SR = 0x00000800, 36 Op_TO = 0x00001000, 37 Op_sign = 0x00002000, 38 Op_const = 0x00004000, 39 Op_SIMM = Op_const | Op_sign, 40 Op_UIMM = Op_const, 41 Op_crbA = 0x00008000, 42 Op_crbB = 0x00010000, 43 Op_WS = Op_crbB, /* kludge, same field as crbB */ 44 Op_rSH = Op_crbB, /* kludge, same field as crbB */ 45 Op_crbD = 0x00020000, 46 Op_crfD = 0x00040000, 47 Op_crfS = 0x00080000, 48 Op_ds = 0x00100000, 49 Op_me = 0x00200000, 50 Op_spr = 0x00400000, 51 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 52 Op_tbr = 0x00800000, 53 54 Op_BP = 0x01000000, 55 Op_BD = 0x02000000, 56 Op_LI = 0x04000000, 57 Op_C = 0x08000000, 58 59 Op_NB = 0x10000000, 60 61 Op_sh_mb_sh = 0x20000000, 62 Op_sh = 0x40000000, 63 Op_SH = Op_sh | Op_sh_mb_sh, 64 Op_mb = 0x80000000, 65 Op_MB = Op_mb | Op_sh_mb_sh, 66 Op_ME = Op_MB, 67 68 }; 69 70 struct opcode { 71 const char *name; 72 u_int32_t mask; 73 u_int32_t code; 74 enum function_mask func; 75 }; 76 77 typedef u_int32_t instr_t; 78 typedef void (op_class_func) (instr_t, vm_offset_t); 79 80 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 81 void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 82 char *disasm_str, size_t slen); 83 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); 84 85 op_class_func op_ill, op_base; 86 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 87 op_class_func op_cl_x3a, op_cl_x3b; 88 op_class_func op_cl_x3e, op_cl_x3f; 89 90 op_class_func *opcodes_base[] = { 91 /*x00*/ op_ill, op_ill, op_base, op_ill, 92 /*x04*/ op_ill, op_ill, op_ill, op_base, 93 /*x08*/ op_base, op_base, op_base, op_base, 94 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 95 /*x10*/ op_base, op_base, op_base, op_cl_x13, 96 /*x14*/ op_base, op_base, op_ill, op_base, 97 /*x18*/ op_base, op_base, op_base, op_base, 98 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 99 /*x20*/ op_base, op_base, op_base, op_base, 100 /*x24*/ op_base, op_base, op_base, op_base, 101 /*x28*/ op_base, op_base, op_base, op_base, 102 /*x2C*/ op_base, op_base, op_base, op_base, 103 /*x30*/ op_base, op_base, op_base, op_base, 104 /*x34*/ op_base, op_base, op_base, op_base, 105 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 106 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 107 }; 108 109 /* This table could be modified to make significant the "reserved" fields 110 * of the opcodes, But I didn't feel like it when typing in the table, 111 * I would recommend that this table be looked over for errors, 112 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 113 * PowerPC Microprocessor Family: The Programming Environments 114 */ 115 116 const struct opcode opcodes[] = { 117 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 118 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 119 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 120 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 121 { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM }, 122 { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM }, 123 { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM }, 124 { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM }, 125 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 126 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 127 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 128 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 129 { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */ 130 { "sc", 0xffffffff, 0x44000002, 0 }, 131 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 132 133 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 134 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 135 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 136 137 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 138 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 139 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 140 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 141 142 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 143 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 144 145 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA }, 146 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA }, 147 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA }, 148 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA }, 149 { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA }, 150 { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA }, 151 { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA }, 152 { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA }, 153 154 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA }, 155 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA }, 156 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA }, 157 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA }, 158 { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA }, 159 { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA }, 160 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA }, 161 { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA }, 162 163 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA }, 164 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA }, 165 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA }, 166 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA }, 167 168 { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA }, 169 { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA }, 170 { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA }, 171 { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA }, 172 { "", 0x0, 0x0, 0 } 173 174 }; 175 /* 13 * 4 = 4c */ 176 const struct opcode opcodes_13[] = { 177 /* 0x13 << 2 */ 178 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 179 { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */ 180 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 181 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 182 { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB }, 183 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 184 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 185 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 186 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 187 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 188 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 189 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 190 { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */ 191 { "", 0x0, 0x0, 0 } 192 }; 193 194 /* 1e * 4 = 78 */ 195 const struct opcode opcodes_1e[] = { 196 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 197 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 198 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 199 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 200 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 201 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 202 { "", 0x0, 0x0, 0 } 203 }; 204 205 /* 1f * 4 = 7c */ 206 const struct opcode opcodes_1f[] = { 207 /* 1f << 2 */ 208 { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B }, 209 { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B }, 210 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 211 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 212 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 213 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 214 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 215 { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B }, 216 { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B }, 217 { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B }, 218 219 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 220 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 221 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 222 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 223 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 224 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_S | Op_A | Op_Rc }, 225 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 226 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 227 { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B }, 228 { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B }, 229 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 230 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 231 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 232 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 233 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 234 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 235 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 236 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 237 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 238 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 239 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 240 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 241 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 242 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 243 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 244 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 245 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 246 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 247 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 248 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 249 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 250 { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B }, 251 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B }, 252 { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B }, 253 { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */ 254 { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B }, 255 { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B }, 256 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 257 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 258 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 259 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B }, 260 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B }, 261 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 262 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 263 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 264 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 265 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 266 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 267 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B }, 268 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 269 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 270 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 271 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 272 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 273 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 274 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 275 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 276 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 277 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 278 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 279 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 280 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 281 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 282 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 283 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 284 { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B }, 285 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 286 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc }, 287 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 288 { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B }, 289 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 290 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 291 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 292 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 293 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 294 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 295 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 296 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 297 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 298 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 299 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 300 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 301 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 302 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 303 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 304 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 305 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 306 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 307 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 308 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 309 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 310 { "sync", 0xfc6007fe, 0x7c0004ac, 0 }, 311 { "lwsync", 0xfc6007fe, 0x7c2004ac, 0 }, 312 { "ptesync", 0xfc6007fe, 0x7c4004ac, 0 }, 313 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 314 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 315 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 316 { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B }, 317 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B }, 318 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B }, 319 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B }, 320 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB }, 321 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B }, 322 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B }, 323 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 324 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 325 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 326 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc }, 327 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 328 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 329 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 330 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B }, 331 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc }, 332 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 333 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 334 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 335 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 336 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B }, 337 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 338 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 339 { "", 0x0, 0x0, 0 } 340 }; 341 342 /* 3a * 4 = e8 */ 343 const struct opcode opcodes_3a[] = { 344 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 345 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 346 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 347 { "", 0x0, 0x0, 0 } 348 }; 349 /* 3b * 4 = ec */ 350 const struct opcode opcodes_3b[] = { 351 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 352 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 353 354 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 355 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 356 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 357 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 358 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 359 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 360 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 361 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 362 { "", 0x0, 0x0, 0 } 363 }; 364 /* 3e * 4 = f8 */ 365 const struct opcode opcodes_3e[] = { 366 { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds }, 367 { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds }, 368 { "", 0x0, 0x0, 0 } 369 }; 370 371 /* 3f * 4 = fc */ 372 const struct opcode opcodes_3f[] = { 373 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 374 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 375 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 376 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 377 378 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 379 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 380 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 381 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 382 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 383 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 384 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 385 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 386 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 387 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 388 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 389 390 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 391 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 392 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 393 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 394 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 395 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 396 { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */ 397 398 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 399 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 400 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 401 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 402 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 403 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 404 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 405 { "", 0x0, 0x0, 0 } 406 }; 407 408 struct specialreg { 409 int reg; 410 const char *name; 411 }; 412 413 const struct specialreg sprregs[] = { 414 { 0x000, "mq" }, 415 { 0x001, "xer" }, 416 { 0x008, "lr" }, 417 { 0x009, "ctr" }, 418 { 0x012, "dsisr" }, 419 { 0x013, "dar" }, 420 { 0x016, "dec" }, 421 { 0x019, "sdr1" }, 422 { 0x01a, "srr0" }, 423 { 0x01b, "srr1" }, 424 { 0x100, "vrsave" }, 425 { 0x110, "sprg0" }, 426 { 0x111, "sprg1" }, 427 { 0x112, "sprg2" }, 428 { 0x113, "sprg3" }, 429 { 0x114, "sprg4" }, 430 { 0x115, "sprg5" }, 431 { 0x116, "sprg6" }, 432 { 0x117, "sprg7" }, 433 { 0x118, "asr" }, 434 { 0x11a, "aer" }, 435 { 0x11c, "tbl" }, 436 { 0x11d, "tbu" }, 437 { 0x11f, "pvr" }, 438 { 0x210, "ibat0u" }, 439 { 0x211, "ibat0l" }, 440 { 0x212, "ibat1u" }, 441 { 0x213, "ibat1l" }, 442 { 0x214, "ibat2u" }, 443 { 0x215, "ibat2l" }, 444 { 0x216, "ibat3u" }, 445 { 0x217, "ibat3l" }, 446 { 0x218, "dbat0u" }, 447 { 0x219, "dbat0l" }, 448 { 0x21a, "dbat1u" }, 449 { 0x21b, "dbat1l" }, 450 { 0x21c, "dbat2u" }, 451 { 0x21d, "dbat2l" }, 452 { 0x21e, "dbat3u" }, 453 { 0x21f, "dbat3l" }, 454 { 0x230, "ibat4u" }, 455 { 0x231, "ibat4l" }, 456 { 0x232, "ibat5u" }, 457 { 0x233, "ibat5l" }, 458 { 0x234, "ibat6u" }, 459 { 0x235, "ibat6l" }, 460 { 0x236, "ibat7u" }, 461 { 0x237, "ibat7l" }, 462 { 0x238, "dbat4u" }, 463 { 0x239, "dbat4l" }, 464 { 0x23a, "dbat5u" }, 465 { 0x23b, "dbat5l" }, 466 { 0x23c, "dbat6u" }, 467 { 0x23d, "dbat6l" }, 468 { 0x23e, "dbat7u" }, 469 { 0x23f, "dbat7l" }, 470 { 0x3b0, "zpr" }, 471 { 0x3b1, "pid" }, 472 { 0x3b3, "ccr0" }, 473 { 0x3b4, "iac3" }, 474 { 0x3b5, "iac4" }, 475 { 0x3b6, "dvc1" }, 476 { 0x3b7, "dvc2" }, 477 { 0x3b9, "sgr" }, 478 { 0x3ba, "dcwr" }, 479 { 0x3bb, "sler" }, 480 { 0x3bc, "su0r" }, 481 { 0x3bd, "dbcr1" }, 482 { 0x3d3, "icdbdr" }, 483 { 0x3d4, "esr" }, 484 { 0x3d5, "dear" }, 485 { 0x3d6, "evpr" }, 486 { 0x3d8, "tsr" }, 487 { 0x3da, "tcr" }, 488 { 0x3db, "pit" }, 489 { 0x3de, "srr2" }, 490 { 0x3df, "srr3" }, 491 { 0x3f0, "hid0" }, 492 { 0x3f1, "hid1" }, 493 { 0x3f2, "iabr" }, 494 { 0x3f3, "hid2" }, 495 { 0x3f5, "dabr" }, 496 { 0x3f6, "msscr0" }, 497 { 0x3f7, "msscr1" }, 498 { 0x3f9, "l2cr" }, 499 { 0x3fa, "dccr" }, 500 { 0x3fb, "iccr" }, 501 { 0x3ff, "pir" }, 502 { 0, NULL } 503 }; 504 505 const struct specialreg dcrregs[] = { 506 { 0x010, "sdram0_cfgaddr" }, 507 { 0x011, "sdram0_cfgdata" }, 508 { 0x012, "ebc0_cfgaddr" }, 509 { 0x013, "ebc0_cfgdata" }, 510 { 0x014, "dcp0_cfgaddr" }, 511 { 0x015, "dcp0_cfgdata" }, 512 { 0x018, "ocm0_isarc" }, 513 { 0x019, "ocm0_iscntl" }, 514 { 0x01a, "ocm0_dsarc" }, 515 { 0x01b, "ocm0_dscntl" }, 516 { 0x084, "plb0_besr" }, 517 { 0x086, "plb0_bear" }, 518 { 0x087, "plb0_acr" }, 519 { 0x0a0, "pob0_besr0" }, 520 { 0x0a2, "pob0_bear" }, 521 { 0x0a4, "pob0_besr1" }, 522 { 0x0b0, "cpc0_pllmr" }, 523 { 0x0b1, "cpc0_cr0" }, 524 { 0x0b2, "cpc0_cr1" }, 525 { 0x0b4, "cpc0_psr" }, 526 { 0x0b5, "cpc0_jtagid" }, 527 { 0x0b8, "cpc0_sr" }, 528 { 0x0b9, "cpc0_er" }, 529 { 0x0ba, "cpc0_fr" }, 530 { 0x0c0, "uic0_sr" }, 531 { 0x0c2, "uic0_er" }, 532 { 0x0c3, "uic0_cr" }, 533 { 0x0c4, "uic0_pr" }, 534 { 0x0c5, "uic0_tr" }, 535 { 0x0c6, "uic0_msr" }, 536 { 0x0c7, "uic0_vr" }, 537 { 0x0c8, "uic0_vcr" }, 538 { 0x100, "dma0_cr0" }, 539 { 0x101, "dma0_ct0" }, 540 { 0x102, "dma0_da0" }, 541 { 0x103, "dma0_sa0" }, 542 { 0x104, "dma0_sg0" }, 543 { 0x108, "dma0_cr1" }, 544 { 0x109, "dma0_ct1" }, 545 { 0x10a, "dma0_da1" }, 546 { 0x10b, "dma0_sa1" }, 547 { 0x10c, "dma0_sg1" }, 548 { 0x110, "dma0_cr2" }, 549 { 0x111, "dma0_ct2" }, 550 { 0x112, "dma0_da2" }, 551 { 0x113, "dma0_sa2" }, 552 { 0x114, "dma0_sg2" }, 553 { 0x118, "dma0_cr3" }, 554 { 0x119, "dma0_ct3" }, 555 { 0x11a, "dma0_da3" }, 556 { 0x11b, "dma0_sa3" }, 557 { 0x11c, "dma0_sg3" }, 558 { 0x120, "dma0_sr" }, 559 { 0x123, "dma0_sgc" }, 560 { 0x125, "dma0_slp" }, 561 { 0x126, "dma0_pol" }, 562 { 0x180, "mal0_cfg" }, 563 { 0x181, "mal0_esr" }, 564 { 0x182, "mal0_ier" }, 565 { 0x184, "mal0_txcasr" }, 566 { 0x185, "mal0_txcarr" }, 567 { 0x186, "mal0_txeobisr" }, 568 { 0x187, "mal0_txdeir" }, 569 { 0x190, "mal0_rxcasr" }, 570 { 0x191, "mal0_rxcarr" }, 571 { 0x192, "mal0_rxeobisr" }, 572 { 0x193, "mal0_rxdeir" }, 573 { 0x1a0, "mal0_txctp0r" }, 574 { 0x1a1, "mal0_txctp1r" }, 575 { 0x1a2, "mal0_txctp2r" }, 576 { 0x1a3, "mal0_txctp3r" }, 577 { 0x1c0, "mal0_rxctp0r" }, 578 { 0x1e0, "mal0_rcbs0" }, 579 { 0, NULL } 580 }; 581 582 static const char *condstr[8] = { 583 "ge", "le", "ne", "ns", "lt", "gt", "eq", "so" 584 }; 585 586 void 587 op_ill(instr_t instr, vm_offset_t loc) 588 { 589 db_printf("illegal instruction %x\n", instr); 590 } 591 592 u_int32_t 593 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 594 { 595 u_int32_t mask = (1 << width) - 1; 596 return ((value >> base) & mask); 597 } 598 599 const struct opcode * search_op(const struct opcode *); 600 601 void 602 disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 603 char *disasm_str, size_t slen) 604 { 605 char * pstr; 606 enum function_mask func; 607 int len; 608 609 #define ADD_LEN(s) do { \ 610 len = (s); \ 611 slen -= len; \ 612 pstr += len; \ 613 } while(0) 614 #define APP_PSTR(fmt, arg) ADD_LEN(snprintf(pstr, slen, (fmt), (arg))) 615 #define APP_PSTRS(fmt) ADD_LEN(snprintf(pstr, slen, "%s", (fmt))) 616 617 pstr = disasm_str; 618 619 func = popcode->func; 620 if (func & Op_BC) { 621 u_int BO, BI; 622 BO = extract_field(instr, 31 - 10, 5); 623 BI = extract_field(instr, 31 - 15, 5); 624 func &= ~Op_BC; 625 if (BO & 4) { 626 /* standard, no decrement */ 627 if (BO & 16) { 628 if (popcode->code == 0x40000000) { 629 APP_PSTRS("c"); 630 func |= Op_BO | Op_BI; 631 } 632 } 633 else { 634 APP_PSTRS(condstr[((BO & 8) >> 1) + (BI & 3)]); 635 if (BI >= 4) 636 func |= Op_crfS; 637 } 638 } 639 else { 640 /* decrement and branch */ 641 if (BO & 2) 642 APP_PSTRS("dz"); 643 else 644 APP_PSTRS("dnz"); 645 if ((BO & 24) == 0) 646 APP_PSTRS("f"); 647 else if ((BO & 24) == 8) 648 APP_PSTRS("t"); 649 else 650 func |= Op_BI; 651 } 652 if (popcode->code == 0x4c000020) 653 APP_PSTRS("lr"); 654 else if (popcode->code == 0x4c000420) 655 APP_PSTRS("ctr"); 656 if ((BO & 20) != 20 && (func & Op_BO) == 0) 657 func |= Op_BP; /* branch prediction hint */ 658 } 659 if (func & Op_OE) { 660 u_int OE; 661 OE = extract_field(instr, 31 - 21, 1); 662 if (OE) { 663 APP_PSTRS("o"); 664 } 665 func &= ~Op_OE; 666 } 667 switch (func & Op_LKM) { 668 case Op_Rc: 669 if (instr & 0x1) 670 APP_PSTRS("."); 671 break; 672 case Op_AA: 673 if (instr & 0x1) 674 APP_PSTRS("l"); 675 if (instr & 0x2) { 676 APP_PSTRS("a"); 677 loc = 0; /* Absolute address */ 678 } 679 break; 680 case Op_LK: 681 if (instr & 0x1) 682 APP_PSTRS("l"); 683 break; 684 default: 685 func &= ~Op_LKM; 686 } 687 if (func & Op_BP) { 688 int y; 689 y = (instr & 0x200000) != 0; 690 if (popcode->code == 0x40000000) { 691 int BD; 692 BD = extract_field(instr, 31 - 29, 14); 693 BD = BD << 18; 694 BD = BD >> 16; 695 BD += loc; 696 if ((vm_offset_t)BD < loc) 697 y ^= 1; 698 } 699 APP_PSTR("%c", y ? '+' : '-'); 700 func &= ~Op_BP; 701 } 702 APP_PSTRS("\t"); 703 704 /* XXX: special cases here, out of flags in a 32bit word. */ 705 if (strcmp(popcode->name, "wrteei") == 0) { 706 int E; 707 E = extract_field(instr, 31 - 16, 5); 708 APP_PSTR("%d", E); 709 return; 710 } 711 else if (strcmp(popcode->name, "mtfsfi") == 0) { 712 u_int UI; 713 UI = extract_field(instr, 31 - 8, 3); 714 APP_PSTR("crf%u, ", UI); 715 UI = extract_field(instr, 31 - 19, 4); 716 APP_PSTR("0x%x", UI); 717 } 718 /* XXX: end of special cases here. */ 719 720 if ((func & Op_FM) == Op_FM) { 721 u_int FM; 722 FM = extract_field(instr, 31 - 14, 8); 723 APP_PSTR("0x%x, ", FM); 724 func &= ~Op_FM; 725 } 726 if (func & Op_D) { /* Op_ST is the same */ 727 u_int D; 728 D = extract_field(instr, 31 - 10, 5); 729 APP_PSTR("r%d, ", D); 730 func &= ~Op_D; 731 } 732 if (func & Op_crbD) { 733 u_int crbD; 734 crbD = extract_field(instr, 31 - 10, 5); 735 APP_PSTR("crb%d, ", crbD); 736 func &= ~Op_crbD; 737 } 738 if (func & Op_crfD) { 739 u_int crfD; 740 crfD = extract_field(instr, 31 - 8, 3); 741 APP_PSTR("crf%d, ", crfD); 742 func &= ~Op_crfD; 743 } 744 if (func & Op_TO) { 745 u_int TO; 746 TO = extract_field(instr, 31 - 10, 1); 747 APP_PSTR("%d, ", TO); 748 func &= ~Op_TO; 749 } 750 if (func & Op_crfS) { 751 u_int crfS; 752 crfS = extract_field(instr, 31 - 13, 3); 753 APP_PSTR("crf%d, ", crfS); 754 func &= ~Op_crfS; 755 } 756 if (func & Op_CRM) { 757 u_int CRM; 758 CRM = extract_field(instr, 31 - 19, 8); 759 APP_PSTR("0x%x, ", CRM); 760 func &= ~Op_CRM; 761 } 762 if (func & Op_BO) { 763 u_int BO; 764 BO = extract_field(instr, 31 - 10, 5); 765 APP_PSTR("%d, ", BO); 766 func &= ~Op_BO; 767 } 768 if (func & Op_BI) { 769 u_int BI; 770 BI = extract_field(instr, 31 - 15, 5); 771 APP_PSTR("%d, ", BI); 772 func &= ~Op_BI; 773 } 774 if (func & Op_dA) { /* register A indirect with displacement */ 775 u_int A; 776 A = extract_field(instr, 31 - 31, 16); 777 if (A & 0x8000) { 778 APP_PSTRS("-"); 779 A = 0x10000-A; 780 } 781 APP_PSTR("0x%x", A); 782 A = extract_field(instr, 31 - 15, 5); 783 APP_PSTR("(r%d)", A); 784 func &= ~Op_dA; 785 } 786 if (func & Op_spr) { 787 u_int spr; 788 u_int sprl; 789 u_int sprh; 790 const struct specialreg *regs; 791 int i; 792 sprl = extract_field(instr, 31 - 15, 5); 793 sprh = extract_field(instr, 31 - 20, 5); 794 spr = sprh << 5 | sprl; 795 796 /* ugly hack - out of bitfields in the function mask */ 797 if (popcode->name[2] == 'd') /* m.Dcr */ 798 regs = dcrregs; 799 else 800 regs = sprregs; 801 for (i = 0; regs[i].name != NULL; i++) 802 if (spr == regs[i].reg) 803 break; 804 if (regs[i].name == NULL) 805 APP_PSTR("[unknown special reg (%d)]", spr); 806 else 807 APP_PSTR("%s", regs[i].name); 808 809 if (popcode->name[1] == 't') /* spr is destination */ 810 APP_PSTRS(", "); 811 func &= ~Op_spr; 812 } 813 if (func & Op_SR) { 814 u_int SR; 815 SR = extract_field(instr, 31 - 15, 3); 816 APP_PSTR("sr%d", SR); 817 if (popcode->name[1] == 't') /* SR is destination */ 818 APP_PSTRS(", "); 819 func &= ~Op_SR; 820 } 821 if (func & Op_A) { 822 u_int A; 823 A = extract_field(instr, 31 - 15, 5); 824 APP_PSTR("r%d, ", A); 825 func &= ~Op_A; 826 } 827 if (func & Op_S) { 828 u_int D; 829 D = extract_field(instr, 31 - 10, 5); 830 APP_PSTR("r%d, ", D); 831 func &= ~Op_S; 832 } 833 if (func & Op_C) { 834 u_int C; 835 C = extract_field(instr, 31 - 25, 5); 836 APP_PSTR("r%d, ", C); 837 func &= ~Op_C; 838 } 839 if (func & Op_B) { 840 u_int B; 841 B = extract_field(instr, 31 - 20, 5); 842 APP_PSTR("r%d", B); 843 func &= ~Op_B; 844 } 845 if (func & Op_crbA) { 846 u_int crbA; 847 crbA = extract_field(instr, 31 - 15, 5); 848 APP_PSTR("%d, ", crbA); 849 func &= ~Op_crbA; 850 } 851 if (func & Op_crbB) { 852 u_int crbB; 853 crbB = extract_field(instr, 31 - 20, 5); 854 APP_PSTR("%d, ", crbB); 855 func &= ~Op_crbB; 856 } 857 if (func & Op_LI) { 858 int LI; 859 LI = extract_field(instr, 31 - 29, 24); 860 LI = LI << 8; 861 LI = LI >> 6; 862 LI += loc; 863 APP_PSTR("0x%x", LI); 864 func &= ~Op_LI; 865 } 866 switch (func & Op_SIMM) { 867 u_int IMM; 868 case Op_SIMM: /* same as Op_d */ 869 IMM = extract_field(instr, 31 - 31, 16); 870 if (IMM & 0x8000) { 871 APP_PSTRS("-"); 872 IMM = 0x10000-IMM; 873 } 874 func &= ~Op_SIMM; 875 goto common; 876 case Op_UIMM: 877 IMM = extract_field(instr, 31 - 31, 16); 878 func &= ~Op_UIMM; 879 goto common; 880 common: 881 APP_PSTR("0x%x", IMM); 882 break; 883 default: 884 ; 885 } 886 if (func & Op_BD) { 887 int BD; 888 BD = extract_field(instr, 31 - 29, 14); 889 BD = BD << 18; 890 BD = BD >> 16; 891 BD += loc; 892 /* Need to sign extend and shift up 2, then add addr */ 893 APP_PSTR("0x%x", BD); 894 func &= ~Op_BD; 895 } 896 if (func & Op_ds) { 897 u_int ds; 898 ds = extract_field(instr, 31 - 29, 14) << 2; 899 APP_PSTR("0x%x", ds); 900 func &= ~Op_ds; 901 } 902 if (func & Op_me) { 903 u_int me, mel, meh; 904 mel = extract_field(instr, 31 - 25, 4); 905 meh = extract_field(instr, 31 - 26, 1); 906 me = meh << 4 | mel; 907 APP_PSTR(", 0x%x", me); 908 func &= ~Op_me; 909 } 910 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 911 u_int SH; 912 SH = extract_field(instr, 31 - 20, 5); 913 APP_PSTR("%d", SH); 914 } 915 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 916 u_int MB; 917 u_int ME; 918 MB = extract_field(instr, 31 - 25, 5); 919 APP_PSTR(", %d", MB); 920 ME = extract_field(instr, 31 - 30, 5); 921 APP_PSTR(", %d", ME); 922 } 923 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 924 u_int sh, shl, shh; 925 shl = extract_field(instr, 31 - 19, 4); 926 shh = extract_field(instr, 31 - 20, 1); 927 sh = shh << 4 | shl; 928 APP_PSTR(", %d", sh); 929 } 930 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 931 u_int mb, mbl, mbh; 932 mbl = extract_field(instr, 31 - 25, 4); 933 mbh = extract_field(instr, 31 - 26, 1); 934 mb = mbh << 4 | mbl; 935 APP_PSTR(", %d", mb); 936 } 937 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 938 u_int me, mel, meh; 939 mel = extract_field(instr, 31 - 25, 4); 940 meh = extract_field(instr, 31 - 26, 1); 941 me = meh << 4 | mel; 942 APP_PSTR(", %d", me); 943 } 944 if (func & Op_tbr) { 945 u_int tbr; 946 u_int tbrl; 947 u_int tbrh; 948 const char *reg; 949 tbrl = extract_field(instr, 31 - 15, 5); 950 tbrh = extract_field(instr, 31 - 20, 5); 951 tbr = tbrh << 5 | tbrl; 952 953 switch (tbr) { 954 case 268: 955 reg = "tbl"; 956 break; 957 case 269: 958 reg = "tbu"; 959 break; 960 default: 961 reg = NULL; 962 } 963 if (reg == NULL) 964 APP_PSTR(", [unknown tbr %d ]", tbr); 965 else 966 APP_PSTR(", %s", reg); 967 func &= ~Op_tbr; 968 } 969 if (func & Op_NB) { 970 u_int NB; 971 NB = extract_field(instr, 31 - 20, 5); 972 if (NB == 0) 973 NB = 32; 974 APP_PSTR(", %d", NB); 975 func &= ~Op_SR; 976 } 977 #undef ADD_LEN 978 #undef APP_PSTR 979 #undef APP_PSTRS 980 } 981 982 void 983 op_base(instr_t instr, vm_offset_t loc) 984 { 985 dis_ppc(opcodes, instr, loc); 986 } 987 988 void 989 op_cl_x13(instr_t instr, vm_offset_t loc) 990 { 991 dis_ppc(opcodes_13, instr, loc); 992 } 993 994 void 995 op_cl_x1e(instr_t instr, vm_offset_t loc) 996 { 997 dis_ppc(opcodes_1e, instr, loc); 998 } 999 1000 void 1001 op_cl_x1f(instr_t instr, vm_offset_t loc) 1002 { 1003 dis_ppc(opcodes_1f, instr, loc); 1004 } 1005 1006 void 1007 op_cl_x3a(instr_t instr, vm_offset_t loc) 1008 { 1009 dis_ppc(opcodes_3a, instr, loc); 1010 } 1011 1012 void 1013 op_cl_x3b(instr_t instr, vm_offset_t loc) 1014 { 1015 dis_ppc(opcodes_3b, instr, loc); 1016 } 1017 1018 void 1019 op_cl_x3e(instr_t instr, vm_offset_t loc) 1020 { 1021 dis_ppc(opcodes_3e, instr, loc); 1022 } 1023 1024 void 1025 op_cl_x3f(instr_t instr, vm_offset_t loc) 1026 { 1027 dis_ppc(opcodes_3f, instr, loc); 1028 } 1029 1030 void 1031 dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) 1032 { 1033 const struct opcode *op; 1034 int found = 0; 1035 int i; 1036 char disasm_str[80]; 1037 1038 for (i = 0, op = &opcodeset[0]; 1039 found == 0 && op->mask != 0; 1040 i++, op = &opcodeset[i]) { 1041 if ((instr & op->mask) == op->code) { 1042 found = 1; 1043 disasm_fields(op, instr, loc, disasm_str, 1044 sizeof disasm_str); 1045 db_printf("%s%s\n", op->name, disasm_str); 1046 return; 1047 } 1048 } 1049 op_ill(instr, loc); 1050 } 1051 1052 db_addr_t 1053 db_disasm(db_addr_t loc, bool extended) 1054 { 1055 int class; 1056 instr_t opcode; 1057 opcode = *(instr_t *)(loc); 1058 if (extended) 1059 db_printf("|%08x| ", opcode); 1060 class = opcode >> 26; 1061 (opcodes_base[class])(opcode, loc); 1062 1063 return (loc + 4); 1064 } 1065 1066 vm_offset_t opc_disasm(vm_offset_t loc, int); 1067 1068 vm_offset_t 1069 opc_disasm(vm_offset_t loc, int xin) 1070 { 1071 int class; 1072 instr_t opcode; 1073 opcode = xin; 1074 class = opcode >> 26; 1075 (opcodes_base[class])(opcode, loc); 1076 1077 return (loc + 4); 1078 } 1079