1 /* $NetBSD: db_disasm.c,v 1.28 2013/07/04 23:00:23 joerg Exp $ */ 2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 3 4 #include <sys/cdefs.h> 5 __FBSDID("$FreeBSD$"); 6 7 #include <sys/param.h> 8 #include <sys/proc.h> 9 #include <sys/systm.h> 10 11 #include <machine/db_machdep.h> 12 13 #include <ddb/ddb.h> 14 #include <ddb/db_access.h> 15 #include <ddb/db_sym.h> 16 #include <ddb/db_variables.h> 17 #include <ddb/db_output.h> 18 19 enum function_mask { 20 Op_A = 0x00000001, 21 Op_B = 0x00000002, 22 Op_BI = 0x00000004, 23 Op_BO = 0x00000008, 24 Op_BC = Op_BI | Op_BO, 25 Op_CRM = 0x00000010, 26 Op_D = 0x00000020, 27 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ 28 Op_S = 0x00000040, /* S-field is swapped with A-field */ 29 Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */ 30 Op_dA = 0x00000080, 31 Op_LK = 0x00000100, 32 Op_Rc = 0x00000200, 33 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 34 Op_LKM = Op_AA, 35 Op_RcM = Op_AA, 36 Op_OE = 0x00000400, 37 Op_SR = 0x00000800, 38 Op_TO = 0x00001000, 39 Op_sign = 0x00002000, 40 Op_const = 0x00004000, 41 Op_SIMM = Op_const | Op_sign, 42 Op_UIMM = Op_const, 43 Op_crbA = 0x00008000, 44 Op_crbB = 0x00010000, 45 Op_WS = Op_crbB, /* kludge, same field as crbB */ 46 Op_rSH = Op_crbB, /* kludge, same field as crbB */ 47 Op_crbD = 0x00020000, 48 Op_crfD = 0x00040000, 49 Op_crfS = 0x00080000, 50 Op_ds = 0x00100000, 51 Op_me = 0x00200000, 52 Op_spr = 0x00400000, 53 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 54 Op_tbr = 0x00800000, 55 56 Op_BP = 0x01000000, 57 Op_BD = 0x02000000, 58 Op_LI = 0x04000000, 59 Op_C = 0x08000000, 60 61 Op_NB = 0x10000000, 62 63 Op_sh_mb_sh = 0x20000000, 64 Op_sh = 0x40000000, 65 Op_SH = Op_sh | Op_sh_mb_sh, 66 Op_mb = 0x80000000, 67 Op_MB = Op_mb | Op_sh_mb_sh, 68 Op_ME = Op_MB, 69 70 }; 71 72 struct opcode { 73 const char *name; 74 u_int32_t mask; 75 u_int32_t code; 76 enum function_mask func; 77 }; 78 79 typedef u_int32_t instr_t; 80 typedef void (op_class_func) (instr_t, vm_offset_t); 81 82 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 83 void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 84 char *disasm_str, size_t slen); 85 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); 86 87 op_class_func op_ill, op_base; 88 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 89 op_class_func op_cl_x3a, op_cl_x3b; 90 op_class_func op_cl_x3e, op_cl_x3f; 91 92 op_class_func *opcodes_base[] = { 93 /*x00*/ op_ill, op_ill, op_base, op_ill, 94 /*x04*/ op_ill, op_ill, op_ill, op_base, 95 /*x08*/ op_base, op_base, op_base, op_base, 96 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 97 /*x10*/ op_base, op_base, op_base, op_cl_x13, 98 /*x14*/ op_base, op_base, op_ill, op_base, 99 /*x18*/ op_base, op_base, op_base, op_base, 100 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 101 /*x20*/ op_base, op_base, op_base, op_base, 102 /*x24*/ op_base, op_base, op_base, op_base, 103 /*x28*/ op_base, op_base, op_base, op_base, 104 /*x2C*/ op_base, op_base, op_base, op_base, 105 /*x30*/ op_base, op_base, op_base, op_base, 106 /*x34*/ op_base, op_base, op_base, op_base, 107 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 108 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 109 }; 110 111 /* This table could be modified to make significant the "reserved" fields 112 * of the opcodes, But I didn't feel like it when typing in the table, 113 * I would recommend that this table be looked over for errors, 114 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 115 * PowerPC Microprocessor Family: The Programming Environments 116 */ 117 118 const struct opcode opcodes[] = { 119 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 120 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 121 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 122 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 123 { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM }, 124 { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM }, 125 { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM }, 126 { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM }, 127 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 128 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 129 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 130 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 131 { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */ 132 { "sc", 0xffffffff, 0x44000002, 0 }, 133 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 134 135 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 136 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 137 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 138 139 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 140 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 141 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 142 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 143 144 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 145 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 146 147 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA }, 148 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA }, 149 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA }, 150 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA }, 151 { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA }, 152 { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA }, 153 { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA }, 154 { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA }, 155 156 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA }, 157 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA }, 158 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA }, 159 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA }, 160 { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA }, 161 { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA }, 162 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA }, 163 { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA }, 164 165 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA }, 166 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA }, 167 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA }, 168 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA }, 169 170 { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA }, 171 { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA }, 172 { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA }, 173 { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA }, 174 { "", 0x0, 0x0, 0 } 175 176 }; 177 /* 13 * 4 = 4c */ 178 const struct opcode opcodes_13[] = { 179 /* 0x13 << 2 */ 180 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 181 { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */ 182 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 183 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 184 { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB }, 185 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 186 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 187 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 188 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 189 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 190 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 191 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 192 { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */ 193 { "", 0x0, 0x0, 0 } 194 }; 195 196 /* 1e * 4 = 78 */ 197 const struct opcode opcodes_1e[] = { 198 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 199 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 200 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 201 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 202 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 203 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 204 { "", 0x0, 0x0, 0 } 205 }; 206 207 /* 1f * 4 = 7c */ 208 const struct opcode opcodes_1f[] = { 209 /* 1f << 2 */ 210 { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B }, 211 { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B }, 212 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 213 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 214 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 215 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 216 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 217 { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B }, 218 { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B }, 219 { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B }, 220 221 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 222 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 223 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 224 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 225 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 226 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_S | Op_A | Op_Rc }, 227 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 228 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 229 { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B }, 230 { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B }, 231 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 232 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 233 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 234 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 235 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 236 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 237 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 238 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 239 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 240 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 241 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 242 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 243 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 244 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 245 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 246 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 247 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 248 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 249 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 250 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 251 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 252 { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B }, 253 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B }, 254 { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B }, 255 { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */ 256 { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B }, 257 { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B }, 258 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 259 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 260 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 261 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B }, 262 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B }, 263 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 264 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 265 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 266 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 267 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 268 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 269 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B }, 270 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 271 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 272 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 273 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 274 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 275 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 276 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 277 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 278 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 279 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 280 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 281 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 282 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 283 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 284 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 285 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 286 { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B }, 287 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 288 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc }, 289 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 290 { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B }, 291 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 292 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 293 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 294 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 295 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 296 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 297 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 298 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 299 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 300 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 301 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 302 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 303 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 304 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 305 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 306 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 307 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 308 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 309 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 310 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 311 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 312 { "sync", 0xfc6007fe, 0x7c0004ac, 0 }, 313 { "lwsync", 0xfc6007fe, 0x7c2004ac, 0 }, 314 { "ptesync", 0xfc6007fe, 0x7c4004ac, 0 }, 315 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 316 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 317 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 318 { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B }, 319 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B }, 320 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B }, 321 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B }, 322 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB }, 323 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B }, 324 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B }, 325 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 326 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 327 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 328 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc }, 329 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 330 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 331 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 332 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B }, 333 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc }, 334 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 335 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 336 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 337 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 338 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B }, 339 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 340 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 341 { "", 0x0, 0x0, 0 } 342 }; 343 344 /* 3a * 4 = e8 */ 345 const struct opcode opcodes_3a[] = { 346 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 347 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 348 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 349 { "", 0x0, 0x0, 0 } 350 }; 351 /* 3b * 4 = ec */ 352 const struct opcode opcodes_3b[] = { 353 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 354 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 355 356 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 357 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 358 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 359 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 360 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 361 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 362 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 363 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 364 { "", 0x0, 0x0, 0 } 365 }; 366 /* 3e * 4 = f8 */ 367 const struct opcode opcodes_3e[] = { 368 { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds }, 369 { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds }, 370 { "", 0x0, 0x0, 0 } 371 }; 372 373 /* 3f * 4 = fc */ 374 const struct opcode opcodes_3f[] = { 375 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 376 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 377 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 378 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 379 380 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 381 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 382 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 383 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 384 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 385 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 386 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 387 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 388 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 389 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 390 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 391 392 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 393 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 394 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 395 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 396 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 397 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 398 { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */ 399 400 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 401 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 402 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 403 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 404 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 405 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 406 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 407 { "", 0x0, 0x0, 0 } 408 }; 409 410 struct specialreg { 411 int reg; 412 const char *name; 413 }; 414 415 const struct specialreg sprregs[] = { 416 { 0x000, "mq" }, 417 { 0x001, "xer" }, 418 { 0x008, "lr" }, 419 { 0x009, "ctr" }, 420 { 0x012, "dsisr" }, 421 { 0x013, "dar" }, 422 { 0x016, "dec" }, 423 { 0x019, "sdr1" }, 424 { 0x01a, "srr0" }, 425 { 0x01b, "srr1" }, 426 { 0x100, "vrsave" }, 427 { 0x110, "sprg0" }, 428 { 0x111, "sprg1" }, 429 { 0x112, "sprg2" }, 430 { 0x113, "sprg3" }, 431 { 0x114, "sprg4" }, 432 { 0x115, "sprg5" }, 433 { 0x116, "sprg6" }, 434 { 0x117, "sprg7" }, 435 { 0x118, "asr" }, 436 { 0x11a, "aer" }, 437 { 0x11c, "tbl" }, 438 { 0x11d, "tbu" }, 439 { 0x11f, "pvr" }, 440 { 0x210, "ibat0u" }, 441 { 0x211, "ibat0l" }, 442 { 0x212, "ibat1u" }, 443 { 0x213, "ibat1l" }, 444 { 0x214, "ibat2u" }, 445 { 0x215, "ibat2l" }, 446 { 0x216, "ibat3u" }, 447 { 0x217, "ibat3l" }, 448 { 0x218, "dbat0u" }, 449 { 0x219, "dbat0l" }, 450 { 0x21a, "dbat1u" }, 451 { 0x21b, "dbat1l" }, 452 { 0x21c, "dbat2u" }, 453 { 0x21d, "dbat2l" }, 454 { 0x21e, "dbat3u" }, 455 { 0x21f, "dbat3l" }, 456 { 0x230, "ibat4u" }, 457 { 0x231, "ibat4l" }, 458 { 0x232, "ibat5u" }, 459 { 0x233, "ibat5l" }, 460 { 0x234, "ibat6u" }, 461 { 0x235, "ibat6l" }, 462 { 0x236, "ibat7u" }, 463 { 0x237, "ibat7l" }, 464 { 0x238, "dbat4u" }, 465 { 0x239, "dbat4l" }, 466 { 0x23a, "dbat5u" }, 467 { 0x23b, "dbat5l" }, 468 { 0x23c, "dbat6u" }, 469 { 0x23d, "dbat6l" }, 470 { 0x23e, "dbat7u" }, 471 { 0x23f, "dbat7l" }, 472 { 0x3b0, "zpr" }, 473 { 0x3b1, "pid" }, 474 { 0x3b3, "ccr0" }, 475 { 0x3b4, "iac3" }, 476 { 0x3b5, "iac4" }, 477 { 0x3b6, "dvc1" }, 478 { 0x3b7, "dvc2" }, 479 { 0x3b9, "sgr" }, 480 { 0x3ba, "dcwr" }, 481 { 0x3bb, "sler" }, 482 { 0x3bc, "su0r" }, 483 { 0x3bd, "dbcr1" }, 484 { 0x3d3, "icdbdr" }, 485 { 0x3d4, "esr" }, 486 { 0x3d5, "dear" }, 487 { 0x3d6, "evpr" }, 488 { 0x3d8, "tsr" }, 489 { 0x3da, "tcr" }, 490 { 0x3db, "pit" }, 491 { 0x3de, "srr2" }, 492 { 0x3df, "srr3" }, 493 { 0x3f0, "hid0" }, 494 { 0x3f1, "hid1" }, 495 { 0x3f2, "iabr" }, 496 { 0x3f3, "hid2" }, 497 { 0x3f5, "dabr" }, 498 { 0x3f6, "msscr0" }, 499 { 0x3f7, "msscr1" }, 500 { 0x3f9, "l2cr" }, 501 { 0x3fa, "dccr" }, 502 { 0x3fb, "iccr" }, 503 { 0x3ff, "pir" }, 504 { 0, NULL } 505 }; 506 507 const struct specialreg dcrregs[] = { 508 { 0x010, "sdram0_cfgaddr" }, 509 { 0x011, "sdram0_cfgdata" }, 510 { 0x012, "ebc0_cfgaddr" }, 511 { 0x013, "ebc0_cfgdata" }, 512 { 0x014, "dcp0_cfgaddr" }, 513 { 0x015, "dcp0_cfgdata" }, 514 { 0x018, "ocm0_isarc" }, 515 { 0x019, "ocm0_iscntl" }, 516 { 0x01a, "ocm0_dsarc" }, 517 { 0x01b, "ocm0_dscntl" }, 518 { 0x084, "plb0_besr" }, 519 { 0x086, "plb0_bear" }, 520 { 0x087, "plb0_acr" }, 521 { 0x0a0, "pob0_besr0" }, 522 { 0x0a2, "pob0_bear" }, 523 { 0x0a4, "pob0_besr1" }, 524 { 0x0b0, "cpc0_pllmr" }, 525 { 0x0b1, "cpc0_cr0" }, 526 { 0x0b2, "cpc0_cr1" }, 527 { 0x0b4, "cpc0_psr" }, 528 { 0x0b5, "cpc0_jtagid" }, 529 { 0x0b8, "cpc0_sr" }, 530 { 0x0b9, "cpc0_er" }, 531 { 0x0ba, "cpc0_fr" }, 532 { 0x0c0, "uic0_sr" }, 533 { 0x0c2, "uic0_er" }, 534 { 0x0c3, "uic0_cr" }, 535 { 0x0c4, "uic0_pr" }, 536 { 0x0c5, "uic0_tr" }, 537 { 0x0c6, "uic0_msr" }, 538 { 0x0c7, "uic0_vr" }, 539 { 0x0c8, "uic0_vcr" }, 540 { 0x100, "dma0_cr0" }, 541 { 0x101, "dma0_ct0" }, 542 { 0x102, "dma0_da0" }, 543 { 0x103, "dma0_sa0" }, 544 { 0x104, "dma0_sg0" }, 545 { 0x108, "dma0_cr1" }, 546 { 0x109, "dma0_ct1" }, 547 { 0x10a, "dma0_da1" }, 548 { 0x10b, "dma0_sa1" }, 549 { 0x10c, "dma0_sg1" }, 550 { 0x110, "dma0_cr2" }, 551 { 0x111, "dma0_ct2" }, 552 { 0x112, "dma0_da2" }, 553 { 0x113, "dma0_sa2" }, 554 { 0x114, "dma0_sg2" }, 555 { 0x118, "dma0_cr3" }, 556 { 0x119, "dma0_ct3" }, 557 { 0x11a, "dma0_da3" }, 558 { 0x11b, "dma0_sa3" }, 559 { 0x11c, "dma0_sg3" }, 560 { 0x120, "dma0_sr" }, 561 { 0x123, "dma0_sgc" }, 562 { 0x125, "dma0_slp" }, 563 { 0x126, "dma0_pol" }, 564 { 0x180, "mal0_cfg" }, 565 { 0x181, "mal0_esr" }, 566 { 0x182, "mal0_ier" }, 567 { 0x184, "mal0_txcasr" }, 568 { 0x185, "mal0_txcarr" }, 569 { 0x186, "mal0_txeobisr" }, 570 { 0x187, "mal0_txdeir" }, 571 { 0x190, "mal0_rxcasr" }, 572 { 0x191, "mal0_rxcarr" }, 573 { 0x192, "mal0_rxeobisr" }, 574 { 0x193, "mal0_rxdeir" }, 575 { 0x1a0, "mal0_txctp0r" }, 576 { 0x1a1, "mal0_txctp1r" }, 577 { 0x1a2, "mal0_txctp2r" }, 578 { 0x1a3, "mal0_txctp3r" }, 579 { 0x1c0, "mal0_rxctp0r" }, 580 { 0x1e0, "mal0_rcbs0" }, 581 { 0, NULL } 582 }; 583 584 static const char *condstr[8] = { 585 "ge", "le", "ne", "ns", "lt", "gt", "eq", "so" 586 }; 587 588 void 589 op_ill(instr_t instr, vm_offset_t loc) 590 { 591 db_printf("illegal instruction %x\n", instr); 592 } 593 594 u_int32_t 595 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 596 { 597 u_int32_t mask = (1 << width) - 1; 598 return ((value >> base) & mask); 599 } 600 601 const struct opcode * search_op(const struct opcode *); 602 603 void 604 disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 605 char *disasm_str, size_t slen) 606 { 607 char * pstr; 608 enum function_mask func; 609 int len; 610 611 #define ADD_LEN(s) do { \ 612 len = (s); \ 613 slen -= len; \ 614 pstr += len; \ 615 } while(0) 616 #define APP_PSTR(fmt, arg) ADD_LEN(snprintf(pstr, slen, (fmt), (arg))) 617 #define APP_PSTRS(fmt) ADD_LEN(snprintf(pstr, slen, "%s", (fmt))) 618 619 pstr = disasm_str; 620 621 func = popcode->func; 622 if (func & Op_BC) { 623 u_int BO, BI; 624 BO = extract_field(instr, 31 - 10, 5); 625 BI = extract_field(instr, 31 - 15, 5); 626 func &= ~Op_BC; 627 if (BO & 4) { 628 /* standard, no decrement */ 629 if (BO & 16) { 630 if (popcode->code == 0x40000000) { 631 APP_PSTRS("c"); 632 func |= Op_BO | Op_BI; 633 } 634 } 635 else { 636 APP_PSTRS(condstr[((BO & 8) >> 1) + (BI & 3)]); 637 if (BI >= 4) 638 func |= Op_crfS; 639 } 640 } 641 else { 642 /* decrement and branch */ 643 if (BO & 2) 644 APP_PSTRS("dz"); 645 else 646 APP_PSTRS("dnz"); 647 if ((BO & 24) == 0) 648 APP_PSTRS("f"); 649 else if ((BO & 24) == 8) 650 APP_PSTRS("t"); 651 else 652 func |= Op_BI; 653 } 654 if (popcode->code == 0x4c000020) 655 APP_PSTRS("lr"); 656 else if (popcode->code == 0x4c000420) 657 APP_PSTRS("ctr"); 658 if ((BO & 20) != 20 && (func & Op_BO) == 0) 659 func |= Op_BP; /* branch prediction hint */ 660 } 661 if (func & Op_OE) { 662 u_int OE; 663 OE = extract_field(instr, 31 - 21, 1); 664 if (OE) { 665 APP_PSTRS("o"); 666 } 667 func &= ~Op_OE; 668 } 669 switch (func & Op_LKM) { 670 case Op_Rc: 671 if (instr & 0x1) 672 APP_PSTRS("."); 673 break; 674 case Op_AA: 675 if (instr & 0x1) 676 APP_PSTRS("l"); 677 if (instr & 0x2) { 678 APP_PSTRS("a"); 679 loc = 0; /* Absolute address */ 680 } 681 break; 682 case Op_LK: 683 if (instr & 0x1) 684 APP_PSTRS("l"); 685 break; 686 default: 687 func &= ~Op_LKM; 688 } 689 if (func & Op_BP) { 690 int y; 691 y = (instr & 0x200000) != 0; 692 if (popcode->code == 0x40000000) { 693 int BD; 694 BD = extract_field(instr, 31 - 29, 14); 695 BD = BD << 18; 696 BD = BD >> 16; 697 BD += loc; 698 if ((vm_offset_t)BD < loc) 699 y ^= 1; 700 } 701 APP_PSTR("%c", y ? '+' : '-'); 702 func &= ~Op_BP; 703 } 704 APP_PSTRS("\t"); 705 706 /* XXX: special cases here, out of flags in a 32bit word. */ 707 if (strcmp(popcode->name, "wrteei") == 0) { 708 int E; 709 E = extract_field(instr, 31 - 16, 5); 710 APP_PSTR("%d", E); 711 return; 712 } 713 else if (strcmp(popcode->name, "mtfsfi") == 0) { 714 u_int UI; 715 UI = extract_field(instr, 31 - 8, 3); 716 APP_PSTR("crf%u, ", UI); 717 UI = extract_field(instr, 31 - 19, 4); 718 APP_PSTR("0x%x", UI); 719 } 720 /* XXX: end of special cases here. */ 721 722 if ((func & Op_FM) == Op_FM) { 723 u_int FM; 724 FM = extract_field(instr, 31 - 14, 8); 725 APP_PSTR("0x%x, ", FM); 726 func &= ~Op_FM; 727 } 728 if (func & Op_D) { /* Op_ST is the same */ 729 u_int D; 730 D = extract_field(instr, 31 - 10, 5); 731 APP_PSTR("r%d, ", D); 732 func &= ~Op_D; 733 } 734 if (func & Op_crbD) { 735 u_int crbD; 736 crbD = extract_field(instr, 31 - 10, 5); 737 APP_PSTR("crb%d, ", crbD); 738 func &= ~Op_crbD; 739 } 740 if (func & Op_crfD) { 741 u_int crfD; 742 crfD = extract_field(instr, 31 - 8, 3); 743 APP_PSTR("crf%d, ", crfD); 744 func &= ~Op_crfD; 745 } 746 if (func & Op_TO) { 747 u_int TO; 748 TO = extract_field(instr, 31 - 10, 1); 749 APP_PSTR("%d, ", TO); 750 func &= ~Op_TO; 751 } 752 if (func & Op_crfS) { 753 u_int crfS; 754 crfS = extract_field(instr, 31 - 13, 3); 755 APP_PSTR("crf%d, ", crfS); 756 func &= ~Op_crfS; 757 } 758 if (func & Op_CRM) { 759 u_int CRM; 760 CRM = extract_field(instr, 31 - 19, 8); 761 APP_PSTR("0x%x, ", CRM); 762 func &= ~Op_CRM; 763 } 764 if (func & Op_BO) { 765 u_int BO; 766 BO = extract_field(instr, 31 - 10, 5); 767 APP_PSTR("%d, ", BO); 768 func &= ~Op_BO; 769 } 770 if (func & Op_BI) { 771 u_int BI; 772 BI = extract_field(instr, 31 - 15, 5); 773 APP_PSTR("%d, ", BI); 774 func &= ~Op_BI; 775 } 776 if (func & Op_dA) { /* register A indirect with displacement */ 777 u_int A; 778 A = extract_field(instr, 31 - 31, 16); 779 if (A & 0x8000) { 780 APP_PSTRS("-"); 781 A = 0x10000-A; 782 } 783 APP_PSTR("0x%x", A); 784 A = extract_field(instr, 31 - 15, 5); 785 APP_PSTR("(r%d)", A); 786 func &= ~Op_dA; 787 } 788 if (func & Op_spr) { 789 u_int spr; 790 u_int sprl; 791 u_int sprh; 792 const struct specialreg *regs; 793 int i; 794 sprl = extract_field(instr, 31 - 15, 5); 795 sprh = extract_field(instr, 31 - 20, 5); 796 spr = sprh << 5 | sprl; 797 798 /* ugly hack - out of bitfields in the function mask */ 799 if (popcode->name[2] == 'd') /* m.Dcr */ 800 regs = dcrregs; 801 else 802 regs = sprregs; 803 for (i = 0; regs[i].name != NULL; i++) 804 if (spr == regs[i].reg) 805 break; 806 if (regs[i].name == NULL) 807 APP_PSTR("[unknown special reg (%d)]", spr); 808 else 809 APP_PSTR("%s", regs[i].name); 810 811 if (popcode->name[1] == 't') /* spr is destination */ 812 APP_PSTRS(", "); 813 func &= ~Op_spr; 814 } 815 if (func & Op_SR) { 816 u_int SR; 817 SR = extract_field(instr, 31 - 15, 3); 818 APP_PSTR("sr%d", SR); 819 if (popcode->name[1] == 't') /* SR is destination */ 820 APP_PSTRS(", "); 821 func &= ~Op_SR; 822 } 823 if (func & Op_A) { 824 u_int A; 825 A = extract_field(instr, 31 - 15, 5); 826 APP_PSTR("r%d, ", A); 827 func &= ~Op_A; 828 } 829 if (func & Op_S) { 830 u_int D; 831 D = extract_field(instr, 31 - 10, 5); 832 APP_PSTR("r%d, ", D); 833 func &= ~Op_S; 834 } 835 if (func & Op_C) { 836 u_int C; 837 C = extract_field(instr, 31 - 25, 5); 838 APP_PSTR("r%d, ", C); 839 func &= ~Op_C; 840 } 841 if (func & Op_B) { 842 u_int B; 843 B = extract_field(instr, 31 - 20, 5); 844 APP_PSTR("r%d", B); 845 func &= ~Op_B; 846 } 847 if (func & Op_crbA) { 848 u_int crbA; 849 crbA = extract_field(instr, 31 - 15, 5); 850 APP_PSTR("%d, ", crbA); 851 func &= ~Op_crbA; 852 } 853 if (func & Op_crbB) { 854 u_int crbB; 855 crbB = extract_field(instr, 31 - 20, 5); 856 APP_PSTR("%d, ", crbB); 857 func &= ~Op_crbB; 858 } 859 if (func & Op_LI) { 860 int LI; 861 LI = extract_field(instr, 31 - 29, 24); 862 LI = LI << 8; 863 LI = LI >> 6; 864 LI += loc; 865 APP_PSTR("0x%x", LI); 866 func &= ~Op_LI; 867 } 868 switch (func & Op_SIMM) { 869 u_int IMM; 870 case Op_SIMM: /* same as Op_d */ 871 IMM = extract_field(instr, 31 - 31, 16); 872 if (IMM & 0x8000) { 873 APP_PSTRS("-"); 874 IMM = 0x10000-IMM; 875 } 876 func &= ~Op_SIMM; 877 goto common; 878 case Op_UIMM: 879 IMM = extract_field(instr, 31 - 31, 16); 880 func &= ~Op_UIMM; 881 goto common; 882 common: 883 APP_PSTR("0x%x", IMM); 884 break; 885 default: 886 ; 887 } 888 if (func & Op_BD) { 889 int BD; 890 BD = extract_field(instr, 31 - 29, 14); 891 BD = BD << 18; 892 BD = BD >> 16; 893 BD += loc; 894 /* Need to sign extend and shift up 2, then add addr */ 895 APP_PSTR("0x%x", BD); 896 func &= ~Op_BD; 897 } 898 if (func & Op_ds) { 899 u_int ds; 900 ds = extract_field(instr, 31 - 29, 14) << 2; 901 APP_PSTR("0x%x", ds); 902 func &= ~Op_ds; 903 } 904 if (func & Op_me) { 905 u_int me, mel, meh; 906 mel = extract_field(instr, 31 - 25, 4); 907 meh = extract_field(instr, 31 - 26, 1); 908 me = meh << 4 | mel; 909 APP_PSTR(", 0x%x", me); 910 func &= ~Op_me; 911 } 912 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 913 u_int SH; 914 SH = extract_field(instr, 31 - 20, 5); 915 APP_PSTR("%d", SH); 916 } 917 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 918 u_int MB; 919 u_int ME; 920 MB = extract_field(instr, 31 - 25, 5); 921 APP_PSTR(", %d", MB); 922 ME = extract_field(instr, 31 - 30, 5); 923 APP_PSTR(", %d", ME); 924 } 925 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 926 u_int sh, shl, shh; 927 shl = extract_field(instr, 31 - 19, 4); 928 shh = extract_field(instr, 31 - 20, 1); 929 sh = shh << 4 | shl; 930 APP_PSTR(", %d", sh); 931 } 932 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 933 u_int mb, mbl, mbh; 934 mbl = extract_field(instr, 31 - 25, 4); 935 mbh = extract_field(instr, 31 - 26, 1); 936 mb = mbh << 4 | mbl; 937 APP_PSTR(", %d", mb); 938 } 939 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 940 u_int me, mel, meh; 941 mel = extract_field(instr, 31 - 25, 4); 942 meh = extract_field(instr, 31 - 26, 1); 943 me = meh << 4 | mel; 944 APP_PSTR(", %d", me); 945 } 946 if (func & Op_tbr) { 947 u_int tbr; 948 u_int tbrl; 949 u_int tbrh; 950 const char *reg; 951 tbrl = extract_field(instr, 31 - 15, 5); 952 tbrh = extract_field(instr, 31 - 20, 5); 953 tbr = tbrh << 5 | tbrl; 954 955 switch (tbr) { 956 case 268: 957 reg = "tbl"; 958 break; 959 case 269: 960 reg = "tbu"; 961 break; 962 default: 963 reg = NULL; 964 } 965 if (reg == NULL) 966 APP_PSTR(", [unknown tbr %d ]", tbr); 967 else 968 APP_PSTR(", %s", reg); 969 func &= ~Op_tbr; 970 } 971 if (func & Op_NB) { 972 u_int NB; 973 NB = extract_field(instr, 31 - 20, 5); 974 if (NB == 0) 975 NB = 32; 976 APP_PSTR(", %d", NB); 977 func &= ~Op_SR; 978 } 979 #undef ADD_LEN 980 #undef APP_PSTR 981 #undef APP_PSTRS 982 } 983 984 void 985 op_base(instr_t instr, vm_offset_t loc) 986 { 987 dis_ppc(opcodes, instr, loc); 988 } 989 990 void 991 op_cl_x13(instr_t instr, vm_offset_t loc) 992 { 993 dis_ppc(opcodes_13, instr, loc); 994 } 995 996 void 997 op_cl_x1e(instr_t instr, vm_offset_t loc) 998 { 999 dis_ppc(opcodes_1e, instr, loc); 1000 } 1001 1002 void 1003 op_cl_x1f(instr_t instr, vm_offset_t loc) 1004 { 1005 dis_ppc(opcodes_1f, instr, loc); 1006 } 1007 1008 void 1009 op_cl_x3a(instr_t instr, vm_offset_t loc) 1010 { 1011 dis_ppc(opcodes_3a, instr, loc); 1012 } 1013 1014 void 1015 op_cl_x3b(instr_t instr, vm_offset_t loc) 1016 { 1017 dis_ppc(opcodes_3b, instr, loc); 1018 } 1019 1020 void 1021 op_cl_x3e(instr_t instr, vm_offset_t loc) 1022 { 1023 dis_ppc(opcodes_3e, instr, loc); 1024 } 1025 1026 void 1027 op_cl_x3f(instr_t instr, vm_offset_t loc) 1028 { 1029 dis_ppc(opcodes_3f, instr, loc); 1030 } 1031 1032 void 1033 dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) 1034 { 1035 const struct opcode *op; 1036 int found = 0; 1037 int i; 1038 char disasm_str[80]; 1039 1040 for (i = 0, op = &opcodeset[0]; 1041 found == 0 && op->mask != 0; 1042 i++, op = &opcodeset[i]) { 1043 if ((instr & op->mask) == op->code) { 1044 found = 1; 1045 disasm_fields(op, instr, loc, disasm_str, 1046 sizeof disasm_str); 1047 db_printf("%s%s\n", op->name, disasm_str); 1048 return; 1049 } 1050 } 1051 op_ill(instr, loc); 1052 } 1053 1054 db_addr_t 1055 db_disasm(db_addr_t loc, bool extended) 1056 { 1057 int class; 1058 instr_t opcode; 1059 opcode = *(instr_t *)(loc); 1060 if (extended) 1061 db_printf("|%08x| ", opcode); 1062 class = opcode >> 26; 1063 (opcodes_base[class])(opcode, loc); 1064 1065 return (loc + 4); 1066 } 1067 1068 vm_offset_t opc_disasm(vm_offset_t loc, int); 1069 1070 vm_offset_t 1071 opc_disasm(vm_offset_t loc, int xin) 1072 { 1073 int class; 1074 instr_t opcode; 1075 opcode = xin; 1076 class = opcode >> 26; 1077 (opcodes_base[class])(opcode, loc); 1078 1079 return (loc + 4); 1080 } 1081