1 /* $FreeBSD$ */ 2 /* $NetBSD: db_disasm.c,v 1.12 2002/01/05 22:07:26 jhawk Exp $ */ 3 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 4 5 #include <sys/param.h> 6 #include <sys/proc.h> 7 #include <sys/systm.h> 8 9 #include <machine/db_machdep.h> 10 #include <machine/trap.h> 11 12 #include <ddb/ddb.h> 13 #include <ddb/db_access.h> 14 #include <ddb/db_sym.h> 15 #include <ddb/db_variables.h> 16 #include <ddb/db_output.h> 17 18 enum function_mask { 19 Op_A = 0x00000001, 20 Op_B = 0x00000002, 21 Op_BI = 0x00000004, 22 Op_BO = 0x00000008, 23 Op_CRM = 0x00000010, 24 Op_D = 0x00000020, /* yes, Op_S and Op_D are the same */ 25 Op_S = 0x00000020, 26 Op_FM = 0x00000040, 27 Op_IMM = 0x00000080, 28 Op_LK = 0x00000100, 29 Op_Rc = 0x00000200, 30 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 31 Op_LKM = Op_AA, 32 Op_RcM = Op_AA, 33 Op_OE = 0x00000400, 34 Op_SR = 0x00000800, 35 Op_TO = 0x00001000, 36 Op_sign = 0x00002000, 37 Op_const = 0x00004000, 38 Op_SIMM = Op_const | Op_sign, 39 Op_UIMM = Op_const, 40 Op_d = Op_const | Op_sign, 41 Op_crbA = 0x00008000, 42 Op_crbB = 0x00010000, 43 Op_WS = Op_crbB, /* kludge, same field as crbB */ 44 Op_crbD = 0x00020000, 45 Op_crfD = 0x00040000, 46 Op_crfS = 0x00080000, 47 Op_ds = 0x00100000, 48 Op_me = 0x00200000, 49 Op_spr = 0x00400000, 50 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 51 Op_tbr = 0x00800000, 52 53 Op_L = 0x01000000, 54 Op_BD = 0x02000000, 55 Op_LI = 0x04000000, 56 Op_C = 0x08000000, 57 58 Op_NB = 0x10000000, 59 60 Op_sh_mb_sh = 0x20000000, 61 Op_sh = 0x40000000, 62 Op_SH = Op_sh | Op_sh_mb_sh, 63 Op_mb = 0x80000000, 64 Op_MB = Op_mb | Op_sh_mb_sh, 65 Op_ME = Op_MB, 66 67 }; 68 69 struct opcode { 70 char *name; 71 u_int32_t mask; 72 u_int32_t code; 73 enum function_mask func; 74 }; 75 76 typedef u_int32_t instr_t; 77 typedef void (op_class_func) (instr_t, vm_offset_t); 78 79 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 80 void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 81 char *disasm_str); 82 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); 83 84 op_class_func op_ill, op_base; 85 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 86 op_class_func op_cl_x3a, op_cl_x3b; 87 op_class_func op_cl_x3e, op_cl_x3f; 88 89 op_class_func *opcodes_base[] = { 90 /*x00*/ op_ill, op_ill, op_base, op_ill, 91 /*x04*/ op_ill, op_ill, op_ill, op_base, 92 /*x08*/ op_base, op_base, op_ill, op_base, 93 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 94 /*x10*/ op_base, op_base, op_base, op_cl_x13, 95 /*x14*/ op_base, op_base, op_ill, op_base, 96 /*x18*/ op_base, op_base, op_base, op_base, 97 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 98 /*x20*/ op_base, op_base, op_base, op_base, 99 /*x24*/ op_base, op_base, op_base, op_base, 100 /*x28*/ op_base, op_base, op_base, op_base, 101 /*x2C*/ op_base, op_base, op_base, op_base, 102 /*x30*/ op_base, op_base, op_base, op_base, 103 /*x34*/ op_base, op_base, op_base, op_base, 104 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 105 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 106 }; 107 108 109 /* This table could be modified to make significant the "reserved" fields 110 * of the opcodes, But I didn't feel like it when typing in the table, 111 * I would recommend that this table be looked over for errors, 112 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 113 * PowerPC Microprocessor Family: The Programming Environments 114 */ 115 116 const struct opcode opcodes[] = { 117 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 118 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 119 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 120 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 121 { "cmpli", 0xfc000000, 0x28000000, Op_crfD | Op_L | Op_A | Op_SIMM }, 122 { "cmpi", 0xfc000000, 0x2c000000, Op_crfD | Op_L | Op_A | Op_SIMM }, 123 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 124 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 125 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 126 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 127 { "bc", 0xfc000000, 0x40000000, Op_BO | Op_BI | Op_BD | Op_AA | Op_LK }, 128 { "sc", 0xffffffff, 0x44000002, Op_BO | Op_BI | Op_BD | Op_AA | Op_LK }, 129 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 130 131 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 132 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 133 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 134 135 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 136 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 137 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 138 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 139 140 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 141 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 142 143 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_A | Op_d }, 144 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_A | Op_d }, 145 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_A | Op_d }, 146 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_A | Op_d }, 147 { "stw", 0xfc000000, 0x90000000, Op_S | Op_A | Op_d }, 148 { "stwu", 0xfc000000, 0x94000000, Op_S | Op_A | Op_d }, 149 { "stb", 0xfc000000, 0x98000000, Op_S | Op_A | Op_d }, 150 { "stbu", 0xfc000000, 0x9c000000, Op_S | Op_A | Op_d }, 151 152 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_A | Op_d }, 153 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_A | Op_d }, 154 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_A | Op_d }, 155 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_A | Op_d }, 156 { "sth", 0xfc000000, 0xb0000000, Op_S | Op_A | Op_d }, 157 { "sthu", 0xfc000000, 0xb4000000, Op_S | Op_A | Op_d }, 158 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_A | Op_d }, 159 { "stmw", 0xfc000000, 0xbc000000, Op_S | Op_A | Op_d }, 160 161 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_A | Op_d }, 162 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_A | Op_d }, 163 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_A | Op_d }, 164 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_A | Op_d }, 165 166 { "stfs", 0xfc000000, 0xd0000000, Op_S | Op_A | Op_d }, 167 { "stfsu", 0xfc000000, 0xd4000000, Op_S | Op_A | Op_d }, 168 { "stfd", 0xfc000000, 0xd8000000, Op_S | Op_A | Op_d }, 169 { "stfdu", 0xfc000000, 0xdc000000, Op_S | Op_A | Op_d }, 170 { "", 0x0, 0x0, 0 } 171 172 }; 173 /* 13 * 4 = 4c */ 174 const struct opcode opcodes_13[] = { 175 /* 0x13 << 2 */ 176 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 177 { "bclr", 0xfc0007fe, 0x4c000020, Op_BO | Op_BI | Op_LK }, 178 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 179 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 180 { "crandc", 0xfc0007fe, 0x4c000102, Op_BO | Op_BI | Op_LK }, 181 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 182 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 183 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 184 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 185 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 186 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 187 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 188 { "bcctr", 0xfc0007fe, 0x4c000420, Op_BO | Op_BI | Op_LK }, 189 { "", 0x0, 0x0, 0 } 190 }; 191 192 /* 1e * 4 = 78 */ 193 const struct opcode opcodes_1e[] = { 194 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 195 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 196 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 197 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 198 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 199 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 200 { "", 0x0, 0x0, 0 } 201 }; 202 203 /* 1f * 4 = 7c */ 204 const struct opcode opcodes_1f[] = { 205 /* 1f << 2 */ 206 { "cmp", 0xfc0007fe, 0x7c000000, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 207 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 208 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 209 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 210 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 211 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 212 213 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 214 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 215 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 216 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 217 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 218 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc }, 219 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 220 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 221 { "cmpl", 0xfc0007fe, 0x7c000040, Op_crfD | Op_L | Op_A | Op_B }, 222 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 223 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 224 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 225 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 226 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 227 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 228 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 229 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 230 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 231 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 232 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 233 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 234 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 235 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 236 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 237 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 238 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 239 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 240 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 241 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 242 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 243 { "stdx", 0xfc0007fe, 0x7c00012a, Op_S | Op_A | Op_B }, 244 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_S | Op_A | Op_B }, 245 { "stwx", 0xfc0007fe, 0x7c00012e, Op_S | Op_A | Op_B }, 246 { "wrteei", 0xfc0003fe, 0x7c000146 }, /* XXX: out of flags! */ 247 { "stdux", 0xfc0007fe, 0x7c00016a, Op_S | Op_A | Op_B }, 248 { "stwux", 0xfc0007fe, 0x7c00016e, Op_S | Op_A | Op_B }, 249 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 250 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 251 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 252 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_S | Op_A | Op_B }, 253 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_S | Op_A | Op_B }, 254 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 255 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 256 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 257 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 258 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 259 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 260 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_S | Op_A | Op_B }, 261 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 262 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 263 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 264 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 265 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 266 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 267 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 268 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 269 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 270 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 271 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 272 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 273 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 274 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 275 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 276 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 277 { "sthx", 0xfc0007fe, 0x7c00032e, Op_S | Op_A | Op_B }, 278 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 279 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_S | Op_A | Op_B | Op_Rc }, 280 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 281 { "sthux", 0xfc0007fe, 0x7c00036e, Op_S | Op_A | Op_B }, 282 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 283 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 284 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 285 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 286 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 287 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 288 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 289 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 290 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 291 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 292 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 293 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 294 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 295 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 296 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 297 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 298 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 299 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 300 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 301 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 302 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 303 { "sync", 0xfc0007fe, 0x7c0004ac, 0 }, 304 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 305 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 306 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 307 { "stswx", 0xfc0007fe, 0x7c00052a, Op_S | Op_A | Op_B }, 308 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_S | Op_A | Op_B }, 309 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_S | Op_A | Op_B }, 310 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_S | Op_A | Op_B }, 311 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_S | Op_A | Op_NB }, 312 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_S | Op_A | Op_B }, 313 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_S | Op_A | Op_B }, 314 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 315 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 316 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 317 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_B | Op_Rc }, 318 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 319 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 320 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 321 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_S | Op_A | Op_B }, 322 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_B | Op_Rc }, 323 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 324 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 325 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 326 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 327 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_S | Op_A | Op_B }, 328 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 329 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 330 { "", 0x0, 0x0, 0 } 331 }; 332 333 /* 3a * 4 = e8 */ 334 const struct opcode opcodes_3a[] = { 335 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 336 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 337 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 338 { "", 0x0, 0x0, 0 } 339 }; 340 /* 3b * 4 = ec */ 341 const struct opcode opcodes_3b[] = { 342 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 343 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 344 345 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 346 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 347 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 348 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 349 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 350 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 351 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 352 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 353 { "", 0x0, 0x0, 0 } 354 }; 355 /* 3e * 4 = f8 */ 356 const struct opcode opcodes_3e[] = { 357 { "std", 0xfc000003, 0xf8000000, Op_S | Op_A | Op_ds }, 358 { "stdu", 0xfc000003, 0xf8000001, Op_S | Op_A | Op_ds }, 359 { "", 0x0, 0x0, 0 } 360 }; 361 362 /* 3f * 4 = fc */ 363 const struct opcode opcodes_3f[] = { 364 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 365 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 366 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 367 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 368 369 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 370 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 371 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 372 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 373 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 374 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 375 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 376 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 377 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 378 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 379 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 380 381 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 382 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 383 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 384 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 385 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 386 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 387 { "mtfsfi", 0xfc0007fe, 0xfc00010c, Op_crfD | Op_IMM | Op_Rc }, 388 389 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 390 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 391 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 392 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 393 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 394 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 395 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 396 { "", 0x0, 0x0, 0 } 397 }; 398 399 400 struct specialreg { 401 int reg; 402 char *name; 403 }; 404 405 const struct specialreg sprregs[] = { 406 { 0x001, "xer" }, 407 { 0x008, "lr" }, 408 { 0x009, "ctr" }, 409 { 0x012, "dsisr" }, 410 { 0x013, "dar" }, 411 { 0x016, "dec" }, 412 { 0x019, "sdr1" }, 413 { 0x01a, "srr0" }, 414 { 0x01b, "srr1" }, 415 { 0x100, "usprg0" }, 416 { 0x110, "sprg0" }, 417 { 0x111, "sprg1" }, 418 { 0x112, "sprg2" }, 419 { 0x113, "sprg3" }, 420 { 0x114, "sprg4" }, 421 { 0x115, "sprg5" }, 422 { 0x116, "sprg6" }, 423 { 0x117, "sprg7" }, 424 { 0x118, "asr" }, 425 { 0x11a, "aer" }, 426 { 0x11c, "tbl" }, 427 { 0x11d, "tbu" }, 428 { 0x11f, "pvr" }, 429 { 0x210, "ibat0u" }, 430 { 0x211, "ibat0l" }, 431 { 0x212, "ibat1u" }, 432 { 0x213, "ibat1l" }, 433 { 0x214, "ibat2u" }, 434 { 0x215, "ibat2l" }, 435 { 0x216, "ibat3u" }, 436 { 0x217, "ibat3l" }, 437 { 0x218, "dbat0u" }, 438 { 0x219, "dbat0l" }, 439 { 0x21a, "dbat1u" }, 440 { 0x21b, "dbat1l" }, 441 { 0x21c, "dbat2u" }, 442 { 0x21d, "dbat2l" }, 443 { 0x21e, "dbat3u" }, 444 { 0x21f, "dbat3l" }, 445 { 0x3b0, "zpr" }, 446 { 0x3b1, "pid" }, 447 { 0x3b3, "ccr0" }, 448 { 0x3b4, "iac3" }, 449 { 0x3b5, "iac4" }, 450 { 0x3b6, "dvc1" }, 451 { 0x3b7, "dvc2" }, 452 { 0x3b9, "sgr" }, 453 { 0x3ba, "dcwr" }, 454 { 0x3bb, "sler" }, 455 { 0x3bc, "su0r" }, 456 { 0x3bd, "dbcr1" }, 457 { 0x3d3, "icdbdr" }, 458 { 0x3d4, "esr" }, 459 { 0x3d5, "dear" }, 460 { 0x3d6, "evpr" }, 461 { 0x3d8, "tsr" }, 462 { 0x3da, "tcr" }, 463 { 0x3db, "pit" }, 464 { 0x3de, "srr2" }, 465 { 0x3df, "srr3" }, 466 { 0x3f0, "dbsr" }, 467 { 0x3f2, "dbcr0" }, 468 { 0x3f4, "iac1" }, 469 { 0x3f5, "iac2" }, 470 { 0x3f6, "dac1" }, 471 { 0x3f7, "dac2" }, 472 { 0x3f9, "l2cr" }, 473 { 0x3fa, "dccr" }, 474 { 0x3fb, "iccr" }, 475 { 0x3ff, "pir" }, 476 { 0, NULL } 477 }; 478 479 const struct specialreg dcrregs[] = { 480 { 0x010, "sdram0_cfgaddr" }, 481 { 0x011, "sdram0_cfgdata" }, 482 { 0x012, "ebc0_cfgaddr" }, 483 { 0x013, "ebc0_cfgdata" }, 484 { 0x014, "dcp0_cfgaddr" }, 485 { 0x015, "dcp0_cfgdata" }, 486 { 0x018, "ocm0_isarc" }, 487 { 0x019, "ocm0_iscntl" }, 488 { 0x01a, "ocm0_dsarc" }, 489 { 0x01b, "ocm0_dscntl" }, 490 { 0x084, "plb0_besr" }, 491 { 0x086, "plb0_bear" }, 492 { 0x087, "plb0_acr" }, 493 { 0x0a0, "pob0_besr0" }, 494 { 0x0a2, "pob0_bear" }, 495 { 0x0a4, "pob0_besr1" }, 496 { 0x0b0, "cpc0_pllmr" }, 497 { 0x0b1, "cpc0_cr0" }, 498 { 0x0b2, "cpc0_cr1" }, 499 { 0x0b4, "cpc0_psr" }, 500 { 0x0b5, "cpc0_jtagid" }, 501 { 0x0b8, "cpc0_sr" }, 502 { 0x0b9, "cpc0_er" }, 503 { 0x0ba, "cpc0_fr" }, 504 { 0x0c0, "uic0_sr" }, 505 { 0x0c2, "uic0_er" }, 506 { 0x0c3, "uic0_cr" }, 507 { 0x0c4, "uic0_pr" }, 508 { 0x0c5, "uic0_tr" }, 509 { 0x0c6, "uic0_msr" }, 510 { 0x0c7, "uic0_vr" }, 511 { 0x0c8, "uic0_vcr" }, 512 { 0x100, "dma0_cr0" }, 513 { 0x101, "dma0_ct0" }, 514 { 0x102, "dma0_da0" }, 515 { 0x103, "dma0_sa0" }, 516 { 0x104, "dma0_sg0" }, 517 { 0x108, "dma0_cr1" }, 518 { 0x109, "dma0_ct1" }, 519 { 0x10a, "dma0_da1" }, 520 { 0x10b, "dma0_sa1" }, 521 { 0x10c, "dma0_sg1" }, 522 { 0x110, "dma0_cr2" }, 523 { 0x111, "dma0_ct2" }, 524 { 0x112, "dma0_da2" }, 525 { 0x113, "dma0_sa2" }, 526 { 0x114, "dma0_sg2" }, 527 { 0x118, "dma0_cr3" }, 528 { 0x119, "dma0_ct3" }, 529 { 0x11a, "dma0_da3" }, 530 { 0x11b, "dma0_sa3" }, 531 { 0x11c, "dma0_sg3" }, 532 { 0x120, "dma0_sr" }, 533 { 0x123, "dma0_sgc" }, 534 { 0x125, "dma0_slp" }, 535 { 0x126, "dma0_pol" }, 536 { 0x180, "mal0_cfg" }, 537 { 0x181, "mal0_esr" }, 538 { 0x182, "mal0_ier" }, 539 { 0x184, "mal0_txcasr" }, 540 { 0x185, "mal0_txcarr" }, 541 { 0x186, "mal0_txeobisr" }, 542 { 0x187, "mal0_txdeir" }, 543 { 0x190, "mal0_rxcasr" }, 544 { 0x191, "mal0_rxcarr" }, 545 { 0x192, "mal0_rxeobisr" }, 546 { 0x193, "mal0_rxdeir" }, 547 { 0x1a0, "mal0_txctp0r" }, 548 { 0x1a1, "mal0_txctp1r" }, 549 { 0x1a2, "mal0_txctp2r" }, 550 { 0x1a3, "mal0_txctp3r" }, 551 { 0x1c0, "mal0_rxctp0r" }, 552 { 0x1e0, "mal0_rcbs0" }, 553 { 0, NULL } 554 }; 555 556 void 557 op_ill(instr_t instr, vm_offset_t loc) 558 { 559 db_printf("illegal instruction %x\n", instr); 560 } 561 562 u_int32_t 563 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 564 { 565 u_int32_t mask = (1 << width) - 1; 566 return ((value >> base) & mask); 567 } 568 569 const struct opcode * search_op(const struct opcode *); 570 571 void 572 disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 573 char *disasm_str) 574 { 575 char * pstr; 576 enum function_mask func; 577 578 pstr = disasm_str; 579 580 func = popcode->func; 581 if (func & Op_OE) { 582 u_int OE; 583 /* also for Op_S (they are the same) */ 584 OE = extract_field(instr, 31 - 21, 1); 585 if (OE) { 586 pstr += sprintf(pstr, "o"); 587 } 588 func &= ~Op_OE; 589 } 590 switch (func & Op_LKM) { 591 case Op_Rc: 592 if (instr & 0x1) { 593 pstr += sprintf(pstr, "."); 594 } 595 break; 596 case Op_AA: 597 if (instr & 0x2) { 598 pstr += sprintf(pstr, "a"); 599 loc = 0; /* Absolute address */ 600 } 601 case Op_LK: 602 if (instr & 0x1) { 603 pstr += sprintf(pstr, "l"); 604 } 605 break; 606 default: 607 func &= ~Op_LKM; 608 } 609 pstr += sprintf(pstr, "\t"); 610 611 /* XXX: special cases here, out of flags in a 32bit word. */ 612 if (strcmp(popcode->name, "wrteei") == 0) { 613 int E; 614 E = extract_field(instr, 31 - 16, 5); 615 pstr += sprintf(pstr, "%d", E); 616 return; 617 } 618 /* XXX: end of special cases here. */ 619 620 if (func & Op_D) { 621 u_int D; 622 /* also for Op_S (they are the same) */ 623 D = extract_field(instr, 31 - 10, 5); 624 pstr += sprintf(pstr, "r%d, ", D); 625 func &= ~Op_D; 626 } 627 if (func & Op_crbD) { 628 u_int crbD; 629 crbD = extract_field(instr, 31 - 10, 5); 630 pstr += sprintf(pstr, "crb%d, ", crbD); 631 func &= ~Op_crbD; 632 } 633 if (func & Op_crfD) { 634 u_int crfD; 635 crfD = extract_field(instr, 31 - 8, 3); 636 pstr += sprintf(pstr, "crf%d, ", crfD); 637 func &= ~Op_crfD; 638 } 639 if (func & Op_L) { 640 u_int L; 641 L = extract_field(instr, 31 - 10, 1); 642 if (L) { 643 pstr += sprintf(pstr, "L, "); 644 } 645 func &= ~Op_L; 646 } 647 if (func & Op_FM) { 648 u_int FM; 649 FM = extract_field(instr, 31 - 10, 8); 650 pstr += sprintf(pstr, "%d, ", FM); 651 func &= ~Op_FM; 652 } 653 if (func & Op_TO) { 654 u_int TO; 655 TO = extract_field(instr, 31 - 10, 1); 656 pstr += sprintf(pstr, "%d, ", TO); 657 func &= ~Op_TO; 658 } 659 if (func & Op_crfS) { 660 u_int crfS; 661 crfS = extract_field(instr, 31 - 13, 3); 662 pstr += sprintf(pstr, "%d, ", crfS); 663 func &= ~Op_crfS; 664 } 665 if (func & Op_BO) { 666 u_int BO; 667 BO = extract_field(instr, 31 - 10, 5); 668 pstr += sprintf(pstr, "%d, ", BO); 669 func &= ~Op_BO; 670 } 671 if (func & Op_A) { 672 u_int A; 673 A = extract_field(instr, 31 - 15, 5); 674 pstr += sprintf(pstr, "r%d, ", A); 675 func &= ~Op_A; 676 } 677 if (func & Op_B) { 678 u_int B; 679 B = extract_field(instr, 31 - 20, 5); 680 pstr += sprintf(pstr, "r%d, ", B); 681 func &= ~Op_B; 682 } 683 if (func & Op_C) { 684 u_int C; 685 C = extract_field(instr, 31 - 25, 5); 686 pstr += sprintf(pstr, "r%d, ", C); 687 func &= ~Op_C; 688 } 689 if (func & Op_BI) { 690 u_int BI; 691 BI = extract_field(instr, 31 - 10, 5); 692 pstr += sprintf(pstr, "%d, ", BI); 693 func &= ~Op_BI; 694 } 695 if (func & Op_crbA) { 696 u_int crbA; 697 crbA = extract_field(instr, 31 - 15, 5); 698 pstr += sprintf(pstr, "%d, ", crbA); 699 func &= ~Op_crbA; 700 } 701 if (func & Op_crbB) { 702 u_int crbB; 703 crbB = extract_field(instr, 31 - 20, 5); 704 pstr += sprintf(pstr, "%d, ", crbB); 705 func &= ~Op_crbB; 706 } 707 if (func & Op_CRM) { 708 u_int CRM; 709 CRM = extract_field(instr, 31 - 19, 8); 710 pstr += sprintf(pstr, "0x%x, ", CRM); 711 func &= ~Op_CRM; 712 } 713 if (func & Op_LI) { 714 int LI; 715 LI = extract_field(instr, 31 - 29, 24); 716 /* Need to sign extend and shift up 2, then add addr */ 717 LI = LI << 8; 718 LI = LI >> 6; 719 LI += loc; 720 pstr += sprintf (pstr, "0x%x, ", LI); 721 func &= ~Op_LI; 722 } 723 switch (func & Op_SIMM) { 724 u_int IMM; 725 case Op_SIMM: /* same as Op_d */ 726 IMM = extract_field(instr, 31 - 31, 16); 727 if (IMM & 0x8000) { 728 pstr += sprintf(pstr, "-"); 729 IMM = 0x10000-IMM; 730 } 731 func &= ~Op_SIMM; 732 goto common; 733 case Op_UIMM: 734 IMM = extract_field(instr, 31 - 31, 16); 735 func &= ~Op_UIMM; 736 goto common; 737 common: 738 pstr += sprintf(pstr, "0x%x", IMM); 739 break; 740 default: 741 break; 742 } 743 if (func & Op_BD) { 744 u_int BD; 745 BD = extract_field(instr, 31 - 29, 14); 746 pstr += sprintf(pstr, "0x%x, ", BD); 747 func &= ~Op_BD; 748 } 749 if (func & Op_ds) { 750 u_int ds; 751 ds = extract_field(instr, 31 - 29, 14) << 2; 752 pstr += sprintf(pstr, "0x%x, ", ds); 753 func &= ~Op_ds; 754 } 755 if (func & Op_spr) { 756 u_int spr; 757 u_int sprl; 758 u_int sprh; 759 const struct specialreg *regs; 760 int i; 761 sprl = extract_field(instr, 31 - 15, 5); 762 sprh = extract_field(instr, 31 - 20, 5); 763 spr = sprh << 5 | sprl; 764 765 /* ugly hack - out of bitfields in the function mask */ 766 if (popcode->name[2] == 'd') /* m.Dcr */ 767 regs = dcrregs; 768 else 769 regs = sprregs; 770 for (i = 0; regs[i].name != NULL; i++) 771 if (spr == regs[i].reg) 772 break; 773 if (regs[i].reg == 0) 774 pstr += sprintf(pstr, "[unknown special reg (%d)]", spr); 775 else 776 pstr += sprintf(pstr, "%s", regs[i].name); 777 func &= ~Op_spr; 778 } 779 780 if (func & Op_me) { 781 u_int me, mel, meh; 782 mel = extract_field(instr, 31 - 25, 4); 783 meh = extract_field(instr, 31 - 26, 1); 784 me = meh << 4 | mel; 785 pstr += sprintf(pstr, ", 0x%x", me); 786 func &= ~Op_me; 787 } 788 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 789 u_int MB; 790 u_int ME; 791 MB = extract_field(instr, 31 - 20, 5); 792 pstr += sprintf(pstr, ", %d", MB); 793 ME = extract_field(instr, 31 - 25, 5); 794 pstr += sprintf(pstr, ", %d", ME); 795 } 796 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 797 u_int SH; 798 SH = extract_field(instr, 31 - 20, 5); 799 pstr += sprintf(pstr, ", %d", SH); 800 } 801 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 802 u_int sh, shl, shh; 803 shl = extract_field(instr, 31 - 19, 4); 804 shh = extract_field(instr, 31 - 20, 1); 805 sh = shh << 4 | shl; 806 pstr += sprintf(pstr, ", %d", sh); 807 } 808 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 809 u_int mb, mbl, mbh; 810 mbl = extract_field(instr, 31 - 25, 4); 811 mbh = extract_field(instr, 31 - 26, 1); 812 mb = mbh << 4 | mbl; 813 pstr += sprintf(pstr, ", %d", mb); 814 } 815 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 816 u_int me, mel, meh; 817 mel = extract_field(instr, 31 - 25, 4); 818 meh = extract_field(instr, 31 - 26, 1); 819 me = meh << 4 | mel; 820 pstr += sprintf(pstr, ", %d", me); 821 } 822 if (func & Op_tbr) { 823 u_int tbr; 824 u_int tbrl; 825 u_int tbrh; 826 char *reg; 827 tbrl = extract_field(instr, 31 - 15, 5); 828 tbrh = extract_field(instr, 31 - 20, 5); 829 tbr = tbrh << 5 | tbrl; 830 831 switch (tbr) { 832 case 268: 833 reg = "tbl"; 834 break; 835 case 269: 836 reg = "tbu"; 837 break; 838 default: 839 reg = 0; 840 } 841 if (reg == 0) 842 pstr += sprintf(pstr, ", [unknown tbr %d ]", tbr); 843 else 844 pstr += sprintf(pstr, ", %s", reg); 845 func &= ~Op_tbr; 846 } 847 if (func & Op_SR) { 848 u_int SR; 849 SR = extract_field(instr, 31 - 15, 3); 850 pstr += sprintf(pstr, ", sr%d", SR); 851 func &= ~Op_SR; 852 } 853 if (func & Op_NB) { 854 u_int NB; 855 NB = extract_field(instr, 31 - 20, 5); 856 if (NB == 0) 857 NB = 32; 858 pstr += sprintf(pstr, ", %d", NB); 859 func &= ~Op_SR; 860 } 861 if (func & Op_IMM) { 862 u_int IMM; 863 IMM = extract_field(instr, 31 - 19, 4); 864 pstr += sprintf(pstr, ", %d", IMM); 865 func &= ~Op_SR; 866 } 867 } 868 869 void 870 op_base(instr_t instr, vm_offset_t loc) 871 { 872 dis_ppc(opcodes, instr, loc); 873 } 874 875 void 876 op_cl_x13(instr_t instr, vm_offset_t loc) 877 { 878 dis_ppc(opcodes_13, instr, loc); 879 } 880 881 void 882 op_cl_x1e(instr_t instr, vm_offset_t loc) 883 { 884 dis_ppc(opcodes_1e, instr, loc); 885 } 886 887 void 888 op_cl_x1f(instr_t instr, vm_offset_t loc) 889 { 890 dis_ppc(opcodes_1f, instr, loc); 891 } 892 893 void 894 op_cl_x3a(instr_t instr, vm_offset_t loc) 895 { 896 dis_ppc(opcodes_3a, instr, loc); 897 } 898 899 void 900 op_cl_x3b(instr_t instr, vm_offset_t loc) 901 { 902 dis_ppc(opcodes_3b, instr, loc); 903 } 904 905 void 906 op_cl_x3e(instr_t instr, vm_offset_t loc) 907 { 908 dis_ppc(opcodes_3e, instr, loc); 909 } 910 911 void 912 op_cl_x3f(instr_t instr, vm_offset_t loc) 913 { 914 dis_ppc(opcodes_3f, instr, loc); 915 } 916 917 void 918 dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) 919 { 920 const struct opcode *op; 921 int found = 0; 922 int i; 923 char disasm_str[30]; 924 925 for (i = 0, op = &opcodeset[0]; 926 found == 0 && op->mask != 0; 927 i++, op = &opcodeset[i]) { 928 if ((instr & op->mask) == op->code) { 929 found = 1; 930 disasm_fields(op, instr, loc, disasm_str); 931 db_printf("%s%s\n", op->name, disasm_str); 932 return; 933 } 934 } 935 op_ill(instr, loc); 936 } 937 938 db_addr_t 939 db_disasm(db_addr_t loc, boolean_t extended) 940 { 941 int class; 942 instr_t opcode; 943 opcode = *(instr_t *)(loc); 944 class = opcode >> 26; 945 (opcodes_base[class])(opcode, loc); 946 947 return (loc + 4); 948 } 949 950 vm_offset_t opc_disasm(vm_offset_t loc, int); 951 952 vm_offset_t 953 opc_disasm(vm_offset_t loc, int xin) 954 { 955 int class; 956 instr_t opcode; 957 opcode = xin; 958 class = opcode >> 26; 959 (opcodes_base[class])(opcode, loc); 960 961 return (loc + 4); 962 } 963