1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Marcel Moolenaar 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/ktr.h> 36 #include <sys/bus.h> 37 #include <sys/cpuset.h> 38 #include <sys/domainset.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/pcpu.h> 43 #include <sys/proc.h> 44 #include <sys/sched.h> 45 #include <sys/smp.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_param.h> 49 #include <vm/pmap.h> 50 #include <vm/vm_map.h> 51 #include <vm/vm_extern.h> 52 #include <vm/vm_kern.h> 53 54 #include <machine/bus.h> 55 #include <machine/cpu.h> 56 #include <machine/intr_machdep.h> 57 #include <machine/pcb.h> 58 #include <machine/platform.h> 59 #include <machine/md_var.h> 60 #include <machine/setjmp.h> 61 #include <machine/smp.h> 62 63 #include "pic_if.h" 64 65 volatile static int ap_awake; 66 volatile static u_int ap_letgo; 67 volatile static u_quad_t ap_timebase; 68 static u_int ipi_msg_cnt[32]; 69 static struct mtx ap_boot_mtx; 70 struct pcb stoppcbs[MAXCPU]; 71 72 void 73 machdep_ap_bootstrap(void) 74 { 75 76 PCPU_SET(awake, 1); 77 __asm __volatile("msync; isync"); 78 79 while (ap_letgo == 0) 80 nop_prio_vlow(); 81 nop_prio_medium(); 82 83 /* 84 * Set timebase as soon as possible to meet an implicit rendezvous 85 * from cpu_mp_unleash(), which sets ap_letgo and then immediately 86 * sets timebase. 87 * 88 * Note that this is instrinsically racy and is only relevant on 89 * platforms that do not support better mechanisms. 90 */ 91 platform_smp_timebase_sync(ap_timebase, 1); 92 93 /* Give platform code a chance to do anything else necessary */ 94 platform_smp_ap_init(); 95 96 /* Initialize decrementer */ 97 decr_ap_init(); 98 99 /* Serialize console output and AP count increment */ 100 mtx_lock_spin(&ap_boot_mtx); 101 ap_awake++; 102 if (bootverbose) 103 printf("SMP: AP CPU #%d launched\n", PCPU_GET(cpuid)); 104 else 105 printf("%s%d%s", ap_awake == 2 ? "Launching APs: " : "", 106 PCPU_GET(cpuid), ap_awake == mp_ncpus ? "\n" : " "); 107 mtx_unlock_spin(&ap_boot_mtx); 108 109 while(smp_started == 0) 110 ; 111 112 /* Start per-CPU event timers. */ 113 cpu_initclocks_ap(); 114 115 /* Announce ourselves awake, and enter the scheduler */ 116 sched_throw(NULL); 117 } 118 119 void 120 cpu_mp_setmaxid(void) 121 { 122 struct cpuref cpuref; 123 int error; 124 125 mp_ncpus = 0; 126 mp_maxid = 0; 127 error = platform_smp_first_cpu(&cpuref); 128 while (!error) { 129 mp_ncpus++; 130 mp_maxid = max(cpuref.cr_cpuid, mp_maxid); 131 error = platform_smp_next_cpu(&cpuref); 132 } 133 /* Sanity. */ 134 if (mp_ncpus == 0) 135 mp_ncpus = 1; 136 } 137 138 int 139 cpu_mp_probe(void) 140 { 141 142 /* 143 * We're not going to enable SMP if there's only 1 processor. 144 */ 145 return (mp_ncpus > 1); 146 } 147 148 void 149 cpu_mp_start(void) 150 { 151 struct cpuref bsp, cpu; 152 struct pcpu *pc; 153 int domain, error; 154 155 error = platform_smp_get_bsp(&bsp); 156 KASSERT(error == 0, ("Don't know BSP")); 157 158 error = platform_smp_first_cpu(&cpu); 159 while (!error) { 160 if (cpu.cr_cpuid >= MAXCPU) { 161 printf("SMP: cpu%d: skipped -- ID out of range\n", 162 cpu.cr_cpuid); 163 goto next; 164 } 165 if (CPU_ISSET(cpu.cr_cpuid, &all_cpus)) { 166 printf("SMP: cpu%d: skipped - duplicate ID\n", 167 cpu.cr_cpuid); 168 goto next; 169 } 170 171 if (vm_ndomains > 1) 172 domain = cpu.cr_domain; 173 else 174 domain = 0; 175 176 if (cpu.cr_cpuid != bsp.cr_cpuid) { 177 void *dpcpu; 178 179 pc = &__pcpu[cpu.cr_cpuid]; 180 dpcpu = (void *)kmem_malloc_domainset(DOMAINSET_PREF(domain), 181 DPCPU_SIZE, M_WAITOK | M_ZERO); 182 pcpu_init(pc, cpu.cr_cpuid, sizeof(*pc)); 183 dpcpu_init(dpcpu, cpu.cr_cpuid); 184 } else { 185 pc = pcpup; 186 pc->pc_cpuid = bsp.cr_cpuid; 187 pc->pc_bsp = 1; 188 } 189 pc->pc_domain = domain; 190 pc->pc_hwref = cpu.cr_hwref; 191 192 CPU_SET(pc->pc_cpuid, &cpuset_domain[pc->pc_domain]); 193 KASSERT(pc->pc_domain < MAXMEMDOM, ("bad domain value %d\n", 194 pc->pc_domain)); 195 CPU_SET(pc->pc_cpuid, &all_cpus); 196 next: 197 error = platform_smp_next_cpu(&cpu); 198 } 199 200 #ifdef SMP 201 platform_smp_probe_threads(); 202 #endif 203 } 204 205 void 206 cpu_mp_announce(void) 207 { 208 struct pcpu *pc; 209 int i; 210 211 if (!bootverbose) 212 return; 213 214 CPU_FOREACH(i) { 215 pc = pcpu_find(i); 216 if (pc == NULL) 217 continue; 218 printf("cpu%d: dev=%x domain=%d ", i, (int)pc->pc_hwref, pc->pc_domain); 219 if (pc->pc_bsp) 220 printf(" (BSP)"); 221 printf("\n"); 222 } 223 } 224 225 static void 226 cpu_mp_unleash(void *dummy) 227 { 228 struct pcpu *pc; 229 int cpus, timeout; 230 int ret; 231 232 if (mp_ncpus <= 1) 233 return; 234 235 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 236 237 cpus = 0; 238 smp_cpus = 0; 239 #ifdef BOOKE 240 tlb1_ap_prep(); 241 #endif 242 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 243 cpus++; 244 if (!pc->pc_bsp) { 245 if (bootverbose) 246 printf("Waking up CPU %d (dev=%x)\n", 247 pc->pc_cpuid, (int)pc->pc_hwref); 248 249 ret = platform_smp_start_cpu(pc); 250 if (ret == 0) { 251 timeout = 2000; /* wait 2sec for the AP */ 252 while (!pc->pc_awake && --timeout > 0) 253 DELAY(1000); 254 } 255 } else { 256 pc->pc_awake = 1; 257 } 258 if (pc->pc_awake) { 259 if (bootverbose) 260 printf("Adding CPU %d, hwref=%jx, awake=%x\n", 261 pc->pc_cpuid, (uintmax_t)pc->pc_hwref, 262 pc->pc_awake); 263 smp_cpus++; 264 } else 265 CPU_SET(pc->pc_cpuid, &stopped_cpus); 266 } 267 268 ap_awake = 1; 269 270 /* Provide our current DEC and TB values for APs */ 271 ap_timebase = mftb() + 10; 272 __asm __volatile("msync; isync"); 273 274 /* Let APs continue */ 275 atomic_store_rel_int(&ap_letgo, 1); 276 277 platform_smp_timebase_sync(ap_timebase, 0); 278 279 while (ap_awake < smp_cpus) 280 ; 281 282 if (smp_cpus != cpus || cpus != mp_ncpus) { 283 printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n", 284 mp_ncpus, cpus, smp_cpus); 285 } 286 287 if (smp_cpus > 1) 288 atomic_store_rel_int(&smp_started, 1); 289 290 /* Let the APs get into the scheduler */ 291 DELAY(10000); 292 293 } 294 295 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL); 296 297 int 298 powerpc_ipi_handler(void *arg) 299 { 300 u_int cpuid; 301 uint32_t ipimask; 302 int msg; 303 304 CTR2(KTR_SMP, "%s: MSR 0x%08x", __func__, mfmsr()); 305 306 ipimask = atomic_readandclear_32(&(pcpup->pc_ipimask)); 307 if (ipimask == 0) 308 return (FILTER_STRAY); 309 while ((msg = ffs(ipimask) - 1) != -1) { 310 ipimask &= ~(1u << msg); 311 ipi_msg_cnt[msg]++; 312 switch (msg) { 313 case IPI_AST: 314 CTR1(KTR_SMP, "%s: IPI_AST", __func__); 315 break; 316 case IPI_PREEMPT: 317 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); 318 sched_preempt(curthread); 319 break; 320 case IPI_RENDEZVOUS: 321 CTR1(KTR_SMP, "%s: IPI_RENDEZVOUS", __func__); 322 smp_rendezvous_action(); 323 break; 324 case IPI_STOP: 325 326 /* 327 * IPI_STOP_HARD is mapped to IPI_STOP so it is not 328 * necessary to add such case in the switch. 329 */ 330 CTR1(KTR_SMP, "%s: IPI_STOP or IPI_STOP_HARD (stop)", 331 __func__); 332 cpuid = PCPU_GET(cpuid); 333 savectx(&stoppcbs[cpuid]); 334 CPU_SET_ATOMIC(cpuid, &stopped_cpus); 335 while (!CPU_ISSET(cpuid, &started_cpus)) 336 cpu_spinwait(); 337 CPU_CLR_ATOMIC(cpuid, &stopped_cpus); 338 CPU_CLR_ATOMIC(cpuid, &started_cpus); 339 CTR1(KTR_SMP, "%s: IPI_STOP (restart)", __func__); 340 break; 341 case IPI_HARDCLOCK: 342 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); 343 hardclockintr(); 344 break; 345 } 346 } 347 348 return (FILTER_HANDLED); 349 } 350 351 static void 352 ipi_send(struct pcpu *pc, int ipi) 353 { 354 355 CTR4(KTR_SMP, "%s: pc=%p, targetcpu=%d, IPI=%d", __func__, 356 pc, pc->pc_cpuid, ipi); 357 358 atomic_set_32(&pc->pc_ipimask, (1 << ipi)); 359 powerpc_sync(); 360 PIC_IPI(root_pic, pc->pc_cpuid); 361 362 CTR1(KTR_SMP, "%s: sent", __func__); 363 } 364 365 /* Send an IPI to a set of cpus. */ 366 void 367 ipi_selected(cpuset_t cpus, int ipi) 368 { 369 struct pcpu *pc; 370 371 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 372 if (CPU_ISSET(pc->pc_cpuid, &cpus)) 373 ipi_send(pc, ipi); 374 } 375 } 376 377 /* Send an IPI to a specific CPU. */ 378 void 379 ipi_cpu(int cpu, u_int ipi) 380 { 381 382 ipi_send(cpuid_to_pcpu[cpu], ipi); 383 } 384 385 /* Send an IPI to all CPUs EXCEPT myself. */ 386 void 387 ipi_all_but_self(int ipi) 388 { 389 struct pcpu *pc; 390 391 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 392 if (pc != pcpup) 393 ipi_send(pc, ipi); 394 } 395 } 396