1 /*- 2 * Copyright (C) 2002 Benno Rice. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/conf.h> 32 #include <sys/kernel.h> 33 34 #include <machine/bus.h> 35 #include <machine/intr.h> 36 #include <machine/intr_machdep.h> 37 #include <machine/md_var.h> 38 #include <machine/pio.h> 39 #include <machine/resource.h> 40 41 #include <vm/vm.h> 42 #include <vm/pmap.h> 43 44 #include <sys/rman.h> 45 46 #include <machine/openpicreg.h> 47 #include <machine/openpicvar.h> 48 49 #include "pic_if.h" 50 51 /* 52 * Local routines 53 */ 54 static u_int openpic_read(struct openpic_softc *, int); 55 static void openpic_write(struct openpic_softc *, int, u_int); 56 static int openpic_read_irq(struct openpic_softc *, int); 57 static void openpic_eoi(struct openpic_softc *, int); 58 static void openpic_enable_irq(struct openpic_softc *, int, int); 59 static void openpic_disable_irq(struct openpic_softc *, int); 60 static void openpic_set_priority(struct openpic_softc *, int, int); 61 static void openpic_intr(void); 62 static void openpic_ext_enable_irq(uintptr_t); 63 static void openpic_ext_disable_irq(uintptr_t); 64 65 /* XXX This limits us to one openpic */ 66 static struct openpic_softc *openpic_softc; 67 68 /* 69 * Called at nexus-probe time to allow interrupts to be enabled by 70 * devices that are probed before the OpenPIC h/w is probed. 71 */ 72 int 73 openpic_early_attach(device_t dev) 74 { 75 struct openpic_softc *sc; 76 77 sc = device_get_softc(dev); 78 openpic_softc = sc; 79 80 sc->sc_rman.rm_type = RMAN_ARRAY; 81 sc->sc_rman.rm_descr = device_get_nameunit(dev); 82 83 if (rman_init(&sc->sc_rman) != 0 || 84 rman_manage_region(&sc->sc_rman, 0, OPENPIC_IRQMAX-1) != 0) { 85 device_printf(dev, "could not set up resource management"); 86 return (ENXIO); 87 } 88 89 intr_init(openpic_intr, OPENPIC_IRQMAX, openpic_ext_enable_irq, 90 openpic_ext_disable_irq); 91 92 sc->sc_early_done = 1; 93 94 return (0); 95 } 96 97 int 98 openpic_attach(device_t dev) 99 { 100 struct openpic_softc *sc; 101 u_int irq; 102 u_int32_t x; 103 104 sc = device_get_softc(dev); 105 sc->sc_hwprobed = 1; 106 107 if (!sc->sc_early_done) 108 openpic_early_attach(dev); 109 110 x = openpic_read(sc, OPENPIC_FEATURE); 111 switch (x & OPENPIC_FEATURE_VERSION_MASK) { 112 case 1: 113 sc->sc_version = "1.0"; 114 break; 115 case 2: 116 sc->sc_version = "1.2"; 117 break; 118 case 3: 119 sc->sc_version = "1.3"; 120 break; 121 default: 122 sc->sc_version = "unknown"; 123 break; 124 } 125 126 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >> 127 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1; 128 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >> 129 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1; 130 131 /* 132 * PSIM seems to report 1 too many IRQs 133 */ 134 if (sc->sc_psim) 135 sc->sc_nirq--; 136 137 if (bootverbose) 138 device_printf(dev, 139 "Version %s, supports %d CPUs and %d irqs\n", 140 sc->sc_version, sc->sc_ncpu, sc->sc_nirq); 141 142 /* disable all interrupts */ 143 for (irq = 0; irq < sc->sc_nirq; irq++) 144 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK); 145 146 openpic_set_priority(sc, 0, 15); 147 148 /* we don't need 8259 passthrough mode */ 149 x = openpic_read(sc, OPENPIC_CONFIG); 150 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE; 151 openpic_write(sc, OPENPIC_CONFIG, x); 152 153 /* send all interrupts to cpu 0 */ 154 for (irq = 0; irq < sc->sc_nirq; irq++) 155 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0); 156 157 for (irq = 0; irq < sc->sc_nirq; irq++) { 158 x = irq; 159 x |= OPENPIC_IMASK; 160 x |= OPENPIC_POLARITY_POSITIVE; 161 x |= OPENPIC_SENSE_LEVEL; 162 x |= 8 << OPENPIC_PRIORITY_SHIFT; 163 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 164 } 165 166 /* XXX IPI */ 167 /* XXX set spurious intr vector */ 168 169 openpic_set_priority(sc, 0, 0); 170 171 /* clear all pending interrupts */ 172 for (irq = 0; irq < sc->sc_nirq; irq++) { 173 openpic_read_irq(sc, 0); 174 openpic_eoi(sc, 0); 175 } 176 177 /* enable pre-h/w reserved irqs, disable all others */ 178 for (irq = 0; irq < sc->sc_nirq; irq++) 179 if (sc->sc_irqrsv[irq]) 180 openpic_enable_irq(sc, irq, IST_LEVEL); 181 else 182 openpic_disable_irq(sc, irq); 183 184 return (0); 185 } 186 187 /* 188 * PIC interface 189 */ 190 191 struct resource * 192 openpic_allocate_intr(device_t dev, device_t child, int *rid, u_long intr, 193 u_int flags) 194 { 195 struct openpic_softc *sc; 196 struct resource *rv; 197 int needactivate; 198 199 sc = device_get_softc(dev); 200 needactivate = flags & RF_ACTIVE; 201 flags &= ~RF_ACTIVE; 202 203 if (sc->sc_hwprobed && (intr > sc->sc_nirq)) { 204 device_printf(dev, "interrupt reservation %ld out of range\n", 205 intr); 206 return (NULL); 207 } 208 209 rv = rman_reserve_resource(&sc->sc_rman, intr, intr, 1, flags, child); 210 if (rv == NULL) { 211 device_printf(dev, "interrupt reservation failed for %s\n", 212 device_get_nameunit(child)); 213 return (NULL); 214 } 215 rman_set_rid(rv, *rid); 216 if (needactivate) { 217 if (bus_activate_resource(child, SYS_RES_IRQ, *rid, rv) != 0) { 218 device_printf(dev, 219 "resource activation failed for %s\n", 220 device_get_nameunit(child)); 221 rman_release_resource(rv); 222 return (NULL); 223 } 224 } 225 226 return (rv); 227 } 228 229 int 230 openpic_setup_intr(device_t dev, device_t child, struct resource *res, 231 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 232 void **cookiep) 233 { 234 struct openpic_softc *sc; 235 u_long start; 236 int error; 237 238 sc = device_get_softc(dev); 239 start = rman_get_start(res); 240 241 if (res == NULL) { 242 device_printf(dev, "null interrupt resource from %s\n", 243 device_get_nameunit(child)); 244 return (EINVAL); 245 } 246 247 if ((rman_get_flags(res) & RF_SHAREABLE) == 0) 248 flags |= INTR_EXCL; 249 250 /* 251 * We depend here on rman_activate_resource() being idempotent. 252 */ 253 error = rman_activate_resource(res); 254 if (error) 255 return (error); 256 257 error = inthand_add(device_get_nameunit(child), start, filt, intr, arg, 258 flags, cookiep); 259 260 if (sc->sc_hwprobed) 261 openpic_enable_irq(sc, start, IST_LEVEL); 262 else 263 sc->sc_irqrsv[start] = 1; 264 265 return (error); 266 } 267 268 int 269 openpic_teardown_intr(device_t dev, device_t child, struct resource *res, 270 void *ih) 271 { 272 int error; 273 274 error = rman_deactivate_resource(res); 275 if (error) 276 return (error); 277 278 error = inthand_remove(rman_get_start(res), ih); 279 280 return (error); 281 } 282 283 int 284 openpic_release_intr(device_t dev, device_t child, int rid, 285 struct resource *res) 286 { 287 int error; 288 289 if (rman_get_flags(res) & RF_ACTIVE) { 290 error = bus_deactivate_resource(child, SYS_RES_IRQ, rid, res); 291 if (error) 292 return (error); 293 } 294 295 return (rman_release_resource(res)); 296 } 297 298 /* 299 * Local routines 300 */ 301 302 static u_int 303 openpic_read(struct openpic_softc *sc, int reg) 304 { 305 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); 306 } 307 308 static void 309 openpic_write(struct openpic_softc *sc, int reg, u_int val) 310 { 311 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); 312 } 313 314 static int 315 openpic_read_irq(struct openpic_softc *sc, int cpu) 316 { 317 return openpic_read(sc, OPENPIC_IACK(cpu)) & OPENPIC_VECTOR_MASK; 318 } 319 320 static void 321 openpic_eoi(struct openpic_softc *sc, int cpu) 322 { 323 openpic_write(sc, OPENPIC_EOI(cpu), 0); 324 } 325 326 static void 327 openpic_enable_irq(struct openpic_softc *sc, int irq, int type) 328 { 329 u_int x; 330 331 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); 332 x &= ~(OPENPIC_IMASK | OPENPIC_SENSE_LEVEL | OPENPIC_SENSE_EDGE); 333 if (type == IST_LEVEL) 334 x |= OPENPIC_SENSE_LEVEL; 335 else 336 x |= OPENPIC_SENSE_EDGE; 337 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 338 } 339 340 static void 341 openpic_disable_irq(struct openpic_softc *sc, int irq) 342 { 343 u_int x; 344 345 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq)); 346 x |= OPENPIC_IMASK; 347 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x); 348 } 349 350 static void 351 openpic_set_priority(struct openpic_softc *sc, int cpu, int pri) 352 { 353 u_int x; 354 355 x = openpic_read(sc, OPENPIC_CPU_PRIORITY(cpu)); 356 x &= ~OPENPIC_CPU_PRIORITY_MASK; 357 x |= pri; 358 openpic_write(sc, OPENPIC_CPU_PRIORITY(cpu), x); 359 } 360 361 static void 362 openpic_intr(void) 363 { 364 struct openpic_softc *sc; 365 int irq; 366 u_int32_t msr; 367 368 sc = openpic_softc; 369 msr = mfmsr(); 370 371 irq = openpic_read_irq(sc, 0); 372 if (irq == 255) { 373 return; 374 } 375 376 start: 377 openpic_disable_irq(sc, irq); 378 /*mtmsr(msr | PSL_EE);*/ 379 380 /* do the interrupt thang */ 381 intr_handle(irq); 382 383 mtmsr(msr); 384 385 openpic_eoi(sc, 0); 386 387 irq = openpic_read_irq(sc, 0); 388 if (irq != 255) 389 goto start; 390 } 391 392 static void 393 openpic_ext_enable_irq(uintptr_t irq) 394 { 395 if (!openpic_softc->sc_hwprobed) 396 return; 397 398 openpic_enable_irq(openpic_softc, irq, IST_LEVEL); 399 } 400 401 static void 402 openpic_ext_disable_irq(uintptr_t irq) 403 { 404 if (!openpic_softc->sc_hwprobed) 405 return; 406 407 openpic_disable_irq(openpic_softc, irq); 408 } 409