1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2010 Nathan Whitehorn 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/sockio.h> 33 #include <sys/endian.h> 34 #include <sys/lock.h> 35 #include <sys/mbuf.h> 36 #include <sys/module.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 42 #include <vm/vm.h> 43 #include <vm/pmap.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/ethernet.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 #include <net/if_dl.h> 52 53 #include <machine/pio.h> 54 #include <machine/bus.h> 55 #include <machine/platform.h> 56 #include <machine/resource.h> 57 #include <sys/bus.h> 58 #include <sys/rman.h> 59 60 #include "ps3bus.h" 61 #include "ps3-hvcall.h" 62 #include "if_glcreg.h" 63 64 static int glc_probe(device_t); 65 static int glc_attach(device_t); 66 static void glc_init(void *xsc); 67 static void glc_start(if_t ifp); 68 static int glc_ioctl(if_t ifp, u_long cmd, caddr_t data); 69 static void glc_set_multicast(struct glc_softc *sc); 70 static int glc_add_rxbuf(struct glc_softc *sc, int idx); 71 static int glc_add_rxbuf_dma(struct glc_softc *sc, int idx); 72 static int glc_encap(struct glc_softc *sc, struct mbuf **m_head, 73 bus_addr_t *pktdesc); 74 static int glc_intr_filter(void *xsc); 75 static void glc_intr(void *xsc); 76 static void glc_tick(void *xsc); 77 static void glc_media_status(if_t ifp, struct ifmediareq *ifmr); 78 static int glc_media_change(if_t ifp); 79 80 static MALLOC_DEFINE(M_GLC, "gelic", "PS3 GELIC ethernet"); 81 82 static device_method_t glc_methods[] = { 83 /* Device interface */ 84 DEVMETHOD(device_probe, glc_probe), 85 DEVMETHOD(device_attach, glc_attach), 86 { 0, 0 } 87 }; 88 89 static driver_t glc_driver = { 90 "glc", 91 glc_methods, 92 sizeof(struct glc_softc) 93 }; 94 95 DRIVER_MODULE(glc, ps3bus, glc_driver, 0, 0); 96 97 static int 98 glc_probe(device_t dev) 99 { 100 101 if (ps3bus_get_bustype(dev) != PS3_BUSTYPE_SYSBUS || 102 ps3bus_get_devtype(dev) != PS3_DEVTYPE_GELIC) 103 return (ENXIO); 104 105 device_set_desc(dev, "Playstation 3 GELIC Network Controller"); 106 return (BUS_PROBE_SPECIFIC); 107 } 108 109 static void 110 glc_getphys(void *xaddr, bus_dma_segment_t *segs, int nsegs, int error) 111 { 112 if (error != 0) 113 return; 114 115 *(bus_addr_t *)xaddr = segs[0].ds_addr; 116 } 117 118 static int 119 glc_attach(device_t dev) 120 { 121 struct glc_softc *sc; 122 struct glc_txsoft *txs; 123 uint64_t mac64, val, junk; 124 int i, err; 125 126 sc = device_get_softc(dev); 127 128 sc->sc_bus = ps3bus_get_bus(dev); 129 sc->sc_dev = ps3bus_get_device(dev); 130 sc->sc_self = dev; 131 132 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 133 MTX_DEF); 134 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 135 sc->next_txdma_slot = 0; 136 sc->bsy_txdma_slots = 0; 137 sc->sc_next_rxdma_slot = 0; 138 sc->first_used_txdma_slot = -1; 139 140 /* 141 * Shut down existing tasks. 142 */ 143 144 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 145 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 146 147 sc->sc_ifp = if_alloc(IFT_ETHER); 148 if_setsoftc(sc->sc_ifp, sc); 149 150 /* 151 * Get MAC address and VLAN id 152 */ 153 154 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_MAC_ADDRESS, 155 0, 0, 0, &mac64, &junk); 156 memcpy(sc->sc_enaddr, &((uint8_t *)&mac64)[2], sizeof(sc->sc_enaddr)); 157 sc->sc_tx_vlan = sc->sc_rx_vlan = -1; 158 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 159 GELIC_VLAN_TX_ETHERNET, 0, 0, &val, &junk); 160 if (err == 0) 161 sc->sc_tx_vlan = val; 162 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID, 163 GELIC_VLAN_RX_ETHERNET, 0, 0, &val, &junk); 164 if (err == 0) 165 sc->sc_rx_vlan = val; 166 167 /* 168 * Set up interrupt handler 169 */ 170 sc->sc_irqid = 0; 171 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqid, 172 RF_ACTIVE); 173 if (sc->sc_irq == NULL) { 174 device_printf(dev, "Could not allocate IRQ!\n"); 175 mtx_destroy(&sc->sc_mtx); 176 return (ENXIO); 177 } 178 179 bus_setup_intr(dev, sc->sc_irq, 180 INTR_TYPE_NET | INTR_MPSAFE | INTR_ENTROPY, 181 glc_intr_filter, glc_intr, sc, &sc->sc_irqctx); 182 sc->sc_hwirq_status = (uint64_t *)contigmalloc(8, M_GLC, M_ZERO, 0, 183 BUS_SPACE_MAXADDR_32BIT, 8, PAGE_SIZE); 184 lv1_net_set_interrupt_status_indicator(sc->sc_bus, sc->sc_dev, 185 vtophys(sc->sc_hwirq_status), 0); 186 lv1_net_set_interrupt_mask(sc->sc_bus, sc->sc_dev, 187 GELIC_INT_RXDONE | GELIC_INT_RXFRAME | GELIC_INT_PHY | 188 GELIC_INT_TX_CHAIN_END, 0); 189 190 /* 191 * Set up DMA. 192 */ 193 194 err = bus_dma_tag_create(bus_get_dma_tag(dev), 32, 0, 195 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 196 129*sizeof(struct glc_dmadesc), 1, 128*sizeof(struct glc_dmadesc), 197 0, NULL,NULL, &sc->sc_dmadesc_tag); 198 199 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_txdmadesc, 200 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 201 &sc->sc_txdmadesc_map); 202 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 203 sc->sc_txdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 204 &sc->sc_txdmadesc_phys, 0); 205 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_rxdmadesc, 206 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 207 &sc->sc_rxdmadesc_map); 208 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 209 sc->sc_rxdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys, 210 &sc->sc_rxdmadesc_phys, 0); 211 212 err = bus_dma_tag_create(bus_get_dma_tag(dev), 128, 0, 213 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 214 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 215 &sc->sc_rxdma_tag); 216 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 217 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 218 BUS_SPACE_MAXSIZE_32BIT, 16, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL, 219 &sc->sc_txdma_tag); 220 221 /* init transmit descriptors */ 222 STAILQ_INIT(&sc->sc_txfreeq); 223 STAILQ_INIT(&sc->sc_txdirtyq); 224 225 /* create TX DMA maps */ 226 err = ENOMEM; 227 for (i = 0; i < GLC_MAX_TX_PACKETS; i++) { 228 txs = &sc->sc_txsoft[i]; 229 txs->txs_mbuf = NULL; 230 err = bus_dmamap_create(sc->sc_txdma_tag, 0, &txs->txs_dmamap); 231 if (err) { 232 device_printf(dev, 233 "unable to create TX DMA map %d, error = %d\n", 234 i, err); 235 } 236 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 237 } 238 239 /* Create the receive buffer DMA maps. */ 240 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 241 err = bus_dmamap_create(sc->sc_rxdma_tag, 0, 242 &sc->sc_rxsoft[i].rxs_dmamap); 243 if (err) { 244 device_printf(dev, 245 "unable to create RX DMA map %d, error = %d\n", 246 i, err); 247 } 248 sc->sc_rxsoft[i].rxs_mbuf = NULL; 249 } 250 251 /* 252 * Attach to network stack 253 */ 254 255 if_initname(sc->sc_ifp, device_get_name(dev), device_get_unit(dev)); 256 if_setmtu(sc->sc_ifp, ETHERMTU); 257 if_setflags(sc->sc_ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 258 if_sethwassist(sc->sc_ifp, CSUM_TCP | CSUM_UDP); 259 if_setcapabilities(sc->sc_ifp, IFCAP_HWCSUM | IFCAP_RXCSUM); 260 if_setcapenable(sc->sc_ifp, IFCAP_HWCSUM | IFCAP_RXCSUM); 261 if_setstartfn(sc->sc_ifp, glc_start); 262 if_setioctlfn(sc->sc_ifp, glc_ioctl); 263 if_setinitfn(sc->sc_ifp, glc_init); 264 265 ifmedia_init(&sc->sc_media, IFM_IMASK, glc_media_change, 266 glc_media_status); 267 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 268 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 269 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 270 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 271 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 272 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 273 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 274 275 if_setsendqlen(sc->sc_ifp, GLC_MAX_TX_PACKETS); 276 if_setsendqready(sc->sc_ifp); 277 278 ether_ifattach(sc->sc_ifp, sc->sc_enaddr); 279 if_sethwassist(sc->sc_ifp, 0); 280 281 return (0); 282 283 mtx_destroy(&sc->sc_mtx); 284 if_free(sc->sc_ifp); 285 return (ENXIO); 286 } 287 288 static void 289 glc_init_locked(struct glc_softc *sc) 290 { 291 int i, error; 292 struct glc_rxsoft *rxs; 293 struct glc_txsoft *txs; 294 295 mtx_assert(&sc->sc_mtx, MA_OWNED); 296 297 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 298 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 299 300 glc_set_multicast(sc); 301 302 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) { 303 rxs = &sc->sc_rxsoft[i]; 304 rxs->rxs_desc_slot = i; 305 306 if (rxs->rxs_mbuf == NULL) { 307 glc_add_rxbuf(sc, i); 308 309 if (rxs->rxs_mbuf == NULL) { 310 rxs->rxs_desc_slot = -1; 311 break; 312 } 313 } 314 315 glc_add_rxbuf_dma(sc, i); 316 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 317 BUS_DMASYNC_PREREAD); 318 } 319 320 /* Clear TX dirty queue */ 321 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 322 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 323 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 324 325 if (txs->txs_mbuf != NULL) { 326 m_freem(txs->txs_mbuf); 327 txs->txs_mbuf = NULL; 328 } 329 330 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 331 } 332 sc->first_used_txdma_slot = -1; 333 sc->bsy_txdma_slots = 0; 334 335 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 336 sc->sc_rxsoft[0].rxs_desc, 0); 337 if (error != 0) 338 device_printf(sc->sc_self, 339 "lv1_net_start_rx_dma error: %d\n", error); 340 341 if_setdrvflagbits(sc->sc_ifp, IFF_DRV_RUNNING, 0); 342 if_setdrvflagbits(sc->sc_ifp, 0, IFF_DRV_OACTIVE); 343 sc->sc_ifpflags = if_getflags(sc->sc_ifp); 344 345 sc->sc_wdog_timer = 0; 346 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 347 } 348 349 static void 350 glc_stop(void *xsc) 351 { 352 struct glc_softc *sc = xsc; 353 354 mtx_assert(&sc->sc_mtx, MA_OWNED); 355 356 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 357 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0); 358 } 359 360 static void 361 glc_init(void *xsc) 362 { 363 struct glc_softc *sc = xsc; 364 365 mtx_lock(&sc->sc_mtx); 366 glc_init_locked(sc); 367 mtx_unlock(&sc->sc_mtx); 368 } 369 370 static void 371 glc_tick(void *xsc) 372 { 373 struct glc_softc *sc = xsc; 374 375 mtx_assert(&sc->sc_mtx, MA_OWNED); 376 377 /* 378 * XXX: Sometimes the RX queue gets stuck. Poke it periodically until 379 * we figure out why. This will fail harmlessly if the RX queue is 380 * already running. 381 */ 382 lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 383 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 384 385 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) { 386 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc); 387 return; 388 } 389 390 /* Problems */ 391 device_printf(sc->sc_self, "device timeout\n"); 392 393 glc_init_locked(sc); 394 } 395 396 static void 397 glc_start_locked(if_t ifp) 398 { 399 struct glc_softc *sc = if_getsoftc(ifp); 400 bus_addr_t first, pktdesc; 401 int kickstart = 0; 402 int error; 403 struct mbuf *mb_head; 404 405 mtx_assert(&sc->sc_mtx, MA_OWNED); 406 first = 0; 407 408 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 409 IFF_DRV_RUNNING) 410 return; 411 412 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 413 kickstart = 1; 414 415 while (!if_sendq_empty(ifp)) { 416 mb_head = if_dequeue(ifp); 417 418 if (mb_head == NULL) 419 break; 420 421 /* Check if the ring buffer is full */ 422 if (sc->bsy_txdma_slots > 125) { 423 /* Put the packet back and stop */ 424 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 425 if_sendq_prepend(ifp, mb_head); 426 break; 427 } 428 429 BPF_MTAP(ifp, mb_head); 430 431 if (sc->sc_tx_vlan >= 0) 432 mb_head = ether_vlanencap(mb_head, sc->sc_tx_vlan); 433 434 if (glc_encap(sc, &mb_head, &pktdesc)) { 435 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 436 break; 437 } 438 439 if (first == 0) 440 first = pktdesc; 441 } 442 443 if (kickstart && first != 0) { 444 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, first, 0); 445 if (error != 0) 446 device_printf(sc->sc_self, 447 "lv1_net_start_tx_dma error: %d\n", error); 448 sc->sc_wdog_timer = 5; 449 } 450 } 451 452 static void 453 glc_start(if_t ifp) 454 { 455 struct glc_softc *sc = if_getsoftc(ifp); 456 457 mtx_lock(&sc->sc_mtx); 458 glc_start_locked(ifp); 459 mtx_unlock(&sc->sc_mtx); 460 } 461 462 static int 463 glc_ioctl(if_t ifp, u_long cmd, caddr_t data) 464 { 465 struct glc_softc *sc = if_getsoftc(ifp); 466 struct ifreq *ifr = (struct ifreq *)data; 467 int err = 0; 468 469 switch (cmd) { 470 case SIOCSIFFLAGS: 471 mtx_lock(&sc->sc_mtx); 472 if ((if_getflags(ifp) & IFF_UP) != 0) { 473 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 474 ((if_getflags(ifp) ^ sc->sc_ifpflags) & 475 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 476 glc_set_multicast(sc); 477 else 478 glc_init_locked(sc); 479 } 480 else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 481 glc_stop(sc); 482 sc->sc_ifpflags = if_getflags(ifp); 483 mtx_unlock(&sc->sc_mtx); 484 break; 485 case SIOCADDMULTI: 486 case SIOCDELMULTI: 487 mtx_lock(&sc->sc_mtx); 488 glc_set_multicast(sc); 489 mtx_unlock(&sc->sc_mtx); 490 break; 491 case SIOCGIFMEDIA: 492 case SIOCSIFMEDIA: 493 err = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 494 break; 495 default: 496 err = ether_ioctl(ifp, cmd, data); 497 break; 498 } 499 500 return (err); 501 } 502 503 static u_int 504 glc_add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 505 { 506 struct glc_softc *sc = arg; 507 uint64_t addr; 508 509 /* 510 * Filter can only hold 32 addresses, so fall back to 511 * the IFF_ALLMULTI case if we have too many. +1 is for 512 * broadcast. 513 */ 514 if (cnt + 1 == 32) 515 return (0); 516 517 addr = 0; 518 memcpy(&((uint8_t *)(&addr))[2], LLADDR(sdl), ETHER_ADDR_LEN); 519 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, addr, 0); 520 521 return (1); 522 } 523 524 static void 525 glc_set_multicast(struct glc_softc *sc) 526 { 527 if_t ifp = sc->sc_ifp; 528 int naddrs; 529 530 /* Clear multicast filter */ 531 lv1_net_remove_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 532 533 /* Add broadcast */ 534 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 535 0xffffffffffffL, 0); 536 537 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 538 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1); 539 } else { 540 naddrs = if_foreach_llmaddr(ifp, glc_add_maddr, sc); 541 if (naddrs + 1 == 32) 542 lv1_net_add_multicast_address(sc->sc_bus, 543 sc->sc_dev, 0, 1); 544 } 545 } 546 547 static int 548 glc_add_rxbuf(struct glc_softc *sc, int idx) 549 { 550 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 551 struct mbuf *m; 552 bus_dma_segment_t segs[1]; 553 int error, nsegs; 554 555 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 556 if (m == NULL) 557 return (ENOBUFS); 558 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 559 560 if (rxs->rxs_mbuf != NULL) { 561 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, 562 BUS_DMASYNC_POSTREAD); 563 bus_dmamap_unload(sc->sc_rxdma_tag, rxs->rxs_dmamap); 564 } 565 566 error = bus_dmamap_load_mbuf_sg(sc->sc_rxdma_tag, rxs->rxs_dmamap, m, 567 segs, &nsegs, BUS_DMA_NOWAIT); 568 if (error != 0) { 569 device_printf(sc->sc_self, 570 "cannot load RS DMA map %d, error = %d\n", idx, error); 571 m_freem(m); 572 return (error); 573 } 574 /* If nsegs is wrong then the stack is corrupt. */ 575 KASSERT(nsegs == 1, 576 ("%s: too many DMA segments (%d)", __func__, nsegs)); 577 rxs->rxs_mbuf = m; 578 rxs->segment = segs[0]; 579 580 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD); 581 582 return (0); 583 } 584 585 static int 586 glc_add_rxbuf_dma(struct glc_softc *sc, int idx) 587 { 588 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx]; 589 590 bzero(&sc->sc_rxdmadesc[idx], sizeof(sc->sc_rxdmadesc[idx])); 591 sc->sc_rxdmadesc[idx].paddr = rxs->segment.ds_addr; 592 sc->sc_rxdmadesc[idx].len = rxs->segment.ds_len; 593 sc->sc_rxdmadesc[idx].next = sc->sc_rxdmadesc_phys + 594 ((idx + 1) % GLC_MAX_RX_PACKETS)*sizeof(sc->sc_rxdmadesc[idx]); 595 sc->sc_rxdmadesc[idx].cmd_stat = GELIC_DESCR_OWNED; 596 597 rxs->rxs_desc_slot = idx; 598 rxs->rxs_desc = sc->sc_rxdmadesc_phys + idx*sizeof(struct glc_dmadesc); 599 600 return (0); 601 } 602 603 static int 604 glc_encap(struct glc_softc *sc, struct mbuf **m_head, bus_addr_t *pktdesc) 605 { 606 bus_dma_segment_t segs[16]; 607 struct glc_txsoft *txs; 608 struct mbuf *m; 609 bus_addr_t firstslotphys; 610 int i, idx, nsegs, nsegs_max; 611 int err = 0; 612 613 /* Max number of segments is the number of free DMA slots */ 614 nsegs_max = 128 - sc->bsy_txdma_slots; 615 616 if (nsegs_max > 16 || sc->first_used_txdma_slot < 0) 617 nsegs_max = 16; 618 619 /* Get a work queue entry. */ 620 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 621 /* Ran out of descriptors. */ 622 return (ENOBUFS); 623 } 624 625 nsegs = 0; 626 for (m = *m_head; m != NULL; m = m->m_next) 627 nsegs++; 628 629 if (nsegs > nsegs_max) { 630 m = m_collapse(*m_head, M_NOWAIT, nsegs_max); 631 if (m == NULL) { 632 m_freem(*m_head); 633 *m_head = NULL; 634 return (ENOBUFS); 635 } 636 *m_head = m; 637 } 638 639 err = bus_dmamap_load_mbuf_sg(sc->sc_txdma_tag, txs->txs_dmamap, 640 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 641 if (err != 0) { 642 m_freem(*m_head); 643 *m_head = NULL; 644 return (err); 645 } 646 647 KASSERT(nsegs <= 128 - sc->bsy_txdma_slots, 648 ("GLC: Mapped too many (%d) DMA segments with %d available", 649 nsegs, 128 - sc->bsy_txdma_slots)); 650 651 if (nsegs == 0) { 652 m_freem(*m_head); 653 *m_head = NULL; 654 return (EIO); 655 } 656 657 txs->txs_ndescs = nsegs; 658 txs->txs_firstdesc = sc->next_txdma_slot; 659 660 idx = txs->txs_firstdesc; 661 firstslotphys = sc->sc_txdmadesc_phys + 662 txs->txs_firstdesc*sizeof(struct glc_dmadesc); 663 664 for (i = 0; i < nsegs; i++) { 665 bzero(&sc->sc_txdmadesc[idx], sizeof(sc->sc_txdmadesc[idx])); 666 sc->sc_txdmadesc[idx].paddr = segs[i].ds_addr; 667 sc->sc_txdmadesc[idx].len = segs[i].ds_len; 668 sc->sc_txdmadesc[idx].next = sc->sc_txdmadesc_phys + 669 ((idx + 1) % GLC_MAX_TX_PACKETS)*sizeof(struct glc_dmadesc); 670 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_NOIPSEC; 671 672 if (i+1 == nsegs) { 673 txs->txs_lastdesc = idx; 674 sc->sc_txdmadesc[idx].next = 0; 675 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_LAST; 676 } 677 678 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 679 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_TCP; 680 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 681 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_UDP; 682 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_DESCR_OWNED; 683 684 idx = (idx + 1) % GLC_MAX_TX_PACKETS; 685 } 686 sc->next_txdma_slot = idx; 687 sc->bsy_txdma_slots += nsegs; 688 if (txs->txs_firstdesc != 0) 689 idx = txs->txs_firstdesc - 1; 690 else 691 idx = GLC_MAX_TX_PACKETS - 1; 692 693 if (sc->first_used_txdma_slot < 0) 694 sc->first_used_txdma_slot = txs->txs_firstdesc; 695 696 bus_dmamap_sync(sc->sc_txdma_tag, txs->txs_dmamap, 697 BUS_DMASYNC_PREWRITE); 698 sc->sc_txdmadesc[idx].next = firstslotphys; 699 700 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 701 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 702 txs->txs_mbuf = *m_head; 703 *pktdesc = firstslotphys; 704 705 return (0); 706 } 707 708 static void 709 glc_rxintr(struct glc_softc *sc) 710 { 711 int i, restart_rxdma, error; 712 struct mbuf *m; 713 if_t ifp = sc->sc_ifp; 714 715 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 716 BUS_DMASYNC_POSTREAD); 717 718 restart_rxdma = 0; 719 while ((sc->sc_rxdmadesc[sc->sc_next_rxdma_slot].cmd_stat & 720 GELIC_DESCR_OWNED) == 0) { 721 i = sc->sc_next_rxdma_slot; 722 sc->sc_next_rxdma_slot++; 723 if (sc->sc_next_rxdma_slot >= GLC_MAX_RX_PACKETS) 724 sc->sc_next_rxdma_slot = 0; 725 726 if (sc->sc_rxdmadesc[i].cmd_stat & GELIC_CMDSTAT_CHAIN_END) 727 restart_rxdma = 1; 728 729 if (sc->sc_rxdmadesc[i].rxerror & GELIC_RXERRORS) { 730 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 731 goto requeue; 732 } 733 734 m = sc->sc_rxsoft[i].rxs_mbuf; 735 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_IPCSUM) { 736 m->m_pkthdr.csum_flags |= 737 CSUM_IP_CHECKED | CSUM_IP_VALID; 738 } 739 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_TCPUDPCSUM) { 740 m->m_pkthdr.csum_flags |= 741 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 742 m->m_pkthdr.csum_data = 0xffff; 743 } 744 745 if (glc_add_rxbuf(sc, i)) { 746 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 747 goto requeue; 748 } 749 750 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 751 m->m_pkthdr.rcvif = ifp; 752 m->m_len = sc->sc_rxdmadesc[i].valid_size; 753 m->m_pkthdr.len = m->m_len; 754 755 /* 756 * Remove VLAN tag. Even on early firmwares that do not allow 757 * multiple VLANs, the VLAN tag is still in place here. 758 */ 759 m_adj(m, 2); 760 761 mtx_unlock(&sc->sc_mtx); 762 if_input(ifp, m); 763 mtx_lock(&sc->sc_mtx); 764 765 requeue: 766 glc_add_rxbuf_dma(sc, i); 767 } 768 769 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map, 770 BUS_DMASYNC_PREWRITE); 771 772 if (restart_rxdma) { 773 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev, 774 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0); 775 if (error != 0) 776 device_printf(sc->sc_self, 777 "lv1_net_start_rx_dma error: %d\n", error); 778 } 779 } 780 781 static void 782 glc_txintr(struct glc_softc *sc) 783 { 784 if_t ifp = sc->sc_ifp; 785 struct glc_txsoft *txs; 786 int progress = 0, kickstart = 0, error; 787 788 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map, 789 BUS_DMASYNC_POSTREAD); 790 791 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 792 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat 793 & GELIC_DESCR_OWNED) 794 break; 795 796 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 797 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap); 798 sc->bsy_txdma_slots -= txs->txs_ndescs; 799 800 if (txs->txs_mbuf != NULL) { 801 m_freem(txs->txs_mbuf); 802 txs->txs_mbuf = NULL; 803 } 804 805 if ((sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 0xf0000000) 806 != 0) { 807 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0); 808 kickstart = 1; 809 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 810 } 811 812 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 813 GELIC_CMDSTAT_CHAIN_END) 814 kickstart = 1; 815 816 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 817 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 818 progress = 1; 819 } 820 821 if (txs != NULL) 822 sc->first_used_txdma_slot = txs->txs_firstdesc; 823 else 824 sc->first_used_txdma_slot = -1; 825 826 if (kickstart || txs != NULL) { 827 /* Speculatively (or necessarily) start the TX queue again */ 828 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, 829 sc->sc_txdmadesc_phys + 830 ((txs == NULL) ? 0 : txs->txs_firstdesc)* 831 sizeof(struct glc_dmadesc), 0); 832 if (error != 0) 833 device_printf(sc->sc_self, 834 "lv1_net_start_tx_dma error: %d\n", error); 835 } 836 837 if (progress) { 838 /* 839 * We freed some descriptors, so reset IFF_DRV_OACTIVE 840 * and restart. 841 */ 842 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 843 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 844 845 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) && 846 !if_sendq_empty(ifp)) 847 glc_start_locked(ifp); 848 } 849 } 850 851 static int 852 glc_intr_filter(void *xsc) 853 { 854 struct glc_softc *sc = xsc; 855 856 powerpc_sync(); 857 atomic_set_64(&sc->sc_interrupt_status, *sc->sc_hwirq_status); 858 return (FILTER_SCHEDULE_THREAD); 859 } 860 861 static void 862 glc_intr(void *xsc) 863 { 864 struct glc_softc *sc = xsc; 865 uint64_t status, linkstat, junk; 866 867 mtx_lock(&sc->sc_mtx); 868 869 status = atomic_readandclear_64(&sc->sc_interrupt_status); 870 871 if (status == 0) { 872 mtx_unlock(&sc->sc_mtx); 873 return; 874 } 875 876 if (status & (GELIC_INT_RXDONE | GELIC_INT_RXFRAME)) 877 glc_rxintr(sc); 878 879 if (status & (GELIC_INT_TXDONE | GELIC_INT_TX_CHAIN_END)) 880 glc_txintr(sc); 881 882 if (status & GELIC_INT_PHY) { 883 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 884 GELIC_VLAN_TX_ETHERNET, 0, 0, &linkstat, &junk); 885 886 linkstat = (linkstat & GELIC_LINK_UP) ? 887 LINK_STATE_UP : LINK_STATE_DOWN; 888 if_link_state_change(sc->sc_ifp, linkstat); 889 } 890 891 mtx_unlock(&sc->sc_mtx); 892 } 893 894 static void 895 glc_media_status(if_t ifp, struct ifmediareq *ifmr) 896 { 897 struct glc_softc *sc = if_getsoftc(ifp); 898 uint64_t status, junk; 899 900 ifmr->ifm_status = IFM_AVALID; 901 ifmr->ifm_active = IFM_ETHER; 902 903 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS, 904 GELIC_VLAN_TX_ETHERNET, 0, 0, &status, &junk); 905 906 if (status & GELIC_LINK_UP) 907 ifmr->ifm_status |= IFM_ACTIVE; 908 909 if (status & GELIC_SPEED_10) 910 ifmr->ifm_active |= IFM_10_T; 911 else if (status & GELIC_SPEED_100) 912 ifmr->ifm_active |= IFM_100_TX; 913 else if (status & GELIC_SPEED_1000) 914 ifmr->ifm_active |= IFM_1000_T; 915 916 if (status & GELIC_FULL_DUPLEX) 917 ifmr->ifm_active |= IFM_FDX; 918 else 919 ifmr->ifm_active |= IFM_HDX; 920 } 921 922 static int 923 glc_media_change(if_t ifp) 924 { 925 struct glc_softc *sc = if_getsoftc(ifp); 926 uint64_t mode, junk; 927 int result; 928 929 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 930 return (EINVAL); 931 932 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) { 933 case IFM_AUTO: 934 mode = GELIC_AUTO_NEG; 935 break; 936 case IFM_10_T: 937 mode = GELIC_SPEED_10; 938 break; 939 case IFM_100_TX: 940 mode = GELIC_SPEED_100; 941 break; 942 case IFM_1000_T: 943 mode = GELIC_SPEED_1000 | GELIC_FULL_DUPLEX; 944 break; 945 default: 946 return (EINVAL); 947 } 948 949 if (IFM_OPTIONS(sc->sc_media.ifm_media) & IFM_FDX) 950 mode |= GELIC_FULL_DUPLEX; 951 952 result = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_SET_LINK_MODE, 953 GELIC_VLAN_TX_ETHERNET, mode, 0, &junk, &junk); 954 955 return (result ? EIO : 0); 956 } 957