1/*- 2 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35#include <machine/asm.h> 36__FBSDID("$FreeBSD$"); 37 38#include "assym.inc" 39 40#include <machine/trap.h> 41#include <machine/riscvreg.h> 42 43.macro save_registers mode 44 addi sp, sp, -(TF_SIZE) 45 46 sd ra, (TF_RA)(sp) 47 48.if \mode == 0 /* We came from userspace. */ 49 sd gp, (TF_GP)(sp) 50.option push 51.option norelax 52 /* Load the kernel's global pointer */ 53 la gp, __global_pointer$ 54.option pop 55 56 /* Load our pcpu */ 57 sd tp, (TF_TP)(sp) 58 ld tp, (TF_SIZE)(sp) 59.else 60 sd tp, (TF_TP)(sp) 61.endif 62 63 sd t0, (TF_T + 0 * 8)(sp) 64 sd t1, (TF_T + 1 * 8)(sp) 65 sd t2, (TF_T + 2 * 8)(sp) 66 sd t3, (TF_T + 3 * 8)(sp) 67 sd t4, (TF_T + 4 * 8)(sp) 68 sd t5, (TF_T + 5 * 8)(sp) 69 sd t6, (TF_T + 6 * 8)(sp) 70 71 sd s0, (TF_S + 0 * 8)(sp) 72 sd s1, (TF_S + 1 * 8)(sp) 73 sd s2, (TF_S + 2 * 8)(sp) 74 sd s3, (TF_S + 3 * 8)(sp) 75 sd s4, (TF_S + 4 * 8)(sp) 76 sd s5, (TF_S + 5 * 8)(sp) 77 sd s6, (TF_S + 6 * 8)(sp) 78 sd s7, (TF_S + 7 * 8)(sp) 79 sd s8, (TF_S + 8 * 8)(sp) 80 sd s9, (TF_S + 9 * 8)(sp) 81 sd s10, (TF_S + 10 * 8)(sp) 82 sd s11, (TF_S + 11 * 8)(sp) 83 84 sd a0, (TF_A + 0 * 8)(sp) 85 sd a1, (TF_A + 1 * 8)(sp) 86 sd a2, (TF_A + 2 * 8)(sp) 87 sd a3, (TF_A + 3 * 8)(sp) 88 sd a4, (TF_A + 4 * 8)(sp) 89 sd a5, (TF_A + 5 * 8)(sp) 90 sd a6, (TF_A + 6 * 8)(sp) 91 sd a7, (TF_A + 7 * 8)(sp) 92 93.if \mode == 1 94 /* Store kernel sp */ 95 li t1, TF_SIZE 96 add t0, sp, t1 97 sd t0, (TF_SP)(sp) 98.else 99 /* Store user sp */ 100 csrr t0, sscratch 101 sd t0, (TF_SP)(sp) 102.endif 103 li t0, 0 104 csrw sscratch, t0 105 csrr t0, sepc 106 sd t0, (TF_SEPC)(sp) 107 csrr t0, sstatus 108 sd t0, (TF_SSTATUS)(sp) 109.if \mode == 1 110 /* Disable user address access for supervisor mode exceptions. */ 111 li t0, SSTATUS_SUM 112 csrc sstatus, t0 113.endif 114 csrr t0, stval 115 sd t0, (TF_STVAL)(sp) 116 csrr t0, scause 117 sd t0, (TF_SCAUSE)(sp) 118.endm 119 120.macro load_registers mode 121 ld t0, (TF_SSTATUS)(sp) 122.if \mode == 0 123 /* Ensure user interrupts will be enabled on eret */ 124 li t1, SSTATUS_SPIE 125 or t0, t0, t1 126.else 127 /* 128 * Disable interrupts for supervisor mode exceptions. 129 * For user mode exceptions we have already done this 130 * in do_ast. 131 */ 132 li t1, ~SSTATUS_SIE 133 and t0, t0, t1 134.endif 135 csrw sstatus, t0 136 137 ld t0, (TF_SEPC)(sp) 138 csrw sepc, t0 139 140.if \mode == 0 141 /* We go to userspace. Load user sp */ 142 ld t0, (TF_SP)(sp) 143 csrw sscratch, t0 144 145 /* Store our pcpu */ 146 sd tp, (TF_SIZE)(sp) 147 ld tp, (TF_TP)(sp) 148 149 /* And restore the user's global pointer */ 150 ld gp, (TF_GP)(sp) 151.endif 152 153 ld ra, (TF_RA)(sp) 154 155 ld t0, (TF_T + 0 * 8)(sp) 156 ld t1, (TF_T + 1 * 8)(sp) 157 ld t2, (TF_T + 2 * 8)(sp) 158 ld t3, (TF_T + 3 * 8)(sp) 159 ld t4, (TF_T + 4 * 8)(sp) 160 ld t5, (TF_T + 5 * 8)(sp) 161 ld t6, (TF_T + 6 * 8)(sp) 162 163 ld s0, (TF_S + 0 * 8)(sp) 164 ld s1, (TF_S + 1 * 8)(sp) 165 ld s2, (TF_S + 2 * 8)(sp) 166 ld s3, (TF_S + 3 * 8)(sp) 167 ld s4, (TF_S + 4 * 8)(sp) 168 ld s5, (TF_S + 5 * 8)(sp) 169 ld s6, (TF_S + 6 * 8)(sp) 170 ld s7, (TF_S + 7 * 8)(sp) 171 ld s8, (TF_S + 8 * 8)(sp) 172 ld s9, (TF_S + 9 * 8)(sp) 173 ld s10, (TF_S + 10 * 8)(sp) 174 ld s11, (TF_S + 11 * 8)(sp) 175 176 ld a0, (TF_A + 0 * 8)(sp) 177 ld a1, (TF_A + 1 * 8)(sp) 178 ld a2, (TF_A + 2 * 8)(sp) 179 ld a3, (TF_A + 3 * 8)(sp) 180 ld a4, (TF_A + 4 * 8)(sp) 181 ld a5, (TF_A + 5 * 8)(sp) 182 ld a6, (TF_A + 6 * 8)(sp) 183 ld a7, (TF_A + 7 * 8)(sp) 184 185 addi sp, sp, (TF_SIZE) 186.endm 187 188.macro do_ast 189 /* Disable interrupts */ 190 csrr a4, sstatus 1911: 192 csrci sstatus, (SSTATUS_SIE) 193 194 ld a1, PC_CURTHREAD(tp) 195 lw a2, TD_AST(a1) 196 197 beqz a2, 2f 198 199 /* Restore interrupts */ 200 andi a4, a4, (SSTATUS_SIE) 201 csrs sstatus, a4 202 203 /* Handle the ast */ 204 mv a0, sp 205 call _C_LABEL(ast) 206 207 /* Re-check for new ast scheduled */ 208 j 1b 2092: 210.endm 211 212ENTRY(cpu_exception_handler) 213 csrrw sp, sscratch, sp 214 beqz sp, 1f 215 /* User mode detected */ 216 j cpu_exception_handler_user 2171: 218 /* Supervisor mode detected */ 219 csrrw sp, sscratch, sp 220 j cpu_exception_handler_supervisor 221END(cpu_exception_handler) 222 223ENTRY(cpu_exception_handler_supervisor) 224 save_registers 1 225 mv a0, sp 226 call _C_LABEL(do_trap_supervisor) 227 load_registers 1 228 sret 229END(cpu_exception_handler_supervisor) 230 231ENTRY(cpu_exception_handler_user) 232 save_registers 0 233 mv a0, sp 234 call _C_LABEL(do_trap_user) 235 do_ast 236 load_registers 0 237 csrrw sp, sscratch, sp 238 sret 239END(cpu_exception_handler_user) 240