1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> 5 * All rights reserved. 6 * Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org> 7 * 8 * Portions of this software were developed by SRI International and the 9 * University of Cambridge Computer Laboratory (Department of Computer Science 10 * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of 11 * the DARPA SSITH research programme. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/ktr.h> 40 #include <sys/module.h> 41 #include <sys/proc.h> 42 #include <sys/rman.h> 43 #include <sys/smp.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "pic_if.h" 53 54 #define PLIC_MAX_IRQS 1024 55 56 #define PLIC_PRIORITY_BASE 0x000000U 57 58 #define PLIC_ENABLE_BASE 0x002000U 59 #define PLIC_ENABLE_STRIDE 0x80U 60 61 #define PLIC_CONTEXT_BASE 0x200000U 62 #define PLIC_CONTEXT_STRIDE 0x1000U 63 #define PLIC_CONTEXT_THRESHOLD 0x0U 64 #define PLIC_CONTEXT_CLAIM 0x4U 65 66 #define PLIC_PRIORITY(n) (PLIC_PRIORITY_BASE + (n) * sizeof(uint32_t)) 67 #define PLIC_ENABLE(sc, n, h) \ 68 (sc->contexts[h].enable_offset + ((n) / 32) * sizeof(uint32_t)) 69 #define PLIC_THRESHOLD(sc, h) \ 70 (sc->contexts[h].context_offset + PLIC_CONTEXT_THRESHOLD) 71 #define PLIC_CLAIM(sc, h) \ 72 (sc->contexts[h].context_offset + PLIC_CONTEXT_CLAIM) 73 74 static pic_disable_intr_t plic_disable_intr; 75 static pic_enable_intr_t plic_enable_intr; 76 static pic_map_intr_t plic_map_intr; 77 static pic_setup_intr_t plic_setup_intr; 78 static pic_post_ithread_t plic_post_ithread; 79 static pic_pre_ithread_t plic_pre_ithread; 80 static pic_bind_intr_t plic_bind_intr; 81 82 struct plic_irqsrc { 83 struct intr_irqsrc isrc; 84 u_int irq; 85 }; 86 87 struct plic_context { 88 bus_size_t enable_offset; 89 bus_size_t context_offset; 90 }; 91 92 struct plic_softc { 93 device_t dev; 94 struct resource * intc_res; 95 struct plic_irqsrc isrcs[PLIC_MAX_IRQS]; 96 struct plic_context contexts[MAXCPU]; 97 int ndev; 98 }; 99 100 #define RD4(sc, reg) \ 101 bus_read_4(sc->intc_res, (reg)) 102 #define WR4(sc, reg, val) \ 103 bus_write_4(sc->intc_res, (reg), (val)) 104 105 static u_int plic_irq_cpu; 106 107 static int 108 riscv_hartid_to_cpu(int hartid) 109 { 110 int i; 111 112 CPU_FOREACH(i) { 113 if (pcpu_find(i)->pc_hart == hartid) 114 return (i); 115 } 116 117 return (-1); 118 } 119 120 static int 121 plic_get_hartid(device_t dev, phandle_t intc) 122 { 123 int hart; 124 125 /* Check the interrupt controller layout. */ 126 if (OF_searchencprop(intc, "#interrupt-cells", &hart, 127 sizeof(hart)) == -1) { 128 device_printf(dev, 129 "Could not find #interrupt-cells for phandle %u\n", intc); 130 return (-1); 131 } 132 133 /* 134 * The parent of the interrupt-controller is the CPU we are 135 * interested in, so search for its hart ID. 136 */ 137 if (OF_searchencprop(OF_parent(intc), "reg", (pcell_t *)&hart, 138 sizeof(hart)) == -1) { 139 device_printf(dev, "Could not find hartid\n"); 140 return (-1); 141 } 142 143 return (hart); 144 } 145 146 static inline void 147 plic_irq_dispatch(struct plic_softc *sc, u_int irq, 148 struct trapframe *tf) 149 { 150 struct plic_irqsrc *src; 151 152 src = &sc->isrcs[irq]; 153 154 if (intr_isrc_dispatch(&src->isrc, tf) != 0) 155 device_printf(sc->dev, "Stray irq %u detected\n", irq); 156 } 157 158 static int 159 plic_intr(void *arg) 160 { 161 struct plic_softc *sc; 162 struct trapframe *tf; 163 uint32_t pending; 164 uint32_t cpu; 165 166 sc = arg; 167 cpu = PCPU_GET(cpuid); 168 169 /* Claim any pending interrupt. */ 170 pending = RD4(sc, PLIC_CLAIM(sc, cpu)); 171 if (pending) { 172 tf = curthread->td_intr_frame; 173 plic_irq_dispatch(sc, pending, tf); 174 } 175 176 return (FILTER_HANDLED); 177 } 178 179 static void 180 plic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 181 { 182 struct plic_softc *sc; 183 struct plic_irqsrc *src; 184 185 sc = device_get_softc(dev); 186 src = (struct plic_irqsrc *)isrc; 187 188 WR4(sc, PLIC_PRIORITY(src->irq), 0); 189 } 190 191 static void 192 plic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 193 { 194 struct plic_softc *sc; 195 struct plic_irqsrc *src; 196 197 sc = device_get_softc(dev); 198 src = (struct plic_irqsrc *)isrc; 199 200 WR4(sc, PLIC_PRIORITY(src->irq), 1); 201 } 202 203 static int 204 plic_map_intr(device_t dev, struct intr_map_data *data, 205 struct intr_irqsrc **isrcp) 206 { 207 struct intr_map_data_fdt *daf; 208 struct plic_softc *sc; 209 210 sc = device_get_softc(dev); 211 212 if (data->type != INTR_MAP_DATA_FDT) 213 return (ENOTSUP); 214 215 daf = (struct intr_map_data_fdt *)data; 216 if (daf->ncells != 1 || daf->cells[0] > sc->ndev) 217 return (EINVAL); 218 219 *isrcp = &sc->isrcs[daf->cells[0]].isrc; 220 221 return (0); 222 } 223 224 static int 225 plic_probe(device_t dev) 226 { 227 228 if (!ofw_bus_status_okay(dev)) 229 return (ENXIO); 230 231 if (!ofw_bus_is_compatible(dev, "riscv,plic0") && 232 !ofw_bus_is_compatible(dev, "sifive,plic-1.0.0")) 233 return (ENXIO); 234 235 device_set_desc(dev, "RISC-V PLIC"); 236 237 return (BUS_PROBE_DEFAULT); 238 } 239 240 static int 241 plic_attach(device_t dev) 242 { 243 struct plic_irqsrc *isrcs; 244 struct plic_softc *sc; 245 struct intr_pic *pic; 246 pcell_t *cells; 247 uint32_t irq; 248 const char *name; 249 phandle_t node; 250 phandle_t xref; 251 uint32_t cpu; 252 int error; 253 int rid; 254 int nintr; 255 int context; 256 int i; 257 int hart; 258 259 sc = device_get_softc(dev); 260 261 sc->dev = dev; 262 263 node = ofw_bus_get_node(dev); 264 if ((OF_getencprop(node, "riscv,ndev", &sc->ndev, 265 sizeof(sc->ndev))) < 0) { 266 device_printf(dev, 267 "Error: could not get number of devices\n"); 268 return (ENXIO); 269 } 270 271 if (sc->ndev >= PLIC_MAX_IRQS) { 272 device_printf(dev, 273 "Error: invalid ndev (%d)\n", sc->ndev); 274 return (ENXIO); 275 } 276 277 /* Request memory resources */ 278 rid = 0; 279 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 280 RF_ACTIVE); 281 if (sc->intc_res == NULL) { 282 device_printf(dev, 283 "Error: could not allocate memory resources\n"); 284 return (ENXIO); 285 } 286 287 /* Register the interrupt sources */ 288 isrcs = sc->isrcs; 289 name = device_get_nameunit(sc->dev); 290 for (irq = 1; irq <= sc->ndev; irq++) { 291 isrcs[irq].irq = irq; 292 error = intr_isrc_register(&isrcs[irq].isrc, sc->dev, 293 0, "%s,%u", name, irq); 294 if (error != 0) 295 return (error); 296 297 WR4(sc, PLIC_PRIORITY(irq), 0); 298 } 299 300 /* 301 * Calculate the per-cpu enable and context register offsets. 302 * 303 * This is tricky for a few reasons. The PLIC divides the interrupt 304 * enable, threshold, and claim bits by "context", where each context 305 * routes to a Core-Local Interrupt Controller (CLIC). 306 * 307 * The tricky part is that the PLIC spec imposes no restrictions on how 308 * these contexts are laid out. So for example, there is no guarantee 309 * that each CPU will have both a machine mode and supervisor context, 310 * or that different PLIC implementations will organize the context 311 * registers in the same way. On top of this, we must handle the fact 312 * that cpuid != hartid, as they may have been renumbered during boot. 313 * We perform the following steps: 314 * 315 * 1. Examine the PLIC's "interrupts-extended" property and skip any 316 * entries that are not for supervisor external interrupts. 317 * 318 * 2. Walk up the device tree to find the corresponding CPU, and grab 319 * it's hart ID. 320 * 321 * 3. Convert the hart to a cpuid, and calculate the register offsets 322 * based on the context number. 323 */ 324 nintr = OF_getencprop_alloc_multi(node, "interrupts-extended", 325 sizeof(uint32_t), (void **)&cells); 326 if (nintr <= 0) { 327 device_printf(dev, "Could not read interrupts-extended\n"); 328 return (ENXIO); 329 } 330 331 /* interrupts-extended is a list of phandles and interrupt types. */ 332 for (i = 0, context = 0; i < nintr; i += 2, context++) { 333 /* Skip M-mode external interrupts */ 334 if (cells[i + 1] != IRQ_EXTERNAL_SUPERVISOR) 335 continue; 336 337 /* Get the hart ID from the CLIC's phandle. */ 338 hart = plic_get_hartid(dev, OF_node_from_xref(cells[i])); 339 if (hart < 0) { 340 OF_prop_free(cells); 341 return (ENXIO); 342 } 343 344 /* Get the corresponding cpuid. */ 345 cpu = riscv_hartid_to_cpu(hart); 346 if (cpu < 0) { 347 device_printf(dev, "Invalid hart!\n"); 348 OF_prop_free(cells); 349 return (ENXIO); 350 } 351 352 /* Set the enable and context register offsets for the CPU. */ 353 sc->contexts[cpu].enable_offset = PLIC_ENABLE_BASE + 354 context * PLIC_ENABLE_STRIDE; 355 sc->contexts[cpu].context_offset = PLIC_CONTEXT_BASE + 356 context * PLIC_CONTEXT_STRIDE; 357 } 358 OF_prop_free(cells); 359 360 /* Set the threshold for each CPU to accept all priorities. */ 361 CPU_FOREACH(cpu) 362 WR4(sc, PLIC_THRESHOLD(sc, cpu), 0); 363 364 xref = OF_xref_from_node(node); 365 pic = intr_pic_register(sc->dev, xref); 366 if (pic == NULL) 367 return (ENXIO); 368 369 csr_set(sie, SIE_SEIE); 370 371 return (intr_pic_claim_root(sc->dev, xref, plic_intr, sc)); 372 } 373 374 static void 375 plic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 376 { 377 378 plic_disable_intr(dev, isrc); 379 } 380 381 static void 382 plic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 383 { 384 struct plic_softc *sc; 385 struct plic_irqsrc *src; 386 uint32_t cpu; 387 388 sc = device_get_softc(dev); 389 src = (struct plic_irqsrc *)isrc; 390 391 cpu = CPU_FFS(&isrc->isrc_cpu) - 1; 392 393 /* Complete the interrupt. */ 394 WR4(sc, PLIC_CLAIM(sc, cpu), src->irq); 395 plic_enable_intr(dev, isrc); 396 } 397 398 static int 399 plic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 400 struct resource *res, struct intr_map_data *data) 401 { 402 CPU_ZERO(&isrc->isrc_cpu); 403 plic_bind_intr(dev, isrc); 404 405 return (0); 406 } 407 408 static int 409 plic_bind_intr(device_t dev, struct intr_irqsrc *isrc) 410 { 411 struct plic_softc *sc; 412 struct plic_irqsrc *src; 413 uint32_t reg; 414 u_int cpu; 415 416 sc = device_get_softc(dev); 417 src = (struct plic_irqsrc *)isrc; 418 419 /* Disable the interrupt source on all CPUs. */ 420 CPU_FOREACH(cpu) { 421 reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu)); 422 reg &= ~(1 << (src->irq % 32)); 423 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg); 424 } 425 426 if (CPU_EMPTY(&isrc->isrc_cpu)) { 427 cpu = plic_irq_cpu = intr_irq_next_cpu(plic_irq_cpu, &all_cpus); 428 CPU_SETOF(cpu, &isrc->isrc_cpu); 429 } else { 430 /* 431 * We will only bind to a single CPU so select the first 432 * CPU found. 433 */ 434 cpu = CPU_FFS(&isrc->isrc_cpu) - 1; 435 } 436 437 /* Enable the interrupt on the selected CPU only. */ 438 reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu)); 439 reg |= (1 << (src->irq % 32)); 440 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg); 441 442 return (0); 443 } 444 445 static device_method_t plic_methods[] = { 446 DEVMETHOD(device_probe, plic_probe), 447 DEVMETHOD(device_attach, plic_attach), 448 449 DEVMETHOD(pic_disable_intr, plic_disable_intr), 450 DEVMETHOD(pic_enable_intr, plic_enable_intr), 451 DEVMETHOD(pic_map_intr, plic_map_intr), 452 DEVMETHOD(pic_pre_ithread, plic_pre_ithread), 453 DEVMETHOD(pic_post_ithread, plic_post_ithread), 454 DEVMETHOD(pic_post_filter, plic_post_ithread), 455 DEVMETHOD(pic_setup_intr, plic_setup_intr), 456 DEVMETHOD(pic_bind_intr, plic_bind_intr), 457 458 DEVMETHOD_END 459 }; 460 461 static driver_t plic_driver = { 462 "plic", 463 plic_methods, 464 sizeof(struct plic_softc), 465 }; 466 467 EARLY_DRIVER_MODULE(plic, simplebus, plic_driver, 0, 0, 468 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 469