128029b68SRuslan Bukin /*-
2af19cc59SRuslan Bukin * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
328029b68SRuslan Bukin * All rights reserved.
428029b68SRuslan Bukin *
528029b68SRuslan Bukin * Portions of this software were developed by SRI International and the
628029b68SRuslan Bukin * University of Cambridge Computer Laboratory under DARPA/AFRL contract
728029b68SRuslan Bukin * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
828029b68SRuslan Bukin *
928029b68SRuslan Bukin * Portions of this software were developed by the University of Cambridge
1028029b68SRuslan Bukin * Computer Laboratory as part of the CTSRD Project, with support from the
1128029b68SRuslan Bukin * UK Higher Education Innovation Fund (HEIF).
1228029b68SRuslan Bukin *
1328029b68SRuslan Bukin * Redistribution and use in source and binary forms, with or without
1428029b68SRuslan Bukin * modification, are permitted provided that the following conditions
1528029b68SRuslan Bukin * are met:
1628029b68SRuslan Bukin * 1. Redistributions of source code must retain the above copyright
1728029b68SRuslan Bukin * notice, this list of conditions and the following disclaimer.
1828029b68SRuslan Bukin * 2. Redistributions in binary form must reproduce the above copyright
1928029b68SRuslan Bukin * notice, this list of conditions and the following disclaimer in the
2028029b68SRuslan Bukin * documentation and/or other materials provided with the distribution.
2128029b68SRuslan Bukin *
2228029b68SRuslan Bukin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
2328029b68SRuslan Bukin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2428029b68SRuslan Bukin * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2528029b68SRuslan Bukin * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
2628029b68SRuslan Bukin * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2728029b68SRuslan Bukin * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2828029b68SRuslan Bukin * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2928029b68SRuslan Bukin * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
3028029b68SRuslan Bukin * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
3128029b68SRuslan Bukin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
3228029b68SRuslan Bukin * SUCH DAMAGE.
3328029b68SRuslan Bukin */
3428029b68SRuslan Bukin
3528029b68SRuslan Bukin /*
3628029b68SRuslan Bukin * RISC-V Timer
3728029b68SRuslan Bukin */
3828029b68SRuslan Bukin
3928029b68SRuslan Bukin #include "opt_platform.h"
4028029b68SRuslan Bukin
4128029b68SRuslan Bukin #include <sys/param.h>
4228029b68SRuslan Bukin #include <sys/systm.h>
4328029b68SRuslan Bukin #include <sys/bus.h>
4428029b68SRuslan Bukin #include <sys/kernel.h>
4528029b68SRuslan Bukin #include <sys/module.h>
466ec8bf9fSJessica Clarke #include <sys/rman.h>
4728029b68SRuslan Bukin #include <sys/timeet.h>
4828029b68SRuslan Bukin #include <sys/timetc.h>
49348c41d1SJessica Clarke #include <sys/vdso.h>
5028029b68SRuslan Bukin #include <sys/watchdog.h>
5128029b68SRuslan Bukin
52d2b6a2ffSMitchell Horne #include <machine/cpufunc.h>
5328029b68SRuslan Bukin #include <machine/intr.h>
54cadaabccSMitchell Horne #include <machine/md_var.h>
555f8228b2SRuslan Bukin #include <machine/sbi.h>
5628029b68SRuslan Bukin
576ec8bf9fSJessica Clarke #include <dev/ofw/ofw_bus.h>
5861fef9e8SRuslan Bukin #include <dev/ofw/openfirm.h>
5928029b68SRuslan Bukin
60af19cc59SRuslan Bukin struct riscv_timer_softc {
616ec8bf9fSJessica Clarke struct resource *irq_res;
6298f50c44SRuslan Bukin void *ih;
6328029b68SRuslan Bukin uint32_t clkfreq;
6428029b68SRuslan Bukin struct eventtimer et;
6528029b68SRuslan Bukin };
66af19cc59SRuslan Bukin static struct riscv_timer_softc *riscv_timer_sc = NULL;
6728029b68SRuslan Bukin
68715276a0SMitchell Horne static timecounter_get_t riscv_timer_tc_get_timecount;
69715276a0SMitchell Horne static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands;
7028029b68SRuslan Bukin
71af19cc59SRuslan Bukin static struct timecounter riscv_timer_timecount = {
7228029b68SRuslan Bukin .tc_name = "RISC-V Timecounter",
73715276a0SMitchell Horne .tc_get_timecount = riscv_timer_tc_get_timecount,
7428029b68SRuslan Bukin .tc_poll_pps = NULL,
7528029b68SRuslan Bukin .tc_counter_mask = ~0u,
7628029b68SRuslan Bukin .tc_frequency = 0,
7728029b68SRuslan Bukin .tc_quality = 1000,
78715276a0SMitchell Horne .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands,
7928029b68SRuslan Bukin };
8028029b68SRuslan Bukin
81af19cc59SRuslan Bukin static inline uint64_t
get_timecount(void)82b82f4170SMitchell Horne get_timecount(void)
83af19cc59SRuslan Bukin {
84af19cc59SRuslan Bukin
85d2b6a2ffSMitchell Horne return (rdtime());
86af19cc59SRuslan Bukin }
87af19cc59SRuslan Bukin
88cadaabccSMitchell Horne static inline void
set_timecmp(uint64_t timecmp)89cadaabccSMitchell Horne set_timecmp(uint64_t timecmp)
90cadaabccSMitchell Horne {
91cadaabccSMitchell Horne
92cadaabccSMitchell Horne if (has_sstc)
93cadaabccSMitchell Horne csr_write(stimecmp, timecmp);
94cadaabccSMitchell Horne else
95cadaabccSMitchell Horne sbi_set_timer(timecmp);
96cadaabccSMitchell Horne }
97cadaabccSMitchell Horne
98715276a0SMitchell Horne static u_int
riscv_timer_tc_get_timecount(struct timecounter * tc __unused)99b82f4170SMitchell Horne riscv_timer_tc_get_timecount(struct timecounter *tc __unused)
10028029b68SRuslan Bukin {
10128029b68SRuslan Bukin
102b82f4170SMitchell Horne return (get_timecount());
10328029b68SRuslan Bukin }
10428029b68SRuslan Bukin
105715276a0SMitchell Horne static uint32_t
riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands * vdso_th,struct timecounter * tc)106715276a0SMitchell Horne riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th,
107715276a0SMitchell Horne struct timecounter *tc)
108715276a0SMitchell Horne {
109715276a0SMitchell Horne vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME;
110715276a0SMitchell Horne bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
111715276a0SMitchell Horne return (1);
112715276a0SMitchell Horne }
113715276a0SMitchell Horne
11428029b68SRuslan Bukin static int
riscv_timer_et_start(struct eventtimer * et,sbintime_t first,sbintime_t period)115715276a0SMitchell Horne riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
11628029b68SRuslan Bukin {
11798f50c44SRuslan Bukin uint64_t counts;
11828029b68SRuslan Bukin
11928029b68SRuslan Bukin if (first != 0) {
12028029b68SRuslan Bukin counts = ((uint32_t)et->et_frequency * first) >> 32;
121cadaabccSMitchell Horne set_timecmp(get_timecount() + counts);
12298f50c44SRuslan Bukin
12328029b68SRuslan Bukin return (0);
12428029b68SRuslan Bukin }
12528029b68SRuslan Bukin
12628029b68SRuslan Bukin return (EINVAL);
12728029b68SRuslan Bukin }
12828029b68SRuslan Bukin
12928029b68SRuslan Bukin static int
riscv_timer_et_stop(struct eventtimer * et)130715276a0SMitchell Horne riscv_timer_et_stop(struct eventtimer *et)
13128029b68SRuslan Bukin {
13228029b68SRuslan Bukin
1333a4256ddSMitchell Horne /* Disable timer interrupts. */
1343a4256ddSMitchell Horne csr_clear(sie, SIE_STIE);
13528029b68SRuslan Bukin
13628029b68SRuslan Bukin return (0);
13728029b68SRuslan Bukin }
13828029b68SRuslan Bukin
13928029b68SRuslan Bukin static int
riscv_timer_intr(void * arg)140af19cc59SRuslan Bukin riscv_timer_intr(void *arg)
14128029b68SRuslan Bukin {
142af19cc59SRuslan Bukin struct riscv_timer_softc *sc;
14328029b68SRuslan Bukin
144af19cc59SRuslan Bukin sc = (struct riscv_timer_softc *)arg;
14528029b68SRuslan Bukin
14698f50c44SRuslan Bukin csr_clear(sip, SIP_STIP);
14728029b68SRuslan Bukin
14828029b68SRuslan Bukin if (sc->et.et_active)
14928029b68SRuslan Bukin sc->et.et_event_cb(&sc->et, sc->et.et_arg);
15028029b68SRuslan Bukin
15128029b68SRuslan Bukin return (FILTER_HANDLED);
15228029b68SRuslan Bukin }
15328029b68SRuslan Bukin
15428029b68SRuslan Bukin static int
riscv_timer_get_timebase(device_t dev,uint32_t * freq)15561fef9e8SRuslan Bukin riscv_timer_get_timebase(device_t dev, uint32_t *freq)
15661fef9e8SRuslan Bukin {
15761fef9e8SRuslan Bukin phandle_t node;
15861fef9e8SRuslan Bukin int len;
15961fef9e8SRuslan Bukin
16061fef9e8SRuslan Bukin node = OF_finddevice("/cpus");
16161fef9e8SRuslan Bukin if (node == -1) {
16261fef9e8SRuslan Bukin if (bootverbose)
16361fef9e8SRuslan Bukin device_printf(dev, "Can't find cpus node.\n");
16461fef9e8SRuslan Bukin return (ENXIO);
16561fef9e8SRuslan Bukin }
16661fef9e8SRuslan Bukin
16761fef9e8SRuslan Bukin len = OF_getproplen(node, "timebase-frequency");
16861fef9e8SRuslan Bukin if (len != 4) {
16961fef9e8SRuslan Bukin if (bootverbose)
17061fef9e8SRuslan Bukin device_printf(dev,
17161fef9e8SRuslan Bukin "Can't find timebase-frequency property.\n");
17261fef9e8SRuslan Bukin return (ENXIO);
17361fef9e8SRuslan Bukin }
17461fef9e8SRuslan Bukin
17561fef9e8SRuslan Bukin OF_getencprop(node, "timebase-frequency", freq, len);
17661fef9e8SRuslan Bukin
17761fef9e8SRuslan Bukin return (0);
17861fef9e8SRuslan Bukin }
17961fef9e8SRuslan Bukin
18061fef9e8SRuslan Bukin static int
riscv_timer_probe(device_t dev)181af19cc59SRuslan Bukin riscv_timer_probe(device_t dev)
18228029b68SRuslan Bukin {
18328029b68SRuslan Bukin
18428029b68SRuslan Bukin device_set_desc(dev, "RISC-V Timer");
185af19cc59SRuslan Bukin
18628029b68SRuslan Bukin return (BUS_PROBE_DEFAULT);
18728029b68SRuslan Bukin }
18828029b68SRuslan Bukin
18928029b68SRuslan Bukin static int
riscv_timer_attach(device_t dev)190af19cc59SRuslan Bukin riscv_timer_attach(device_t dev)
19128029b68SRuslan Bukin {
192af19cc59SRuslan Bukin struct riscv_timer_softc *sc;
1936ec8bf9fSJessica Clarke int irq, rid, error;
1946ec8bf9fSJessica Clarke phandle_t iparent;
1956ec8bf9fSJessica Clarke pcell_t cell;
19628029b68SRuslan Bukin
19728029b68SRuslan Bukin sc = device_get_softc(dev);
198715276a0SMitchell Horne if (riscv_timer_sc != NULL)
19928029b68SRuslan Bukin return (ENXIO);
20028029b68SRuslan Bukin
201af19cc59SRuslan Bukin if (device_get_unit(dev) != 0)
20261fef9e8SRuslan Bukin return (ENXIO);
20328029b68SRuslan Bukin
20461fef9e8SRuslan Bukin if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) {
20528029b68SRuslan Bukin device_printf(dev, "No clock frequency specified\n");
20628029b68SRuslan Bukin return (ENXIO);
20728029b68SRuslan Bukin }
20828029b68SRuslan Bukin
209af19cc59SRuslan Bukin riscv_timer_sc = sc;
210af19cc59SRuslan Bukin
2116ec8bf9fSJessica Clarke iparent = OF_xref_from_node(ofw_bus_get_node(intr_irq_root_dev));
2126ec8bf9fSJessica Clarke cell = IRQ_TIMER_SUPERVISOR;
2136ec8bf9fSJessica Clarke irq = ofw_bus_map_intr(dev, iparent, 1, &cell);
2146ec8bf9fSJessica Clarke error = bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
2156ec8bf9fSJessica Clarke if (error != 0) {
2166ec8bf9fSJessica Clarke device_printf(dev, "Unable to register IRQ resource\n");
2176ec8bf9fSJessica Clarke return (ENXIO);
2186ec8bf9fSJessica Clarke }
2196ec8bf9fSJessica Clarke
2206ec8bf9fSJessica Clarke rid = 0;
2216ec8bf9fSJessica Clarke sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2226ec8bf9fSJessica Clarke RF_ACTIVE);
2236ec8bf9fSJessica Clarke if (sc->irq_res == NULL) {
2246ec8bf9fSJessica Clarke device_printf(dev, "Unable to alloc IRQ resource\n");
2256ec8bf9fSJessica Clarke return (ENXIO);
2266ec8bf9fSJessica Clarke }
2276ec8bf9fSJessica Clarke
22828029b68SRuslan Bukin /* Setup IRQs handler */
2296ec8bf9fSJessica Clarke error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
2306ec8bf9fSJessica Clarke riscv_timer_intr, NULL, sc, &sc->ih);
2316ec8bf9fSJessica Clarke if (error != 0) {
2326ec8bf9fSJessica Clarke device_printf(dev, "Unable to setup IRQ resource\n");
23328029b68SRuslan Bukin return (ENXIO);
23428029b68SRuslan Bukin }
23528029b68SRuslan Bukin
236af19cc59SRuslan Bukin riscv_timer_timecount.tc_frequency = sc->clkfreq;
237af19cc59SRuslan Bukin riscv_timer_timecount.tc_priv = sc;
238af19cc59SRuslan Bukin tc_init(&riscv_timer_timecount);
23928029b68SRuslan Bukin
24028029b68SRuslan Bukin sc->et.et_name = "RISC-V Eventtimer";
24128029b68SRuslan Bukin sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
24228029b68SRuslan Bukin sc->et.et_quality = 1000;
24328029b68SRuslan Bukin
24428029b68SRuslan Bukin sc->et.et_frequency = sc->clkfreq;
24528029b68SRuslan Bukin sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
24628029b68SRuslan Bukin sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
247715276a0SMitchell Horne sc->et.et_start = riscv_timer_et_start;
248715276a0SMitchell Horne sc->et.et_stop = riscv_timer_et_stop;
24928029b68SRuslan Bukin sc->et.et_priv = sc;
25028029b68SRuslan Bukin et_register(&sc->et);
25128029b68SRuslan Bukin
25233734a1fSMitchell Horne set_cputicker(get_timecount, sc->clkfreq, false);
25333734a1fSMitchell Horne
25428029b68SRuslan Bukin return (0);
25528029b68SRuslan Bukin }
25628029b68SRuslan Bukin
257af19cc59SRuslan Bukin static device_method_t riscv_timer_methods[] = {
258af19cc59SRuslan Bukin DEVMETHOD(device_probe, riscv_timer_probe),
259af19cc59SRuslan Bukin DEVMETHOD(device_attach, riscv_timer_attach),
26028029b68SRuslan Bukin { 0, 0 }
26128029b68SRuslan Bukin };
26228029b68SRuslan Bukin
263af19cc59SRuslan Bukin static driver_t riscv_timer_driver = {
26428029b68SRuslan Bukin "timer",
265af19cc59SRuslan Bukin riscv_timer_methods,
266af19cc59SRuslan Bukin sizeof(struct riscv_timer_softc),
26728029b68SRuslan Bukin };
26828029b68SRuslan Bukin
2692663ef1bSJohn Baldwin EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0,
2702663ef1bSJohn Baldwin BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
27128029b68SRuslan Bukin
27228029b68SRuslan Bukin void
DELAY(int usec)27328029b68SRuslan Bukin DELAY(int usec)
27428029b68SRuslan Bukin {
27598f50c44SRuslan Bukin int64_t counts, counts_per_usec;
27698f50c44SRuslan Bukin uint64_t first, last;
27728029b68SRuslan Bukin
27828029b68SRuslan Bukin /*
27928029b68SRuslan Bukin * Check the timers are setup, if not just
28028029b68SRuslan Bukin * use a for loop for the meantime
28128029b68SRuslan Bukin */
282af19cc59SRuslan Bukin if (riscv_timer_sc == NULL) {
28328029b68SRuslan Bukin for (; usec > 0; usec--)
28428029b68SRuslan Bukin for (counts = 200; counts > 0; counts--)
28528029b68SRuslan Bukin /*
28628029b68SRuslan Bukin * Prevent the compiler from optimizing
28728029b68SRuslan Bukin * out the loop
28828029b68SRuslan Bukin */
28928029b68SRuslan Bukin cpufunc_nullop();
29028029b68SRuslan Bukin return;
29128029b68SRuslan Bukin }
292d5d7606cSColin Percival TSENTER();
29328029b68SRuslan Bukin
29428029b68SRuslan Bukin /* Get the number of times to count */
295af19cc59SRuslan Bukin counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
29628029b68SRuslan Bukin
29728029b68SRuslan Bukin /*
29828029b68SRuslan Bukin * Clamp the timeout at a maximum value (about 32 seconds with
29928029b68SRuslan Bukin * a 66MHz clock). *Nobody* should be delay()ing for anywhere
30028029b68SRuslan Bukin * near that length of time and if they are, they should be hung
30128029b68SRuslan Bukin * out to dry.
30228029b68SRuslan Bukin */
30328029b68SRuslan Bukin if (usec >= (0x80000000U / counts_per_usec))
30428029b68SRuslan Bukin counts = (0x80000000U / counts_per_usec) - 1;
30528029b68SRuslan Bukin else
30628029b68SRuslan Bukin counts = usec * counts_per_usec;
30728029b68SRuslan Bukin
308b82f4170SMitchell Horne first = get_timecount();
30928029b68SRuslan Bukin
31028029b68SRuslan Bukin while (counts > 0) {
311b82f4170SMitchell Horne last = get_timecount();
31298f50c44SRuslan Bukin counts -= (int64_t)(last - first);
31328029b68SRuslan Bukin first = last;
31428029b68SRuslan Bukin }
315d5d7606cSColin Percival TSEXIT();
31628029b68SRuslan Bukin }
317