128029b68SRuslan Bukin /*- 298f50c44SRuslan Bukin * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com> 328029b68SRuslan Bukin * All rights reserved. 428029b68SRuslan Bukin * 528029b68SRuslan Bukin * Portions of this software were developed by SRI International and the 628029b68SRuslan Bukin * University of Cambridge Computer Laboratory under DARPA/AFRL contract 728029b68SRuslan Bukin * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 828029b68SRuslan Bukin * 928029b68SRuslan Bukin * Portions of this software were developed by the University of Cambridge 1028029b68SRuslan Bukin * Computer Laboratory as part of the CTSRD Project, with support from the 1128029b68SRuslan Bukin * UK Higher Education Innovation Fund (HEIF). 1228029b68SRuslan Bukin * 1328029b68SRuslan Bukin * Redistribution and use in source and binary forms, with or without 1428029b68SRuslan Bukin * modification, are permitted provided that the following conditions 1528029b68SRuslan Bukin * are met: 1628029b68SRuslan Bukin * 1. Redistributions of source code must retain the above copyright 1728029b68SRuslan Bukin * notice, this list of conditions and the following disclaimer. 1828029b68SRuslan Bukin * 2. Redistributions in binary form must reproduce the above copyright 1928029b68SRuslan Bukin * notice, this list of conditions and the following disclaimer in the 2028029b68SRuslan Bukin * documentation and/or other materials provided with the distribution. 2128029b68SRuslan Bukin * 2228029b68SRuslan Bukin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2328029b68SRuslan Bukin * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2428029b68SRuslan Bukin * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2528029b68SRuslan Bukin * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2628029b68SRuslan Bukin * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2728029b68SRuslan Bukin * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2828029b68SRuslan Bukin * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2928029b68SRuslan Bukin * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3028029b68SRuslan Bukin * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3128029b68SRuslan Bukin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3228029b68SRuslan Bukin * SUCH DAMAGE. 3328029b68SRuslan Bukin */ 3428029b68SRuslan Bukin 3528029b68SRuslan Bukin /* 3628029b68SRuslan Bukin * RISC-V Timer 3728029b68SRuslan Bukin */ 3828029b68SRuslan Bukin 3928029b68SRuslan Bukin #include "opt_platform.h" 4028029b68SRuslan Bukin 4128029b68SRuslan Bukin #include <sys/cdefs.h> 4228029b68SRuslan Bukin __FBSDID("$FreeBSD$"); 4328029b68SRuslan Bukin 4428029b68SRuslan Bukin #include <sys/param.h> 4528029b68SRuslan Bukin #include <sys/systm.h> 4628029b68SRuslan Bukin #include <sys/bus.h> 4728029b68SRuslan Bukin #include <sys/kernel.h> 4828029b68SRuslan Bukin #include <sys/module.h> 4928029b68SRuslan Bukin #include <sys/malloc.h> 5028029b68SRuslan Bukin #include <sys/rman.h> 5128029b68SRuslan Bukin #include <sys/timeet.h> 5228029b68SRuslan Bukin #include <sys/timetc.h> 5328029b68SRuslan Bukin #include <sys/watchdog.h> 5428029b68SRuslan Bukin 5528029b68SRuslan Bukin #include <sys/proc.h> 5628029b68SRuslan Bukin 5728029b68SRuslan Bukin #include <machine/bus.h> 5828029b68SRuslan Bukin #include <machine/cpu.h> 5928029b68SRuslan Bukin #include <machine/intr.h> 6028029b68SRuslan Bukin #include <machine/asm.h> 6128029b68SRuslan Bukin #include <machine/trap.h> 625f8228b2SRuslan Bukin #include <machine/sbi.h> 6328029b68SRuslan Bukin 6428029b68SRuslan Bukin #include <dev/fdt/fdt_common.h> 6528029b68SRuslan Bukin #include <dev/ofw/openfirm.h> 6628029b68SRuslan Bukin #include <dev/ofw/ofw_bus.h> 6728029b68SRuslan Bukin #include <dev/ofw/ofw_bus_subr.h> 6828029b68SRuslan Bukin 6928029b68SRuslan Bukin #define DEFAULT_FREQ 1000000 7028029b68SRuslan Bukin 7198f50c44SRuslan Bukin #define TIMER_COUNTS 0x00 7298f50c44SRuslan Bukin #define TIMER_MTIMECMP(cpu) (0x08 + (cpu * 8)) 7398f50c44SRuslan Bukin 7498f50c44SRuslan Bukin #define READ8(_sc, _reg) \ 7598f50c44SRuslan Bukin bus_space_read_8(_sc->bst, _sc->bsh, _reg) 7698f50c44SRuslan Bukin #define WRITE8(_sc, _reg, _val) \ 7798f50c44SRuslan Bukin bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val) 7898f50c44SRuslan Bukin 7928029b68SRuslan Bukin struct riscv_tmr_softc { 8098f50c44SRuslan Bukin struct resource *res[2]; 8198f50c44SRuslan Bukin bus_space_tag_t bst; 8298f50c44SRuslan Bukin bus_space_handle_t bsh; 8398f50c44SRuslan Bukin void *ih; 8428029b68SRuslan Bukin uint32_t clkfreq; 8528029b68SRuslan Bukin struct eventtimer et; 8628029b68SRuslan Bukin }; 8728029b68SRuslan Bukin 8828029b68SRuslan Bukin static struct riscv_tmr_softc *riscv_tmr_sc = NULL; 8928029b68SRuslan Bukin 9028029b68SRuslan Bukin static struct resource_spec timer_spec[] = { 9198f50c44SRuslan Bukin { SYS_RES_MEMORY, 0, RF_ACTIVE }, 9228029b68SRuslan Bukin { SYS_RES_IRQ, 0, RF_ACTIVE }, 9328029b68SRuslan Bukin { -1, 0 } 9428029b68SRuslan Bukin }; 9528029b68SRuslan Bukin 9628029b68SRuslan Bukin static timecounter_get_t riscv_tmr_get_timecount; 9728029b68SRuslan Bukin 9828029b68SRuslan Bukin static struct timecounter riscv_tmr_timecount = { 9928029b68SRuslan Bukin .tc_name = "RISC-V Timecounter", 10028029b68SRuslan Bukin .tc_get_timecount = riscv_tmr_get_timecount, 10128029b68SRuslan Bukin .tc_poll_pps = NULL, 10228029b68SRuslan Bukin .tc_counter_mask = ~0u, 10328029b68SRuslan Bukin .tc_frequency = 0, 10428029b68SRuslan Bukin .tc_quality = 1000, 10528029b68SRuslan Bukin }; 10628029b68SRuslan Bukin 10728029b68SRuslan Bukin static long 10898f50c44SRuslan Bukin get_counts(struct riscv_tmr_softc *sc) 10928029b68SRuslan Bukin { 11028029b68SRuslan Bukin 11198f50c44SRuslan Bukin return (READ8(sc, TIMER_COUNTS)); 11228029b68SRuslan Bukin } 11328029b68SRuslan Bukin 11428029b68SRuslan Bukin static unsigned 11528029b68SRuslan Bukin riscv_tmr_get_timecount(struct timecounter *tc) 11628029b68SRuslan Bukin { 11798f50c44SRuslan Bukin struct riscv_tmr_softc *sc; 11828029b68SRuslan Bukin 11998f50c44SRuslan Bukin sc = tc->tc_priv; 12098f50c44SRuslan Bukin 12198f50c44SRuslan Bukin return (get_counts(sc)); 12228029b68SRuslan Bukin } 12328029b68SRuslan Bukin 12428029b68SRuslan Bukin static int 12528029b68SRuslan Bukin riscv_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 12628029b68SRuslan Bukin { 12728029b68SRuslan Bukin struct riscv_tmr_softc *sc; 12898f50c44SRuslan Bukin uint64_t counts; 12998f50c44SRuslan Bukin int cpu; 13028029b68SRuslan Bukin 13128029b68SRuslan Bukin sc = (struct riscv_tmr_softc *)et->et_priv; 13228029b68SRuslan Bukin 13328029b68SRuslan Bukin if (first != 0) { 13428029b68SRuslan Bukin counts = ((uint32_t)et->et_frequency * first) >> 32; 13598f50c44SRuslan Bukin counts += READ8(sc, TIMER_COUNTS); 13698f50c44SRuslan Bukin cpu = PCPU_GET(cpuid); 13798f50c44SRuslan Bukin WRITE8(sc, TIMER_MTIMECMP(cpu), counts); 13898f50c44SRuslan Bukin csr_set(sie, SIE_STIE); 1395f8228b2SRuslan Bukin sbi_set_timer(counts); 14098f50c44SRuslan Bukin 14128029b68SRuslan Bukin return (0); 14228029b68SRuslan Bukin } 14328029b68SRuslan Bukin 14428029b68SRuslan Bukin return (EINVAL); 14528029b68SRuslan Bukin 14628029b68SRuslan Bukin } 14728029b68SRuslan Bukin 14828029b68SRuslan Bukin static int 14928029b68SRuslan Bukin riscv_tmr_stop(struct eventtimer *et) 15028029b68SRuslan Bukin { 15128029b68SRuslan Bukin struct riscv_tmr_softc *sc; 15228029b68SRuslan Bukin 15328029b68SRuslan Bukin sc = (struct riscv_tmr_softc *)et->et_priv; 15428029b68SRuslan Bukin 15528029b68SRuslan Bukin /* TODO */ 15628029b68SRuslan Bukin 15728029b68SRuslan Bukin return (0); 15828029b68SRuslan Bukin } 15928029b68SRuslan Bukin 16028029b68SRuslan Bukin static int 16128029b68SRuslan Bukin riscv_tmr_intr(void *arg) 16228029b68SRuslan Bukin { 16328029b68SRuslan Bukin struct riscv_tmr_softc *sc; 16428029b68SRuslan Bukin 16528029b68SRuslan Bukin sc = (struct riscv_tmr_softc *)arg; 16628029b68SRuslan Bukin 16798f50c44SRuslan Bukin csr_clear(sip, SIP_STIP); 16828029b68SRuslan Bukin 16928029b68SRuslan Bukin if (sc->et.et_active) 17028029b68SRuslan Bukin sc->et.et_event_cb(&sc->et, sc->et.et_arg); 17128029b68SRuslan Bukin 17228029b68SRuslan Bukin return (FILTER_HANDLED); 17328029b68SRuslan Bukin } 17428029b68SRuslan Bukin 17528029b68SRuslan Bukin static int 17628029b68SRuslan Bukin riscv_tmr_fdt_probe(device_t dev) 17728029b68SRuslan Bukin { 17828029b68SRuslan Bukin 17928029b68SRuslan Bukin if (!ofw_bus_status_okay(dev)) 18028029b68SRuslan Bukin return (ENXIO); 18128029b68SRuslan Bukin 18228029b68SRuslan Bukin if (ofw_bus_is_compatible(dev, "riscv,timer")) { 18328029b68SRuslan Bukin device_set_desc(dev, "RISC-V Timer"); 18428029b68SRuslan Bukin return (BUS_PROBE_DEFAULT); 18528029b68SRuslan Bukin } 18628029b68SRuslan Bukin 18728029b68SRuslan Bukin return (ENXIO); 18828029b68SRuslan Bukin } 18928029b68SRuslan Bukin 19028029b68SRuslan Bukin static int 19128029b68SRuslan Bukin riscv_tmr_attach(device_t dev) 19228029b68SRuslan Bukin { 19328029b68SRuslan Bukin struct riscv_tmr_softc *sc; 19428029b68SRuslan Bukin phandle_t node; 19528029b68SRuslan Bukin pcell_t clock; 19628029b68SRuslan Bukin int error; 19728029b68SRuslan Bukin 19828029b68SRuslan Bukin sc = device_get_softc(dev); 19928029b68SRuslan Bukin if (riscv_tmr_sc) 20028029b68SRuslan Bukin return (ENXIO); 20128029b68SRuslan Bukin 20228029b68SRuslan Bukin /* Get the base clock frequency */ 20328029b68SRuslan Bukin node = ofw_bus_get_node(dev); 20428029b68SRuslan Bukin if (node > 0) { 20528029b68SRuslan Bukin error = OF_getprop(node, "clock-frequency", &clock, 20628029b68SRuslan Bukin sizeof(clock)); 20728029b68SRuslan Bukin if (error > 0) { 20828029b68SRuslan Bukin sc->clkfreq = fdt32_to_cpu(clock); 20928029b68SRuslan Bukin } 21028029b68SRuslan Bukin } 21128029b68SRuslan Bukin 21228029b68SRuslan Bukin if (sc->clkfreq == 0) 21328029b68SRuslan Bukin sc->clkfreq = DEFAULT_FREQ; 21428029b68SRuslan Bukin 21528029b68SRuslan Bukin if (sc->clkfreq == 0) { 21628029b68SRuslan Bukin device_printf(dev, "No clock frequency specified\n"); 21728029b68SRuslan Bukin return (ENXIO); 21828029b68SRuslan Bukin } 21928029b68SRuslan Bukin 22028029b68SRuslan Bukin if (bus_alloc_resources(dev, timer_spec, sc->res)) { 22128029b68SRuslan Bukin device_printf(dev, "could not allocate resources\n"); 22228029b68SRuslan Bukin return (ENXIO); 22328029b68SRuslan Bukin } 22428029b68SRuslan Bukin 22598f50c44SRuslan Bukin /* Memory interface */ 22698f50c44SRuslan Bukin sc->bst = rman_get_bustag(sc->res[0]); 22798f50c44SRuslan Bukin sc->bsh = rman_get_bushandle(sc->res[0]); 22898f50c44SRuslan Bukin 22928029b68SRuslan Bukin riscv_tmr_sc = sc; 23028029b68SRuslan Bukin 23128029b68SRuslan Bukin /* Setup IRQs handler */ 23298f50c44SRuslan Bukin error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, 23398f50c44SRuslan Bukin riscv_tmr_intr, NULL, sc, &sc->ih); 23428029b68SRuslan Bukin if (error) { 23528029b68SRuslan Bukin device_printf(dev, "Unable to alloc int resource.\n"); 23628029b68SRuslan Bukin return (ENXIO); 23728029b68SRuslan Bukin } 23828029b68SRuslan Bukin 23928029b68SRuslan Bukin riscv_tmr_timecount.tc_frequency = sc->clkfreq; 24098f50c44SRuslan Bukin riscv_tmr_timecount.tc_priv = sc; 24128029b68SRuslan Bukin tc_init(&riscv_tmr_timecount); 24228029b68SRuslan Bukin 24328029b68SRuslan Bukin sc->et.et_name = "RISC-V Eventtimer"; 24428029b68SRuslan Bukin sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 24528029b68SRuslan Bukin sc->et.et_quality = 1000; 24628029b68SRuslan Bukin 24728029b68SRuslan Bukin sc->et.et_frequency = sc->clkfreq; 24828029b68SRuslan Bukin sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 24928029b68SRuslan Bukin sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 25028029b68SRuslan Bukin sc->et.et_start = riscv_tmr_start; 25128029b68SRuslan Bukin sc->et.et_stop = riscv_tmr_stop; 25228029b68SRuslan Bukin sc->et.et_priv = sc; 25328029b68SRuslan Bukin et_register(&sc->et); 25428029b68SRuslan Bukin 25528029b68SRuslan Bukin return (0); 25628029b68SRuslan Bukin } 25728029b68SRuslan Bukin 25828029b68SRuslan Bukin static device_method_t riscv_tmr_fdt_methods[] = { 25928029b68SRuslan Bukin DEVMETHOD(device_probe, riscv_tmr_fdt_probe), 26028029b68SRuslan Bukin DEVMETHOD(device_attach, riscv_tmr_attach), 26128029b68SRuslan Bukin { 0, 0 } 26228029b68SRuslan Bukin }; 26328029b68SRuslan Bukin 26428029b68SRuslan Bukin static driver_t riscv_tmr_fdt_driver = { 26528029b68SRuslan Bukin "timer", 26628029b68SRuslan Bukin riscv_tmr_fdt_methods, 26728029b68SRuslan Bukin sizeof(struct riscv_tmr_softc), 26828029b68SRuslan Bukin }; 26928029b68SRuslan Bukin 27028029b68SRuslan Bukin static devclass_t riscv_tmr_fdt_devclass; 27128029b68SRuslan Bukin 27228029b68SRuslan Bukin EARLY_DRIVER_MODULE(timer, simplebus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass, 27328029b68SRuslan Bukin 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 27428029b68SRuslan Bukin EARLY_DRIVER_MODULE(timer, ofwbus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass, 27528029b68SRuslan Bukin 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 27628029b68SRuslan Bukin 27728029b68SRuslan Bukin void 27828029b68SRuslan Bukin DELAY(int usec) 27928029b68SRuslan Bukin { 28098f50c44SRuslan Bukin int64_t counts, counts_per_usec; 28198f50c44SRuslan Bukin uint64_t first, last; 28228029b68SRuslan Bukin 28328029b68SRuslan Bukin /* 28428029b68SRuslan Bukin * Check the timers are setup, if not just 28528029b68SRuslan Bukin * use a for loop for the meantime 28628029b68SRuslan Bukin */ 28728029b68SRuslan Bukin if (riscv_tmr_sc == NULL) { 28828029b68SRuslan Bukin for (; usec > 0; usec--) 28928029b68SRuslan Bukin for (counts = 200; counts > 0; counts--) 29028029b68SRuslan Bukin /* 29128029b68SRuslan Bukin * Prevent the compiler from optimizing 29228029b68SRuslan Bukin * out the loop 29328029b68SRuslan Bukin */ 29428029b68SRuslan Bukin cpufunc_nullop(); 29528029b68SRuslan Bukin return; 29628029b68SRuslan Bukin } 29728029b68SRuslan Bukin 29828029b68SRuslan Bukin /* Get the number of times to count */ 29928029b68SRuslan Bukin counts_per_usec = ((riscv_tmr_timecount.tc_frequency / 1000000) + 1); 30028029b68SRuslan Bukin 30128029b68SRuslan Bukin /* 30228029b68SRuslan Bukin * Clamp the timeout at a maximum value (about 32 seconds with 30328029b68SRuslan Bukin * a 66MHz clock). *Nobody* should be delay()ing for anywhere 30428029b68SRuslan Bukin * near that length of time and if they are, they should be hung 30528029b68SRuslan Bukin * out to dry. 30628029b68SRuslan Bukin */ 30728029b68SRuslan Bukin if (usec >= (0x80000000U / counts_per_usec)) 30828029b68SRuslan Bukin counts = (0x80000000U / counts_per_usec) - 1; 30928029b68SRuslan Bukin else 31028029b68SRuslan Bukin counts = usec * counts_per_usec; 31128029b68SRuslan Bukin 31298f50c44SRuslan Bukin first = get_counts(riscv_tmr_sc); 31328029b68SRuslan Bukin 31428029b68SRuslan Bukin while (counts > 0) { 31598f50c44SRuslan Bukin last = get_counts(riscv_tmr_sc); 31698f50c44SRuslan Bukin counts -= (int64_t)(last - first); 31728029b68SRuslan Bukin first = last; 31828029b68SRuslan Bukin } 31928029b68SRuslan Bukin } 320