1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/vdso.h> 52 #include <sys/watchdog.h> 53 54 #include <machine/cpufunc.h> 55 #include <machine/intr.h> 56 #include <machine/sbi.h> 57 58 #include <dev/ofw/openfirm.h> 59 60 struct riscv_timer_softc { 61 void *ih; 62 uint32_t clkfreq; 63 struct eventtimer et; 64 }; 65 static struct riscv_timer_softc *riscv_timer_sc = NULL; 66 67 static timecounter_get_t riscv_timer_tc_get_timecount; 68 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands; 69 70 static struct timecounter riscv_timer_timecount = { 71 .tc_name = "RISC-V Timecounter", 72 .tc_get_timecount = riscv_timer_tc_get_timecount, 73 .tc_poll_pps = NULL, 74 .tc_counter_mask = ~0u, 75 .tc_frequency = 0, 76 .tc_quality = 1000, 77 .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands, 78 }; 79 80 static inline uint64_t 81 get_timecount(void) 82 { 83 84 return (rdtime()); 85 } 86 87 static u_int 88 riscv_timer_tc_get_timecount(struct timecounter *tc __unused) 89 { 90 91 return (get_timecount()); 92 } 93 94 static uint32_t 95 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th, 96 struct timecounter *tc) 97 { 98 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; 99 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 100 return (1); 101 } 102 103 static int 104 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 105 { 106 uint64_t counts; 107 108 if (first != 0) { 109 counts = ((uint32_t)et->et_frequency * first) >> 32; 110 sbi_set_timer(get_timecount() + counts); 111 csr_set(sie, SIE_STIE); 112 113 return (0); 114 } 115 116 return (EINVAL); 117 } 118 119 static int 120 riscv_timer_et_stop(struct eventtimer *et) 121 { 122 123 /* Disable timer interrupts. */ 124 csr_clear(sie, SIE_STIE); 125 126 return (0); 127 } 128 129 static int 130 riscv_timer_intr(void *arg) 131 { 132 struct riscv_timer_softc *sc; 133 134 sc = (struct riscv_timer_softc *)arg; 135 136 csr_clear(sip, SIP_STIP); 137 138 if (sc->et.et_active) 139 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 140 141 return (FILTER_HANDLED); 142 } 143 144 static int 145 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 146 { 147 phandle_t node; 148 int len; 149 150 node = OF_finddevice("/cpus"); 151 if (node == -1) { 152 if (bootverbose) 153 device_printf(dev, "Can't find cpus node.\n"); 154 return (ENXIO); 155 } 156 157 len = OF_getproplen(node, "timebase-frequency"); 158 if (len != 4) { 159 if (bootverbose) 160 device_printf(dev, 161 "Can't find timebase-frequency property.\n"); 162 return (ENXIO); 163 } 164 165 OF_getencprop(node, "timebase-frequency", freq, len); 166 167 return (0); 168 } 169 170 static int 171 riscv_timer_probe(device_t dev) 172 { 173 174 device_set_desc(dev, "RISC-V Timer"); 175 176 return (BUS_PROBE_DEFAULT); 177 } 178 179 static int 180 riscv_timer_attach(device_t dev) 181 { 182 struct riscv_timer_softc *sc; 183 int error; 184 185 sc = device_get_softc(dev); 186 if (riscv_timer_sc != NULL) 187 return (ENXIO); 188 189 if (device_get_unit(dev) != 0) 190 return (ENXIO); 191 192 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 193 device_printf(dev, "No clock frequency specified\n"); 194 return (ENXIO); 195 } 196 197 riscv_timer_sc = sc; 198 199 /* Setup IRQs handler */ 200 error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr, 201 NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih); 202 if (error) { 203 device_printf(dev, "Unable to alloc int resource.\n"); 204 return (ENXIO); 205 } 206 207 riscv_timer_timecount.tc_frequency = sc->clkfreq; 208 riscv_timer_timecount.tc_priv = sc; 209 tc_init(&riscv_timer_timecount); 210 211 sc->et.et_name = "RISC-V Eventtimer"; 212 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 213 sc->et.et_quality = 1000; 214 215 sc->et.et_frequency = sc->clkfreq; 216 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 217 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 218 sc->et.et_start = riscv_timer_et_start; 219 sc->et.et_stop = riscv_timer_et_stop; 220 sc->et.et_priv = sc; 221 et_register(&sc->et); 222 223 set_cputicker(get_timecount, sc->clkfreq, false); 224 225 return (0); 226 } 227 228 static device_method_t riscv_timer_methods[] = { 229 DEVMETHOD(device_probe, riscv_timer_probe), 230 DEVMETHOD(device_attach, riscv_timer_attach), 231 { 0, 0 } 232 }; 233 234 static driver_t riscv_timer_driver = { 235 "timer", 236 riscv_timer_methods, 237 sizeof(struct riscv_timer_softc), 238 }; 239 240 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0, 241 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 242 243 void 244 DELAY(int usec) 245 { 246 int64_t counts, counts_per_usec; 247 uint64_t first, last; 248 249 /* 250 * Check the timers are setup, if not just 251 * use a for loop for the meantime 252 */ 253 if (riscv_timer_sc == NULL) { 254 for (; usec > 0; usec--) 255 for (counts = 200; counts > 0; counts--) 256 /* 257 * Prevent the compiler from optimizing 258 * out the loop 259 */ 260 cpufunc_nullop(); 261 return; 262 } 263 TSENTER(); 264 265 /* Get the number of times to count */ 266 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 267 268 /* 269 * Clamp the timeout at a maximum value (about 32 seconds with 270 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 271 * near that length of time and if they are, they should be hung 272 * out to dry. 273 */ 274 if (usec >= (0x80000000U / counts_per_usec)) 275 counts = (0x80000000U / counts_per_usec) - 1; 276 else 277 counts = usec * counts_per_usec; 278 279 first = get_timecount(); 280 281 while (counts > 0) { 282 last = get_timecount(); 283 counts -= (int64_t)(last - first); 284 first = last; 285 } 286 TSEXIT(); 287 } 288