1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/timeet.h> 47 #include <sys/timetc.h> 48 #include <sys/vdso.h> 49 #include <sys/watchdog.h> 50 51 #include <machine/cpufunc.h> 52 #include <machine/intr.h> 53 #include <machine/md_var.h> 54 #include <machine/sbi.h> 55 56 #include <dev/ofw/openfirm.h> 57 58 struct riscv_timer_softc { 59 void *ih; 60 uint32_t clkfreq; 61 struct eventtimer et; 62 }; 63 static struct riscv_timer_softc *riscv_timer_sc = NULL; 64 65 static timecounter_get_t riscv_timer_tc_get_timecount; 66 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands; 67 68 static struct timecounter riscv_timer_timecount = { 69 .tc_name = "RISC-V Timecounter", 70 .tc_get_timecount = riscv_timer_tc_get_timecount, 71 .tc_poll_pps = NULL, 72 .tc_counter_mask = ~0u, 73 .tc_frequency = 0, 74 .tc_quality = 1000, 75 .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands, 76 }; 77 78 static inline uint64_t 79 get_timecount(void) 80 { 81 82 return (rdtime()); 83 } 84 85 static inline void 86 set_timecmp(uint64_t timecmp) 87 { 88 89 if (has_sstc) 90 csr_write(stimecmp, timecmp); 91 else 92 sbi_set_timer(timecmp); 93 } 94 95 static u_int 96 riscv_timer_tc_get_timecount(struct timecounter *tc __unused) 97 { 98 99 return (get_timecount()); 100 } 101 102 static uint32_t 103 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th, 104 struct timecounter *tc) 105 { 106 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; 107 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 108 return (1); 109 } 110 111 static int 112 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 113 { 114 uint64_t counts; 115 116 if (first != 0) { 117 counts = ((uint32_t)et->et_frequency * first) >> 32; 118 set_timecmp(get_timecount() + counts); 119 csr_set(sie, SIE_STIE); 120 121 return (0); 122 } 123 124 return (EINVAL); 125 } 126 127 static int 128 riscv_timer_et_stop(struct eventtimer *et) 129 { 130 131 /* Disable timer interrupts. */ 132 csr_clear(sie, SIE_STIE); 133 134 return (0); 135 } 136 137 static int 138 riscv_timer_intr(void *arg) 139 { 140 struct riscv_timer_softc *sc; 141 142 sc = (struct riscv_timer_softc *)arg; 143 144 csr_clear(sip, SIP_STIP); 145 146 if (sc->et.et_active) 147 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 148 149 return (FILTER_HANDLED); 150 } 151 152 static int 153 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 154 { 155 phandle_t node; 156 int len; 157 158 node = OF_finddevice("/cpus"); 159 if (node == -1) { 160 if (bootverbose) 161 device_printf(dev, "Can't find cpus node.\n"); 162 return (ENXIO); 163 } 164 165 len = OF_getproplen(node, "timebase-frequency"); 166 if (len != 4) { 167 if (bootverbose) 168 device_printf(dev, 169 "Can't find timebase-frequency property.\n"); 170 return (ENXIO); 171 } 172 173 OF_getencprop(node, "timebase-frequency", freq, len); 174 175 return (0); 176 } 177 178 static int 179 riscv_timer_probe(device_t dev) 180 { 181 182 device_set_desc(dev, "RISC-V Timer"); 183 184 return (BUS_PROBE_DEFAULT); 185 } 186 187 static int 188 riscv_timer_attach(device_t dev) 189 { 190 struct riscv_timer_softc *sc; 191 int error; 192 193 sc = device_get_softc(dev); 194 if (riscv_timer_sc != NULL) 195 return (ENXIO); 196 197 if (device_get_unit(dev) != 0) 198 return (ENXIO); 199 200 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 201 device_printf(dev, "No clock frequency specified\n"); 202 return (ENXIO); 203 } 204 205 riscv_timer_sc = sc; 206 207 /* Setup IRQs handler */ 208 error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr, 209 NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih); 210 if (error) { 211 device_printf(dev, "Unable to alloc int resource.\n"); 212 return (ENXIO); 213 } 214 215 riscv_timer_timecount.tc_frequency = sc->clkfreq; 216 riscv_timer_timecount.tc_priv = sc; 217 tc_init(&riscv_timer_timecount); 218 219 sc->et.et_name = "RISC-V Eventtimer"; 220 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 221 sc->et.et_quality = 1000; 222 223 sc->et.et_frequency = sc->clkfreq; 224 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 225 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 226 sc->et.et_start = riscv_timer_et_start; 227 sc->et.et_stop = riscv_timer_et_stop; 228 sc->et.et_priv = sc; 229 et_register(&sc->et); 230 231 set_cputicker(get_timecount, sc->clkfreq, false); 232 233 return (0); 234 } 235 236 static device_method_t riscv_timer_methods[] = { 237 DEVMETHOD(device_probe, riscv_timer_probe), 238 DEVMETHOD(device_attach, riscv_timer_attach), 239 { 0, 0 } 240 }; 241 242 static driver_t riscv_timer_driver = { 243 "timer", 244 riscv_timer_methods, 245 sizeof(struct riscv_timer_softc), 246 }; 247 248 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0, 249 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 250 251 void 252 DELAY(int usec) 253 { 254 int64_t counts, counts_per_usec; 255 uint64_t first, last; 256 257 /* 258 * Check the timers are setup, if not just 259 * use a for loop for the meantime 260 */ 261 if (riscv_timer_sc == NULL) { 262 for (; usec > 0; usec--) 263 for (counts = 200; counts > 0; counts--) 264 /* 265 * Prevent the compiler from optimizing 266 * out the loop 267 */ 268 cpufunc_nullop(); 269 return; 270 } 271 TSENTER(); 272 273 /* Get the number of times to count */ 274 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 275 276 /* 277 * Clamp the timeout at a maximum value (about 32 seconds with 278 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 279 * near that length of time and if they are, they should be hung 280 * out to dry. 281 */ 282 if (usec >= (0x80000000U / counts_per_usec)) 283 counts = (0x80000000U / counts_per_usec) - 1; 284 else 285 counts = usec * counts_per_usec; 286 287 first = get_timecount(); 288 289 while (counts > 0) { 290 last = get_timecount(); 291 counts -= (int64_t)(last - first); 292 first = last; 293 } 294 TSEXIT(); 295 } 296