1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/cdefs.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/module.h> 47 #include <sys/timeet.h> 48 #include <sys/timetc.h> 49 #include <sys/vdso.h> 50 #include <sys/watchdog.h> 51 52 #include <machine/cpufunc.h> 53 #include <machine/intr.h> 54 #include <machine/md_var.h> 55 #include <machine/sbi.h> 56 57 #include <dev/ofw/openfirm.h> 58 59 struct riscv_timer_softc { 60 void *ih; 61 uint32_t clkfreq; 62 struct eventtimer et; 63 }; 64 static struct riscv_timer_softc *riscv_timer_sc = NULL; 65 66 static timecounter_get_t riscv_timer_tc_get_timecount; 67 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands; 68 69 static struct timecounter riscv_timer_timecount = { 70 .tc_name = "RISC-V Timecounter", 71 .tc_get_timecount = riscv_timer_tc_get_timecount, 72 .tc_poll_pps = NULL, 73 .tc_counter_mask = ~0u, 74 .tc_frequency = 0, 75 .tc_quality = 1000, 76 .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands, 77 }; 78 79 static inline uint64_t 80 get_timecount(void) 81 { 82 83 return (rdtime()); 84 } 85 86 static inline void 87 set_timecmp(uint64_t timecmp) 88 { 89 90 if (has_sstc) 91 csr_write(stimecmp, timecmp); 92 else 93 sbi_set_timer(timecmp); 94 } 95 96 static u_int 97 riscv_timer_tc_get_timecount(struct timecounter *tc __unused) 98 { 99 100 return (get_timecount()); 101 } 102 103 static uint32_t 104 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th, 105 struct timecounter *tc) 106 { 107 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; 108 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 109 return (1); 110 } 111 112 static int 113 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 114 { 115 uint64_t counts; 116 117 if (first != 0) { 118 counts = ((uint32_t)et->et_frequency * first) >> 32; 119 set_timecmp(get_timecount() + counts); 120 csr_set(sie, SIE_STIE); 121 122 return (0); 123 } 124 125 return (EINVAL); 126 } 127 128 static int 129 riscv_timer_et_stop(struct eventtimer *et) 130 { 131 132 /* Disable timer interrupts. */ 133 csr_clear(sie, SIE_STIE); 134 135 return (0); 136 } 137 138 static int 139 riscv_timer_intr(void *arg) 140 { 141 struct riscv_timer_softc *sc; 142 143 sc = (struct riscv_timer_softc *)arg; 144 145 csr_clear(sip, SIP_STIP); 146 147 if (sc->et.et_active) 148 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 149 150 return (FILTER_HANDLED); 151 } 152 153 static int 154 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 155 { 156 phandle_t node; 157 int len; 158 159 node = OF_finddevice("/cpus"); 160 if (node == -1) { 161 if (bootverbose) 162 device_printf(dev, "Can't find cpus node.\n"); 163 return (ENXIO); 164 } 165 166 len = OF_getproplen(node, "timebase-frequency"); 167 if (len != 4) { 168 if (bootverbose) 169 device_printf(dev, 170 "Can't find timebase-frequency property.\n"); 171 return (ENXIO); 172 } 173 174 OF_getencprop(node, "timebase-frequency", freq, len); 175 176 return (0); 177 } 178 179 static int 180 riscv_timer_probe(device_t dev) 181 { 182 183 device_set_desc(dev, "RISC-V Timer"); 184 185 return (BUS_PROBE_DEFAULT); 186 } 187 188 static int 189 riscv_timer_attach(device_t dev) 190 { 191 struct riscv_timer_softc *sc; 192 int error; 193 194 sc = device_get_softc(dev); 195 if (riscv_timer_sc != NULL) 196 return (ENXIO); 197 198 if (device_get_unit(dev) != 0) 199 return (ENXIO); 200 201 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 202 device_printf(dev, "No clock frequency specified\n"); 203 return (ENXIO); 204 } 205 206 riscv_timer_sc = sc; 207 208 /* Setup IRQs handler */ 209 error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr, 210 NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih); 211 if (error) { 212 device_printf(dev, "Unable to alloc int resource.\n"); 213 return (ENXIO); 214 } 215 216 riscv_timer_timecount.tc_frequency = sc->clkfreq; 217 riscv_timer_timecount.tc_priv = sc; 218 tc_init(&riscv_timer_timecount); 219 220 sc->et.et_name = "RISC-V Eventtimer"; 221 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 222 sc->et.et_quality = 1000; 223 224 sc->et.et_frequency = sc->clkfreq; 225 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 226 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 227 sc->et.et_start = riscv_timer_et_start; 228 sc->et.et_stop = riscv_timer_et_stop; 229 sc->et.et_priv = sc; 230 et_register(&sc->et); 231 232 set_cputicker(get_timecount, sc->clkfreq, false); 233 234 return (0); 235 } 236 237 static device_method_t riscv_timer_methods[] = { 238 DEVMETHOD(device_probe, riscv_timer_probe), 239 DEVMETHOD(device_attach, riscv_timer_attach), 240 { 0, 0 } 241 }; 242 243 static driver_t riscv_timer_driver = { 244 "timer", 245 riscv_timer_methods, 246 sizeof(struct riscv_timer_softc), 247 }; 248 249 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0, 250 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 251 252 void 253 DELAY(int usec) 254 { 255 int64_t counts, counts_per_usec; 256 uint64_t first, last; 257 258 /* 259 * Check the timers are setup, if not just 260 * use a for loop for the meantime 261 */ 262 if (riscv_timer_sc == NULL) { 263 for (; usec > 0; usec--) 264 for (counts = 200; counts > 0; counts--) 265 /* 266 * Prevent the compiler from optimizing 267 * out the loop 268 */ 269 cpufunc_nullop(); 270 return; 271 } 272 TSENTER(); 273 274 /* Get the number of times to count */ 275 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 276 277 /* 278 * Clamp the timeout at a maximum value (about 32 seconds with 279 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 280 * near that length of time and if they are, they should be hung 281 * out to dry. 282 */ 283 if (usec >= (0x80000000U / counts_per_usec)) 284 counts = (0x80000000U / counts_per_usec) - 1; 285 else 286 counts = usec * counts_per_usec; 287 288 first = get_timecount(); 289 290 while (counts > 0) { 291 last = get_timecount(); 292 counts -= (int64_t)(last - first); 293 first = last; 294 } 295 TSEXIT(); 296 } 297