1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/vdso.h> 52 #include <sys/watchdog.h> 53 54 #include <machine/cpufunc.h> 55 #include <machine/intr.h> 56 #include <machine/sbi.h> 57 58 #include <dev/ofw/openfirm.h> 59 60 struct riscv_timer_softc { 61 void *ih; 62 uint32_t clkfreq; 63 struct eventtimer et; 64 }; 65 static struct riscv_timer_softc *riscv_timer_sc = NULL; 66 67 static timecounter_get_t riscv_timer_tc_get_timecount; 68 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands; 69 70 static struct timecounter riscv_timer_timecount = { 71 .tc_name = "RISC-V Timecounter", 72 .tc_get_timecount = riscv_timer_tc_get_timecount, 73 .tc_poll_pps = NULL, 74 .tc_counter_mask = ~0u, 75 .tc_frequency = 0, 76 .tc_quality = 1000, 77 .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands, 78 }; 79 80 static inline uint64_t 81 get_cycles(void) 82 { 83 84 return (rdtime()); 85 } 86 87 static long 88 get_counts(struct riscv_timer_softc *sc) 89 { 90 uint64_t counts; 91 92 counts = get_cycles(); 93 94 return (counts); 95 } 96 97 static u_int 98 riscv_timer_tc_get_timecount(struct timecounter *tc) 99 { 100 struct riscv_timer_softc *sc; 101 102 sc = tc->tc_priv; 103 104 return (get_counts(sc)); 105 } 106 107 static uint32_t 108 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th, 109 struct timecounter *tc) 110 { 111 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; 112 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 113 return (1); 114 } 115 116 static int 117 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 118 { 119 uint64_t counts; 120 121 if (first != 0) { 122 counts = ((uint32_t)et->et_frequency * first) >> 32; 123 sbi_set_timer(get_cycles() + counts); 124 csr_set(sie, SIE_STIE); 125 126 return (0); 127 } 128 129 return (EINVAL); 130 } 131 132 static int 133 riscv_timer_et_stop(struct eventtimer *et) 134 { 135 136 /* TODO */ 137 138 return (0); 139 } 140 141 static int 142 riscv_timer_intr(void *arg) 143 { 144 struct riscv_timer_softc *sc; 145 146 sc = (struct riscv_timer_softc *)arg; 147 148 csr_clear(sip, SIP_STIP); 149 150 if (sc->et.et_active) 151 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 152 153 return (FILTER_HANDLED); 154 } 155 156 static int 157 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 158 { 159 phandle_t node; 160 int len; 161 162 node = OF_finddevice("/cpus"); 163 if (node == -1) { 164 if (bootverbose) 165 device_printf(dev, "Can't find cpus node.\n"); 166 return (ENXIO); 167 } 168 169 len = OF_getproplen(node, "timebase-frequency"); 170 if (len != 4) { 171 if (bootverbose) 172 device_printf(dev, 173 "Can't find timebase-frequency property.\n"); 174 return (ENXIO); 175 } 176 177 OF_getencprop(node, "timebase-frequency", freq, len); 178 179 return (0); 180 } 181 182 static int 183 riscv_timer_probe(device_t dev) 184 { 185 186 device_set_desc(dev, "RISC-V Timer"); 187 188 return (BUS_PROBE_DEFAULT); 189 } 190 191 static int 192 riscv_timer_attach(device_t dev) 193 { 194 struct riscv_timer_softc *sc; 195 int error; 196 197 sc = device_get_softc(dev); 198 if (riscv_timer_sc != NULL) 199 return (ENXIO); 200 201 if (device_get_unit(dev) != 0) 202 return (ENXIO); 203 204 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 205 device_printf(dev, "No clock frequency specified\n"); 206 return (ENXIO); 207 } 208 209 riscv_timer_sc = sc; 210 211 /* Setup IRQs handler */ 212 error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr, 213 NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih); 214 if (error) { 215 device_printf(dev, "Unable to alloc int resource.\n"); 216 return (ENXIO); 217 } 218 219 riscv_timer_timecount.tc_frequency = sc->clkfreq; 220 riscv_timer_timecount.tc_priv = sc; 221 tc_init(&riscv_timer_timecount); 222 223 sc->et.et_name = "RISC-V Eventtimer"; 224 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 225 sc->et.et_quality = 1000; 226 227 sc->et.et_frequency = sc->clkfreq; 228 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 229 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 230 sc->et.et_start = riscv_timer_et_start; 231 sc->et.et_stop = riscv_timer_et_stop; 232 sc->et.et_priv = sc; 233 et_register(&sc->et); 234 235 return (0); 236 } 237 238 static device_method_t riscv_timer_methods[] = { 239 DEVMETHOD(device_probe, riscv_timer_probe), 240 DEVMETHOD(device_attach, riscv_timer_attach), 241 { 0, 0 } 242 }; 243 244 static driver_t riscv_timer_driver = { 245 "timer", 246 riscv_timer_methods, 247 sizeof(struct riscv_timer_softc), 248 }; 249 250 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0, 251 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 252 253 void 254 DELAY(int usec) 255 { 256 int64_t counts, counts_per_usec; 257 uint64_t first, last; 258 259 /* 260 * Check the timers are setup, if not just 261 * use a for loop for the meantime 262 */ 263 if (riscv_timer_sc == NULL) { 264 for (; usec > 0; usec--) 265 for (counts = 200; counts > 0; counts--) 266 /* 267 * Prevent the compiler from optimizing 268 * out the loop 269 */ 270 cpufunc_nullop(); 271 return; 272 } 273 TSENTER(); 274 275 /* Get the number of times to count */ 276 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 277 278 /* 279 * Clamp the timeout at a maximum value (about 32 seconds with 280 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 281 * near that length of time and if they are, they should be hung 282 * out to dry. 283 */ 284 if (usec >= (0x80000000U / counts_per_usec)) 285 counts = (0x80000000U / counts_per_usec) - 1; 286 else 287 counts = usec * counts_per_usec; 288 289 first = get_counts(riscv_timer_sc); 290 291 while (counts > 0) { 292 last = get_counts(riscv_timer_sc); 293 counts -= (int64_t)(last - first); 294 first = last; 295 } 296 TSEXIT(); 297 } 298