1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/vdso.h> 52 #include <sys/watchdog.h> 53 54 #include <machine/cpufunc.h> 55 #include <machine/intr.h> 56 #include <machine/sbi.h> 57 58 #include <dev/ofw/openfirm.h> 59 60 struct riscv_timer_softc { 61 void *ih; 62 uint32_t clkfreq; 63 struct eventtimer et; 64 }; 65 static struct riscv_timer_softc *riscv_timer_sc = NULL; 66 67 static timecounter_get_t riscv_timer_tc_get_timecount; 68 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands; 69 70 static struct timecounter riscv_timer_timecount = { 71 .tc_name = "RISC-V Timecounter", 72 .tc_get_timecount = riscv_timer_tc_get_timecount, 73 .tc_poll_pps = NULL, 74 .tc_counter_mask = ~0u, 75 .tc_frequency = 0, 76 .tc_quality = 1000, 77 .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands, 78 }; 79 80 static inline uint64_t 81 get_timecount(void) 82 { 83 84 return (rdtime()); 85 } 86 87 static u_int 88 riscv_timer_tc_get_timecount(struct timecounter *tc __unused) 89 { 90 91 return (get_timecount()); 92 } 93 94 static uint32_t 95 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th, 96 struct timecounter *tc) 97 { 98 vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME; 99 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 100 return (1); 101 } 102 103 static int 104 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 105 { 106 uint64_t counts; 107 108 if (first != 0) { 109 counts = ((uint32_t)et->et_frequency * first) >> 32; 110 sbi_set_timer(get_timecount() + counts); 111 csr_set(sie, SIE_STIE); 112 113 return (0); 114 } 115 116 return (EINVAL); 117 } 118 119 static int 120 riscv_timer_et_stop(struct eventtimer *et) 121 { 122 123 /* TODO */ 124 125 return (0); 126 } 127 128 static int 129 riscv_timer_intr(void *arg) 130 { 131 struct riscv_timer_softc *sc; 132 133 sc = (struct riscv_timer_softc *)arg; 134 135 csr_clear(sip, SIP_STIP); 136 137 if (sc->et.et_active) 138 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 139 140 return (FILTER_HANDLED); 141 } 142 143 static int 144 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 145 { 146 phandle_t node; 147 int len; 148 149 node = OF_finddevice("/cpus"); 150 if (node == -1) { 151 if (bootverbose) 152 device_printf(dev, "Can't find cpus node.\n"); 153 return (ENXIO); 154 } 155 156 len = OF_getproplen(node, "timebase-frequency"); 157 if (len != 4) { 158 if (bootverbose) 159 device_printf(dev, 160 "Can't find timebase-frequency property.\n"); 161 return (ENXIO); 162 } 163 164 OF_getencprop(node, "timebase-frequency", freq, len); 165 166 return (0); 167 } 168 169 static int 170 riscv_timer_probe(device_t dev) 171 { 172 173 device_set_desc(dev, "RISC-V Timer"); 174 175 return (BUS_PROBE_DEFAULT); 176 } 177 178 static int 179 riscv_timer_attach(device_t dev) 180 { 181 struct riscv_timer_softc *sc; 182 int error; 183 184 sc = device_get_softc(dev); 185 if (riscv_timer_sc != NULL) 186 return (ENXIO); 187 188 if (device_get_unit(dev) != 0) 189 return (ENXIO); 190 191 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 192 device_printf(dev, "No clock frequency specified\n"); 193 return (ENXIO); 194 } 195 196 riscv_timer_sc = sc; 197 198 /* Setup IRQs handler */ 199 error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr, 200 NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih); 201 if (error) { 202 device_printf(dev, "Unable to alloc int resource.\n"); 203 return (ENXIO); 204 } 205 206 riscv_timer_timecount.tc_frequency = sc->clkfreq; 207 riscv_timer_timecount.tc_priv = sc; 208 tc_init(&riscv_timer_timecount); 209 210 sc->et.et_name = "RISC-V Eventtimer"; 211 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 212 sc->et.et_quality = 1000; 213 214 sc->et.et_frequency = sc->clkfreq; 215 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 216 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 217 sc->et.et_start = riscv_timer_et_start; 218 sc->et.et_stop = riscv_timer_et_stop; 219 sc->et.et_priv = sc; 220 et_register(&sc->et); 221 222 return (0); 223 } 224 225 static device_method_t riscv_timer_methods[] = { 226 DEVMETHOD(device_probe, riscv_timer_probe), 227 DEVMETHOD(device_attach, riscv_timer_attach), 228 { 0, 0 } 229 }; 230 231 static driver_t riscv_timer_driver = { 232 "timer", 233 riscv_timer_methods, 234 sizeof(struct riscv_timer_softc), 235 }; 236 237 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0, 238 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 239 240 void 241 DELAY(int usec) 242 { 243 int64_t counts, counts_per_usec; 244 uint64_t first, last; 245 246 /* 247 * Check the timers are setup, if not just 248 * use a for loop for the meantime 249 */ 250 if (riscv_timer_sc == NULL) { 251 for (; usec > 0; usec--) 252 for (counts = 200; counts > 0; counts--) 253 /* 254 * Prevent the compiler from optimizing 255 * out the loop 256 */ 257 cpufunc_nullop(); 258 return; 259 } 260 TSENTER(); 261 262 /* Get the number of times to count */ 263 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 264 265 /* 266 * Clamp the timeout at a maximum value (about 32 seconds with 267 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 268 * near that length of time and if they are, they should be hung 269 * out to dry. 270 */ 271 if (usec >= (0x80000000U / counts_per_usec)) 272 counts = (0x80000000U / counts_per_usec) - 1; 273 else 274 counts = usec * counts_per_usec; 275 276 first = get_timecount(); 277 278 while (counts > 0) { 279 last = get_timecount(); 280 counts -= (int64_t)(last - first); 281 first = last; 282 } 283 TSEXIT(); 284 } 285