1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/malloc.h> 50 #include <sys/rman.h> 51 #include <sys/timeet.h> 52 #include <sys/timetc.h> 53 #include <sys/watchdog.h> 54 55 #include <sys/proc.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/intr.h> 60 #include <machine/asm.h> 61 #include <machine/trap.h> 62 #include <machine/sbi.h> 63 64 #define DEFAULT_FREQ 10000000 65 66 #define TIMER_COUNTS 0x00 67 #define TIMER_MTIMECMP(cpu) (cpu * 8) 68 69 struct riscv_timer_softc { 70 void *ih; 71 uint32_t clkfreq; 72 struct eventtimer et; 73 int intr_rid; 74 struct resource *intr_res; 75 }; 76 77 static struct riscv_timer_softc *riscv_timer_sc = NULL; 78 79 static timecounter_get_t riscv_timer_get_timecount; 80 81 static struct timecounter riscv_timer_timecount = { 82 .tc_name = "RISC-V Timecounter", 83 .tc_get_timecount = riscv_timer_get_timecount, 84 .tc_poll_pps = NULL, 85 .tc_counter_mask = ~0u, 86 .tc_frequency = 0, 87 .tc_quality = 1000, 88 }; 89 90 static inline uint64_t 91 get_cycles(void) 92 { 93 uint64_t cycles; 94 95 __asm __volatile("rdtime %0" : "=r" (cycles)); 96 97 return (cycles); 98 } 99 100 static long 101 get_counts(struct riscv_timer_softc *sc) 102 { 103 uint64_t counts; 104 105 counts = get_cycles(); 106 107 return (counts); 108 } 109 110 static unsigned 111 riscv_timer_get_timecount(struct timecounter *tc) 112 { 113 struct riscv_timer_softc *sc; 114 115 sc = tc->tc_priv; 116 117 return (get_counts(sc)); 118 } 119 120 static int 121 riscv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 122 { 123 uint64_t counts; 124 125 if (first != 0) { 126 counts = ((uint32_t)et->et_frequency * first) >> 32; 127 sbi_set_timer(get_cycles() + counts); 128 csr_set(sie, SIE_STIE); 129 130 return (0); 131 } 132 133 return (EINVAL); 134 135 } 136 137 static int 138 riscv_timer_stop(struct eventtimer *et) 139 { 140 141 /* TODO */ 142 143 return (0); 144 } 145 146 static int 147 riscv_timer_intr(void *arg) 148 { 149 struct riscv_timer_softc *sc; 150 151 sc = (struct riscv_timer_softc *)arg; 152 153 csr_clear(sip, SIP_STIP); 154 155 if (sc->et.et_active) 156 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 157 158 return (FILTER_HANDLED); 159 } 160 161 static int 162 riscv_timer_probe(device_t dev) 163 { 164 165 device_set_desc(dev, "RISC-V Timer"); 166 167 return (BUS_PROBE_DEFAULT); 168 } 169 170 static int 171 riscv_timer_attach(device_t dev) 172 { 173 struct riscv_timer_softc *sc; 174 int error; 175 176 sc = device_get_softc(dev); 177 if (riscv_timer_sc) 178 return (ENXIO); 179 180 if (device_get_unit(dev) != 0) 181 return ENXIO; 182 183 sc->clkfreq = DEFAULT_FREQ; 184 if (sc->clkfreq == 0) { 185 device_printf(dev, "No clock frequency specified\n"); 186 return (ENXIO); 187 } 188 189 riscv_timer_sc = sc; 190 191 sc->intr_rid = 0; 192 sc->intr_res = bus_alloc_resource(dev, 193 SYS_RES_IRQ, &sc->intr_rid, IRQ_TIMER_SUPERVISOR, 194 IRQ_TIMER_SUPERVISOR, 1, RF_ACTIVE); 195 if (sc->intr_res == NULL) { 196 device_printf(dev, "failed to allocate irq\n"); 197 return (ENXIO); 198 } 199 200 /* Setup IRQs handler */ 201 error = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 202 riscv_timer_intr, NULL, sc, &sc->ih); 203 if (error) { 204 device_printf(dev, "Unable to alloc int resource.\n"); 205 return (ENXIO); 206 } 207 208 riscv_timer_timecount.tc_frequency = sc->clkfreq; 209 riscv_timer_timecount.tc_priv = sc; 210 tc_init(&riscv_timer_timecount); 211 212 sc->et.et_name = "RISC-V Eventtimer"; 213 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 214 sc->et.et_quality = 1000; 215 216 sc->et.et_frequency = sc->clkfreq; 217 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 218 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 219 sc->et.et_start = riscv_timer_start; 220 sc->et.et_stop = riscv_timer_stop; 221 sc->et.et_priv = sc; 222 et_register(&sc->et); 223 224 return (0); 225 } 226 227 static device_method_t riscv_timer_methods[] = { 228 DEVMETHOD(device_probe, riscv_timer_probe), 229 DEVMETHOD(device_attach, riscv_timer_attach), 230 { 0, 0 } 231 }; 232 233 static driver_t riscv_timer_driver = { 234 "timer", 235 riscv_timer_methods, 236 sizeof(struct riscv_timer_softc), 237 }; 238 239 static devclass_t riscv_timer_devclass; 240 241 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, riscv_timer_devclass, 242 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 243 244 void 245 DELAY(int usec) 246 { 247 int64_t counts, counts_per_usec; 248 uint64_t first, last; 249 250 /* 251 * Check the timers are setup, if not just 252 * use a for loop for the meantime 253 */ 254 if (riscv_timer_sc == NULL) { 255 for (; usec > 0; usec--) 256 for (counts = 200; counts > 0; counts--) 257 /* 258 * Prevent the compiler from optimizing 259 * out the loop 260 */ 261 cpufunc_nullop(); 262 return; 263 } 264 TSENTER(); 265 266 /* Get the number of times to count */ 267 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 268 269 /* 270 * Clamp the timeout at a maximum value (about 32 seconds with 271 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 272 * near that length of time and if they are, they should be hung 273 * out to dry. 274 */ 275 if (usec >= (0x80000000U / counts_per_usec)) 276 counts = (0x80000000U / counts_per_usec) - 1; 277 else 278 counts = usec * counts_per_usec; 279 280 first = get_counts(riscv_timer_sc); 281 282 while (counts > 0) { 283 last = get_counts(riscv_timer_sc); 284 counts -= (int64_t)(last - first); 285 first = last; 286 } 287 TSEXIT(); 288 } 289