1 /*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * RISC-V Timer 37 */ 38 39 #include "opt_platform.h" 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/malloc.h> 50 #include <sys/rman.h> 51 #include <sys/timeet.h> 52 #include <sys/timetc.h> 53 #include <sys/watchdog.h> 54 55 #include <sys/proc.h> 56 57 #include <machine/bus.h> 58 #include <machine/cpu.h> 59 #include <machine/cpufunc.h> 60 #include <machine/intr.h> 61 #include <machine/asm.h> 62 #include <machine/trap.h> 63 #include <machine/sbi.h> 64 65 #include <dev/fdt/fdt_common.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 #include <dev/ofw/openfirm.h> 69 70 #define TIMER_COUNTS 0x00 71 #define TIMER_MTIMECMP(cpu) (cpu * 8) 72 73 struct riscv_timer_softc { 74 void *ih; 75 uint32_t clkfreq; 76 struct eventtimer et; 77 }; 78 79 static struct riscv_timer_softc *riscv_timer_sc = NULL; 80 81 static timecounter_get_t riscv_timer_get_timecount; 82 83 static struct timecounter riscv_timer_timecount = { 84 .tc_name = "RISC-V Timecounter", 85 .tc_get_timecount = riscv_timer_get_timecount, 86 .tc_poll_pps = NULL, 87 .tc_counter_mask = ~0u, 88 .tc_frequency = 0, 89 .tc_quality = 1000, 90 }; 91 92 static inline uint64_t 93 get_cycles(void) 94 { 95 96 return (rdtime()); 97 } 98 99 static long 100 get_counts(struct riscv_timer_softc *sc) 101 { 102 uint64_t counts; 103 104 counts = get_cycles(); 105 106 return (counts); 107 } 108 109 static unsigned 110 riscv_timer_get_timecount(struct timecounter *tc) 111 { 112 struct riscv_timer_softc *sc; 113 114 sc = tc->tc_priv; 115 116 return (get_counts(sc)); 117 } 118 119 static int 120 riscv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 121 { 122 uint64_t counts; 123 124 if (first != 0) { 125 counts = ((uint32_t)et->et_frequency * first) >> 32; 126 sbi_set_timer(get_cycles() + counts); 127 csr_set(sie, SIE_STIE); 128 129 return (0); 130 } 131 132 return (EINVAL); 133 134 } 135 136 static int 137 riscv_timer_stop(struct eventtimer *et) 138 { 139 140 /* TODO */ 141 142 return (0); 143 } 144 145 static int 146 riscv_timer_intr(void *arg) 147 { 148 struct riscv_timer_softc *sc; 149 150 sc = (struct riscv_timer_softc *)arg; 151 152 csr_clear(sip, SIP_STIP); 153 154 if (sc->et.et_active) 155 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 156 157 return (FILTER_HANDLED); 158 } 159 160 static int 161 riscv_timer_get_timebase(device_t dev, uint32_t *freq) 162 { 163 phandle_t node; 164 int len; 165 166 node = OF_finddevice("/cpus"); 167 if (node == -1) { 168 if (bootverbose) 169 device_printf(dev, "Can't find cpus node.\n"); 170 return (ENXIO); 171 } 172 173 len = OF_getproplen(node, "timebase-frequency"); 174 if (len != 4) { 175 if (bootverbose) 176 device_printf(dev, 177 "Can't find timebase-frequency property.\n"); 178 return (ENXIO); 179 } 180 181 OF_getencprop(node, "timebase-frequency", freq, len); 182 183 return (0); 184 } 185 186 static int 187 riscv_timer_probe(device_t dev) 188 { 189 190 device_set_desc(dev, "RISC-V Timer"); 191 192 return (BUS_PROBE_DEFAULT); 193 } 194 195 static int 196 riscv_timer_attach(device_t dev) 197 { 198 struct riscv_timer_softc *sc; 199 int error; 200 201 sc = device_get_softc(dev); 202 if (riscv_timer_sc) 203 return (ENXIO); 204 205 if (device_get_unit(dev) != 0) 206 return (ENXIO); 207 208 if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) { 209 device_printf(dev, "No clock frequency specified\n"); 210 return (ENXIO); 211 } 212 213 riscv_timer_sc = sc; 214 215 /* Setup IRQs handler */ 216 error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr, 217 NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih); 218 if (error) { 219 device_printf(dev, "Unable to alloc int resource.\n"); 220 return (ENXIO); 221 } 222 223 riscv_timer_timecount.tc_frequency = sc->clkfreq; 224 riscv_timer_timecount.tc_priv = sc; 225 tc_init(&riscv_timer_timecount); 226 227 sc->et.et_name = "RISC-V Eventtimer"; 228 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU; 229 sc->et.et_quality = 1000; 230 231 sc->et.et_frequency = sc->clkfreq; 232 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 233 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 234 sc->et.et_start = riscv_timer_start; 235 sc->et.et_stop = riscv_timer_stop; 236 sc->et.et_priv = sc; 237 et_register(&sc->et); 238 239 return (0); 240 } 241 242 static device_method_t riscv_timer_methods[] = { 243 DEVMETHOD(device_probe, riscv_timer_probe), 244 DEVMETHOD(device_attach, riscv_timer_attach), 245 { 0, 0 } 246 }; 247 248 static driver_t riscv_timer_driver = { 249 "timer", 250 riscv_timer_methods, 251 sizeof(struct riscv_timer_softc), 252 }; 253 254 static devclass_t riscv_timer_devclass; 255 256 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, riscv_timer_devclass, 257 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE); 258 259 void 260 DELAY(int usec) 261 { 262 int64_t counts, counts_per_usec; 263 uint64_t first, last; 264 265 /* 266 * Check the timers are setup, if not just 267 * use a for loop for the meantime 268 */ 269 if (riscv_timer_sc == NULL) { 270 for (; usec > 0; usec--) 271 for (counts = 200; counts > 0; counts--) 272 /* 273 * Prevent the compiler from optimizing 274 * out the loop 275 */ 276 cpufunc_nullop(); 277 return; 278 } 279 TSENTER(); 280 281 /* Get the number of times to count */ 282 counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1); 283 284 /* 285 * Clamp the timeout at a maximum value (about 32 seconds with 286 * a 66MHz clock). *Nobody* should be delay()ing for anywhere 287 * near that length of time and if they are, they should be hung 288 * out to dry. 289 */ 290 if (usec >= (0x80000000U / counts_per_usec)) 291 counts = (0x80000000U / counts_per_usec) - 1; 292 else 293 counts = usec * counts_per_usec; 294 295 first = get_counts(riscv_timer_sc); 296 297 while (counts > 0) { 298 last = get_counts(riscv_timer_sc); 299 counts -= (int64_t)(last - first); 300 first = last; 301 } 302 TSEXIT(); 303 } 304