1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_PMC_H_ 36 #define _SYS_PMC_H_ 37 38 #include <dev/hwpmc/pmc_events.h> 39 #include <sys/proc.h> 40 #include <sys/counter.h> 41 #include <machine/pmc_mdep.h> 42 #include <machine/profile.h> 43 #ifdef _KERNEL 44 #include <sys/epoch.h> 45 #include <ck_queue.h> 46 #endif 47 48 #define PMC_MODULE_NAME "hwpmc" 49 #define PMC_NAME_MAX 64 /* HW counter name size */ 50 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 51 52 /* 53 * Kernel<->userland API version number [MMmmpppp] 54 * 55 * Major numbers are to be incremented when an incompatible change to 56 * the ABI occurs that older clients will not be able to handle. 57 * 58 * Minor numbers are incremented when a backwards compatible change 59 * occurs that allows older correct programs to run unchanged. For 60 * example, when support for a new PMC type is added. 61 * 62 * The patch version is incremented for every bug fix. 63 */ 64 #define PMC_VERSION_MAJOR 0x09 65 #define PMC_VERSION_MINOR 0x03 66 #define PMC_VERSION_PATCH 0x0000 67 68 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 69 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 70 71 #define PMC_CPUID_LEN 64 72 /* cpu model name for pmu lookup */ 73 extern char pmc_cpuid[PMC_CPUID_LEN]; 74 75 /* 76 * Kinds of CPUs known. 77 * 78 * We keep track of CPU variants that need to be distinguished in 79 * some way for PMC operations. CPU names are grouped by manufacturer 80 * and numbered sparsely in order to minimize changes to the ABI involved 81 * when new CPUs are added. 82 * 83 * Please keep the pmc(3) manual page in sync with this list. 84 */ 85 86 #define __PMC_CPUS() \ 87 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 88 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 89 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ 90 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ 91 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ 92 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ 93 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ 94 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ 95 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ 96 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 97 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 98 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 99 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 100 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 101 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 102 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 103 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 104 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 105 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 106 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 107 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 108 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 109 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 110 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 111 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 112 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 113 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 114 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 115 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ 116 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ 117 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ 118 __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ 119 __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ 120 __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ 121 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 122 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 123 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 124 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ 125 __PMC_CPU(MIPS_BERI, 0x203, "BERI") \ 126 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 127 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 128 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 129 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ 130 __PMC_CPU(GENERIC, 0x400, "Generic") \ 131 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 132 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 133 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 134 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 135 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 136 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 137 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 138 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ 139 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") 140 141 enum pmc_cputype { 142 #undef __PMC_CPU 143 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 144 __PMC_CPUS() 145 }; 146 147 #define PMC_CPU_FIRST PMC_CPU_AMD_K7 148 #define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76 149 150 /* 151 * Classes of PMCs 152 */ 153 154 #define __PMC_CLASSES() \ 155 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 156 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ 157 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 158 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \ 159 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \ 160 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \ 161 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 162 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 163 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 164 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 165 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ 166 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ 167 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ 168 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 169 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 170 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 171 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 172 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 173 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ 174 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 175 __PMC_CLASS(BERI, 0x14, "MIPS BERI") \ 176 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ 177 __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \ 178 __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \ 179 __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU") 180 181 enum pmc_class { 182 #undef __PMC_CLASS 183 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 184 __PMC_CLASSES() 185 }; 186 187 #define PMC_CLASS_FIRST PMC_CLASS_TSC 188 #define PMC_CLASS_LAST PMC_CLASS_CMN600_PMU 189 190 /* 191 * A PMC can be in the following states: 192 * 193 * Hardware states: 194 * DISABLED -- administratively prohibited from being used. 195 * FREE -- HW available for use 196 * Software states: 197 * ALLOCATED -- allocated 198 * STOPPED -- allocated, but not counting events 199 * RUNNING -- allocated, and in operation; 'pm_runcount' 200 * holds the number of CPUs using this PMC at 201 * a given instant 202 * DELETED -- being destroyed 203 */ 204 205 #define __PMC_HWSTATES() \ 206 __PMC_STATE(DISABLED) \ 207 __PMC_STATE(FREE) 208 209 #define __PMC_SWSTATES() \ 210 __PMC_STATE(ALLOCATED) \ 211 __PMC_STATE(STOPPED) \ 212 __PMC_STATE(RUNNING) \ 213 __PMC_STATE(DELETED) 214 215 #define __PMC_STATES() \ 216 __PMC_HWSTATES() \ 217 __PMC_SWSTATES() 218 219 enum pmc_state { 220 #undef __PMC_STATE 221 #define __PMC_STATE(S) PMC_STATE_##S, 222 __PMC_STATES() 223 __PMC_STATE(MAX) 224 }; 225 226 #define PMC_STATE_FIRST PMC_STATE_DISABLED 227 #define PMC_STATE_LAST PMC_STATE_DELETED 228 229 /* 230 * An allocated PMC may used as a 'global' counter or as a 231 * 'thread-private' one. Each such mode of use can be in either 232 * statistical sampling mode or in counting mode. Thus a PMC in use 233 * 234 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 235 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 236 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 237 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 238 * 239 * Statistical profiling modes rely on the PMC periodically delivering 240 * a interrupt to the CPU (when the configured number of events have 241 * been measured), so the PMC must have the ability to generate 242 * interrupts. 243 * 244 * In counting modes, the PMC counts its configured events, with the 245 * value of the PMC being read whenever needed by its owner process. 246 * 247 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 248 * to be thread private and count events only when the profiled thread 249 * actually executes on the CPU. 250 * 251 * The system-wide "global" modes keep the PMCs running all the time 252 * and are used to measure the behaviour of the whole system. 253 */ 254 255 #define __PMC_MODES() \ 256 __PMC_MODE(SS, 0) \ 257 __PMC_MODE(SC, 1) \ 258 __PMC_MODE(TS, 2) \ 259 __PMC_MODE(TC, 3) 260 261 enum pmc_mode { 262 #undef __PMC_MODE 263 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 264 __PMC_MODES() 265 }; 266 267 #define PMC_MODE_FIRST PMC_MODE_SS 268 #define PMC_MODE_LAST PMC_MODE_TC 269 270 #define PMC_IS_COUNTING_MODE(mode) \ 271 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 272 #define PMC_IS_SYSTEM_MODE(mode) \ 273 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 274 #define PMC_IS_SAMPLING_MODE(mode) \ 275 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 276 #define PMC_IS_VIRTUAL_MODE(mode) \ 277 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 278 279 /* 280 * PMC row disposition 281 */ 282 283 #define __PMC_DISPOSITIONS(N) \ 284 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 285 __PMC_DISP(FREE) /* free/available */ \ 286 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 287 __PMC_DISP(UNKNOWN) /* sentinel */ 288 289 enum pmc_disp { 290 #undef __PMC_DISP 291 #define __PMC_DISP(D) PMC_DISP_##D , 292 __PMC_DISPOSITIONS() 293 }; 294 295 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 296 #define PMC_DISP_LAST PMC_DISP_THREAD 297 298 /* 299 * Counter capabilities 300 * 301 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 302 */ 303 304 #define __PMC_CAPS() \ 305 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 306 __PMC_CAP(USER, 1, "count user-mode events") \ 307 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 308 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 309 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 310 __PMC_CAP(READ, 5, "read PMC counter") \ 311 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 312 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 313 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 314 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 315 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 316 __PMC_CAP(CASCADE, 11, "cascade counters") \ 317 __PMC_CAP(SYSWIDE, 12, "system wide counter") \ 318 __PMC_CAP(DOMWIDE, 13, "NUMA domain wide counter") 319 320 enum pmc_caps 321 { 322 #undef __PMC_CAP 323 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 324 __PMC_CAPS() 325 }; 326 327 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 328 #define PMC_CAP_LAST PMC_CAP_DOMWIDE 329 330 /* 331 * PMC Event Numbers 332 * 333 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 334 */ 335 336 enum pmc_event { 337 #undef __PMC_EV 338 #undef __PMC_EV_BLOCK 339 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 340 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 341 __PMC_EVENTS() 342 }; 343 344 /* 345 * PMC SYSCALL INTERFACE 346 */ 347 348 /* 349 * "PMC_OPS" -- these are the commands recognized by the kernel 350 * module, and are used when performing a system call from userland. 351 */ 352 #define __PMC_OPS() \ 353 __PMC_OP(CONFIGURELOG, "Set log file") \ 354 __PMC_OP(FLUSHLOG, "Flush log file") \ 355 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 356 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 357 __PMC_OP(GETMODULEVERSION, "Get module version") \ 358 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 359 __PMC_OP(PMCADMIN, "Set PMC state") \ 360 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 361 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 362 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 363 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 364 __PMC_OP(PMCRELEASE, "Release a PMC") \ 365 __PMC_OP(PMCRW, "Read/Set a PMC") \ 366 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 367 __PMC_OP(PMCSTART, "Start a PMC") \ 368 __PMC_OP(PMCSTOP, "Stop a PMC") \ 369 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 370 __PMC_OP(CLOSELOG, "Close log file") \ 371 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 372 373 enum pmc_ops { 374 #undef __PMC_OP 375 #define __PMC_OP(N, D) PMC_OP_##N, 376 __PMC_OPS() 377 }; 378 379 /* 380 * Flags used in operations on PMCs. 381 */ 382 383 #define PMC_F_UNUSED1 0x00000001 /* unused */ 384 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 385 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 386 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 387 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 388 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 389 390 /* V2 API */ 391 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 392 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 393 394 /* internal flags */ 395 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 396 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 397 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 398 399 #define PMC_CALLCHAIN_DEPTH_MAX 512 400 401 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 402 403 /* 404 * Cookies used to denote allocated PMCs, and the values of PMCs. 405 */ 406 407 typedef uint32_t pmc_id_t; 408 typedef uint64_t pmc_value_t; 409 410 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 411 412 /* 413 * PMC IDs have the following format: 414 * 415 * +-----------------------+-------+-----------+ 416 * | CPU | PMC MODE | CLASS | ROW INDEX | 417 * +-----------------------+-------+-----------+ 418 * 419 * where CPU is 12 bits, MODE 4, CLASS 8, and ROW INDEX 8 Field 'CPU' 420 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 421 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 422 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 423 * row index for the PMC. 424 * 425 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 426 * number of hardware PMCs on this cpu. 427 */ 428 429 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 430 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 431 #define PMC_ID_TO_MODE(ID) (((ID) & 0xF0000) >> 16) 432 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 433 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 434 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xF) << 16) | \ 435 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 436 437 /* 438 * Data structures for system calls supported by the pmc driver. 439 */ 440 441 /* 442 * OP PMCALLOCATE 443 * 444 * Allocate a PMC on the named CPU. 445 */ 446 447 #define PMC_CPU_ANY ~0 448 449 struct pmc_op_pmcallocate { 450 uint32_t pm_caps; /* PMC_CAP_* */ 451 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 452 enum pmc_class pm_class; /* class of PMC desired */ 453 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 454 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 455 enum pmc_mode pm_mode; /* desired mode */ 456 pmc_id_t pm_pmcid; /* [return] process pmc id */ 457 pmc_value_t pm_count; /* initial/sample count */ 458 459 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 460 }; 461 462 /* 463 * OP PMCADMIN 464 * 465 * Set the administrative state (i.e., whether enabled or disabled) of 466 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 467 * absolute PMC number and need not have been first allocated by the 468 * calling process. 469 */ 470 471 struct pmc_op_pmcadmin { 472 int pm_cpu; /* CPU# */ 473 uint32_t pm_flags; /* flags */ 474 int pm_pmc; /* PMC# */ 475 enum pmc_state pm_state; /* desired state */ 476 }; 477 478 /* 479 * OP PMCATTACH / OP PMCDETACH 480 * 481 * Attach/detach a PMC and a process. 482 */ 483 484 struct pmc_op_pmcattach { 485 pmc_id_t pm_pmc; /* PMC to attach to */ 486 pid_t pm_pid; /* target process */ 487 }; 488 489 /* 490 * OP PMCSETCOUNT 491 * 492 * Set the sampling rate (i.e., the reload count) for statistical counters. 493 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 494 */ 495 496 struct pmc_op_pmcsetcount { 497 pmc_value_t pm_count; /* initial/sample count */ 498 pmc_id_t pm_pmcid; /* PMC id to set */ 499 }; 500 501 /* 502 * OP PMCRW 503 * 504 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 505 * to have been previously allocated using PMCALLOCATE. 506 */ 507 508 struct pmc_op_pmcrw { 509 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 510 pmc_id_t pm_pmcid; /* pmc id */ 511 pmc_value_t pm_value; /* new&returned value */ 512 }; 513 514 /* 515 * OP GETPMCINFO 516 * 517 * retrieve PMC state for a named CPU. The caller is expected to 518 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 519 * values. 520 */ 521 522 struct pmc_info { 523 char pm_name[PMC_NAME_MAX]; /* pmc name */ 524 enum pmc_class pm_class; /* enum pmc_class */ 525 int pm_enabled; /* whether enabled */ 526 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 527 pid_t pm_ownerpid; /* owner, or -1 */ 528 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 529 enum pmc_event pm_event; /* current event */ 530 uint32_t pm_flags; /* current flags */ 531 pmc_value_t pm_reloadcount; /* sampling counters only */ 532 }; 533 534 struct pmc_op_getpmcinfo { 535 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 536 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 537 }; 538 539 /* 540 * OP GETCPUINFO 541 * 542 * Retrieve system CPU information. 543 */ 544 545 struct pmc_classinfo { 546 enum pmc_class pm_class; /* class id */ 547 uint32_t pm_caps; /* counter capabilities */ 548 uint32_t pm_width; /* width of the PMC */ 549 uint32_t pm_num; /* number of PMCs in class */ 550 }; 551 552 struct pmc_op_getcpuinfo { 553 enum pmc_cputype pm_cputype; /* what kind of CPU */ 554 uint32_t pm_ncpu; /* max CPU number */ 555 uint32_t pm_npmc; /* #PMCs per CPU */ 556 uint32_t pm_nclass; /* #classes of PMCs */ 557 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 558 }; 559 560 /* 561 * OP CONFIGURELOG 562 * 563 * Configure a log file for writing system-wide statistics to. 564 */ 565 566 struct pmc_op_configurelog { 567 int pm_flags; 568 int pm_logfd; /* logfile fd (or -1) */ 569 }; 570 571 /* 572 * OP GETDRIVERSTATS 573 * 574 * Retrieve pmc(4) driver-wide statistics. 575 */ 576 #ifdef _KERNEL 577 struct pmc_driverstats { 578 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 579 counter_u64_t pm_intr_processed; /* #interrupts processed */ 580 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 581 counter_u64_t pm_syscalls; /* #syscalls */ 582 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 583 counter_u64_t pm_buffer_requests; /* #buffer requests */ 584 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 585 counter_u64_t pm_log_sweeps; /* #sample buffer processing 586 passes */ 587 counter_u64_t pm_merges; /* merged k+u */ 588 counter_u64_t pm_overwrites; /* UR overwrites */ 589 }; 590 #endif 591 592 struct pmc_op_getdriverstats { 593 unsigned int pm_intr_ignored; /* #interrupts ignored */ 594 unsigned int pm_intr_processed; /* #interrupts processed */ 595 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 596 unsigned int pm_syscalls; /* #syscalls */ 597 unsigned int pm_syscall_errors; /* #syscalls with errors */ 598 unsigned int pm_buffer_requests; /* #buffer requests */ 599 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 600 unsigned int pm_log_sweeps; /* #sample buffer processing 601 passes */ 602 }; 603 604 /* 605 * OP RELEASE / OP START / OP STOP 606 * 607 * Simple operations on a PMC id. 608 */ 609 610 struct pmc_op_simple { 611 pmc_id_t pm_pmcid; 612 }; 613 614 /* 615 * OP WRITELOG 616 * 617 * Flush the current log buffer and write 4 bytes of user data to it. 618 */ 619 620 struct pmc_op_writelog { 621 uint32_t pm_userdata; 622 }; 623 624 /* 625 * OP GETMSR 626 * 627 * Retrieve the machine specific address associated with the allocated 628 * PMC. This number can be used subsequently with a read-performance-counter 629 * instruction. 630 */ 631 632 struct pmc_op_getmsr { 633 uint32_t pm_msr; /* machine specific address */ 634 pmc_id_t pm_pmcid; /* allocated pmc id */ 635 }; 636 637 /* 638 * OP GETDYNEVENTINFO 639 * 640 * Retrieve a PMC dynamic class events list. 641 */ 642 643 struct pmc_dyn_event_descr { 644 char pm_ev_name[PMC_NAME_MAX]; 645 enum pmc_event pm_ev_code; 646 }; 647 648 struct pmc_op_getdyneventinfo { 649 enum pmc_class pm_class; 650 unsigned int pm_nevent; 651 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 652 }; 653 654 #ifdef _KERNEL 655 656 #include <sys/malloc.h> 657 #include <sys/sysctl.h> 658 #include <sys/_cpuset.h> 659 660 #include <machine/frame.h> 661 662 #define PMC_HASH_SIZE 1024 663 #define PMC_MTXPOOL_SIZE 2048 664 #define PMC_LOG_BUFFER_SIZE 256 665 #define PMC_NLOGBUFFERS_PCPU 32 666 #define PMC_NSAMPLES 256 667 #define PMC_CALLCHAIN_DEPTH 128 668 #define PMC_THREADLIST_MAX 128 669 670 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 671 672 /* 673 * Locking keys 674 * 675 * (b) - pmc_bufferlist_mtx (spin lock) 676 * (k) - pmc_kthread_mtx (sleep lock) 677 * (o) - po->po_mtx (spin lock) 678 * (g) - global_epoch_preempt (epoch) 679 * (p) - pmc_sx (sx) 680 */ 681 682 /* 683 * PMC commands 684 */ 685 686 struct pmc_syscall_args { 687 register_t pmop_code; /* one of PMC_OP_* */ 688 void *pmop_data; /* syscall parameter */ 689 }; 690 691 /* 692 * Interface to processor specific s1tuff 693 */ 694 695 /* 696 * struct pmc_descr 697 * 698 * Machine independent (i.e., the common parts) of a human readable 699 * PMC description. 700 */ 701 702 struct pmc_descr { 703 char pd_name[PMC_NAME_MAX]; /* name */ 704 uint32_t pd_caps; /* capabilities */ 705 enum pmc_class pd_class; /* class of the PMC */ 706 uint32_t pd_width; /* width in bits */ 707 }; 708 709 /* 710 * struct pmc_target 711 * 712 * This structure records all the target processes associated with a 713 * PMC. 714 */ 715 716 struct pmc_target { 717 LIST_ENTRY(pmc_target) pt_next; 718 struct pmc_process *pt_process; /* target descriptor */ 719 }; 720 721 /* 722 * struct pmc 723 * 724 * Describes each allocated PMC. 725 * 726 * Each PMC has precisely one owner, namely the process that allocated 727 * the PMC. 728 * 729 * A PMC may be attached to multiple target processes. The 730 * 'pm_targets' field links all the target processes being monitored 731 * by this PMC. 732 * 733 * The 'pm_savedvalue' field is protected by a mutex. 734 * 735 * On a multi-cpu machine, multiple target threads associated with a 736 * process-virtual PMC could be concurrently executing on different 737 * CPUs. The 'pm_runcount' field is atomically incremented every time 738 * the PMC gets scheduled on a CPU and atomically decremented when it 739 * get descheduled. Deletion of a PMC is only permitted when this 740 * field is '0'. 741 * 742 */ 743 struct pmc_pcpu_state { 744 uint32_t pps_overflowcnt; /* count overflow interrupts */ 745 uint8_t pps_stalled; 746 uint8_t pps_cpustate; 747 } __aligned(CACHE_LINE_SIZE); 748 struct pmc { 749 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 750 LIST_ENTRY(pmc) pm_next; /* owner's list */ 751 752 /* 753 * System-wide PMCs are allocated on a CPU and are not moved 754 * around. For system-wide PMCs we record the CPU the PMC was 755 * allocated on in the 'CPU' field of the pmc ID. 756 * 757 * Virtual PMCs run on whichever CPU is currently executing 758 * their targets' threads. For these PMCs we need to save 759 * their current PMC counter values when they are taken off 760 * CPU. 761 */ 762 763 union { 764 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 765 } pm_gv; 766 767 /* 768 * For sampling mode PMCs, we keep track of the PMC's "reload 769 * count", which is the counter value to be loaded in when 770 * arming the PMC for the next counting session. For counting 771 * modes on PMCs that are read-only (e.g., the x86 TSC), we 772 * keep track of the initial value at the start of 773 * counting-mode operation. 774 */ 775 776 union { 777 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 778 pmc_value_t pm_initial; /* counting PMC modes */ 779 } pm_sc; 780 781 struct pmc_pcpu_state *pm_pcpu_state; 782 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 783 uint32_t pm_caps; /* PMC capabilities */ 784 enum pmc_event pm_event; /* event being measured */ 785 uint32_t pm_flags; /* additional flags PMC_F_... */ 786 struct pmc_owner *pm_owner; /* owner thread state */ 787 counter_u64_t pm_runcount; /* #cpus currently on */ 788 enum pmc_state pm_state; /* current PMC state */ 789 790 /* 791 * The PMC ID field encodes the row-index for the PMC, its 792 * mode, class and the CPU# associated with the PMC. 793 */ 794 795 pmc_id_t pm_id; /* allocated PMC id */ 796 enum pmc_class pm_class; 797 798 /* md extensions */ 799 union pmc_md_pmc pm_md; 800 }; 801 802 /* 803 * Accessor macros for 'struct pmc' 804 */ 805 806 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 807 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 808 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 809 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 810 811 /* 812 * struct pmc_threadpmcstate 813 * 814 * Record per-PMC, per-thread state. 815 */ 816 struct pmc_threadpmcstate { 817 pmc_value_t pt_pmcval; /* per-thread reload count */ 818 }; 819 820 /* 821 * struct pmc_thread 822 * 823 * Record a 'target' thread being profiled. 824 */ 825 struct pmc_thread { 826 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 827 struct thread *pt_td; /* target thread */ 828 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 829 }; 830 831 /* 832 * struct pmc_process 833 * 834 * Record a 'target' process being profiled. 835 * 836 * The target process being profiled could be different from the owner 837 * process which allocated the PMCs. Each target process descriptor 838 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 839 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 840 * array. The size of this structure is thus PMC architecture 841 * dependent. 842 * 843 */ 844 845 struct pmc_targetstate { 846 struct pmc *pp_pmc; /* target PMC */ 847 pmc_value_t pp_pmcval; /* per-process value */ 848 }; 849 850 struct pmc_process { 851 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 852 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 853 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 854 int pp_refcnt; /* reference count */ 855 uint32_t pp_flags; /* flags PMC_PP_* */ 856 struct proc *pp_proc; /* target process */ 857 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 858 }; 859 860 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 861 862 /* 863 * struct pmc_owner 864 * 865 * We associate a PMC with an 'owner' process. 866 * 867 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 868 * lifetime, where NCPUS is the numbers of CPUS in the system and 869 * NHWPMC is the number of hardware PMCs per CPU. These are 870 * maintained in the list headed by the 'po_pmcs' to save on space. 871 * 872 */ 873 874 struct pmc_owner { 875 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 876 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 877 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 878 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 879 struct mtx po_mtx; /* spin lock for (o) */ 880 struct proc *po_owner; /* owner proc */ 881 uint32_t po_flags; /* (k) flags PMC_PO_* */ 882 struct proc *po_kthread; /* (k) helper kthread */ 883 struct file *po_file; /* file reference */ 884 int po_error; /* recorded error */ 885 short po_sscount; /* # SS PMCs owned */ 886 short po_logprocmaps; /* global mappings done */ 887 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 888 }; 889 890 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 891 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 892 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 893 894 /* 895 * struct pmc_hw -- describe the state of the PMC hardware 896 * 897 * When in use, a HW PMC is associated with one allocated 'struct pmc' 898 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 899 * 900 * On an SMP box, one or more HW PMC's in process virtual mode with 901 * the same 'phw_pmc' could be executing on different CPUs. In order 902 * to handle this case correctly, we need to ensure that only 903 * incremental counts get added to the saved value in the associated 904 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 905 * value at the time the hardware is started during this context 906 * switch (i.e., the difference between the new (hardware) count and 907 * the saved count is atomically added to the count field in 'struct 908 * pmc' at context switch time). 909 * 910 */ 911 912 struct pmc_hw { 913 uint32_t phw_state; /* see PHW_* macros below */ 914 struct pmc *phw_pmc; /* current thread PMC */ 915 }; 916 917 #define PMC_PHW_RI_MASK 0x000000FF 918 #define PMC_PHW_CPU_SHIFT 8 919 #define PMC_PHW_CPU_MASK 0x0000FF00 920 #define PMC_PHW_FLAGS_SHIFT 16 921 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 922 923 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 924 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 925 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 926 PMC_PHW_CPU_MASK) 927 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 928 PMC_PHW_CPU_SHIFT) 929 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 930 PMC_PHW_FLAGS_MASK) 931 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 932 PMC_PHW_FLAGS_SHIFT) 933 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 934 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 935 936 /* 937 * struct pmc_sample 938 * 939 * Space for N (tunable) PC samples and associated control data. 940 */ 941 942 struct pmc_sample { 943 uint16_t ps_nsamples; /* callchain depth */ 944 uint16_t ps_nsamples_actual; 945 uint16_t ps_cpu; /* cpu number */ 946 uint16_t ps_flags; /* other flags */ 947 lwpid_t ps_tid; /* thread id */ 948 pid_t ps_pid; /* process PID or -1 */ 949 int ps_ticks; /* ticks at sample time */ 950 /* pad */ 951 struct thread *ps_td; /* which thread */ 952 struct pmc *ps_pmc; /* interrupting PMC */ 953 uintptr_t *ps_pc; /* (const) callchain start */ 954 uint64_t ps_tsc; /* tsc value */ 955 }; 956 957 #define PMC_SAMPLE_FREE ((uint16_t) 0) 958 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 959 960 struct pmc_samplebuffer { 961 volatile uint64_t ps_prodidx; /* producer index */ 962 volatile uint64_t ps_considx; /* consumer index */ 963 uintptr_t *ps_callchains; /* all saved call chains */ 964 struct pmc_sample ps_samples[]; /* array of sample entries */ 965 }; 966 967 #define PMC_CONS_SAMPLE(psb) \ 968 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 969 970 #define PMC_CONS_SAMPLE_OFF(psb, off) \ 971 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 972 973 #define PMC_PROD_SAMPLE(psb) \ 974 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 975 976 /* 977 * struct pmc_cpustate 978 * 979 * A CPU is modelled as a collection of HW PMCs with space for additional 980 * flags. 981 */ 982 983 struct pmc_cpu { 984 uint32_t pc_state; /* physical cpu number + flags */ 985 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 986 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 987 }; 988 989 #define PMC_PCPU_CPU_MASK 0x000000FF 990 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 991 #define PMC_PCPU_FLAGS_SHIFT 8 992 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 993 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 994 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 995 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 996 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 997 998 /* 999 * struct pmc_binding 1000 * 1001 * CPU binding information. 1002 */ 1003 1004 struct pmc_binding { 1005 int pb_bound; /* is bound? */ 1006 int pb_cpu; /* if so, to which CPU */ 1007 u_char pb_priority; /* Thread active priority. */ 1008 }; 1009 1010 struct pmc_mdep; 1011 1012 /* 1013 * struct pmc_classdep 1014 * 1015 * PMC class-dependent operations. 1016 */ 1017 struct pmc_classdep { 1018 uint32_t pcd_caps; /* class capabilities */ 1019 enum pmc_class pcd_class; /* class id */ 1020 int pcd_num; /* number of PMCs */ 1021 int pcd_ri; /* row index of the first PMC in class */ 1022 int pcd_width; /* width of the PMC */ 1023 1024 /* configuring/reading/writing the hardware PMCs */ 1025 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1026 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1027 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); 1028 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); 1029 1030 /* pmc allocation/release */ 1031 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1032 const struct pmc_op_pmcallocate *_a); 1033 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1034 1035 /* starting and stopping PMCs */ 1036 int (*pcd_start_pmc)(int _cpu, int _ri); 1037 int (*pcd_stop_pmc)(int _cpu, int _ri); 1038 1039 /* description */ 1040 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1041 struct pmc **_ppmc); 1042 1043 /* class-dependent initialization & finalization */ 1044 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1045 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1046 1047 /* machine-specific interface */ 1048 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1049 }; 1050 1051 /* 1052 * struct pmc_mdep 1053 * 1054 * Machine dependent bits needed per CPU type. 1055 */ 1056 1057 struct pmc_mdep { 1058 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1059 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1060 uint32_t pmd_nclass; /* number of PMC classes present */ 1061 1062 /* 1063 * Machine dependent methods. 1064 */ 1065 1066 /* per-cpu initialization and finalization */ 1067 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1068 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1069 1070 /* thread context switch in/out */ 1071 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1072 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1073 1074 /* handle a PMC interrupt */ 1075 int (*pmd_intr)(struct trapframe *_tf); 1076 1077 /* 1078 * PMC class dependent information. 1079 */ 1080 struct pmc_classdep pmd_classdep[]; 1081 }; 1082 1083 /* 1084 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1085 * to struct pmc_cpu descriptors. 1086 */ 1087 1088 extern struct pmc_cpu **pmc_pcpu; 1089 1090 /* driver statistics */ 1091 extern struct pmc_driverstats pmc_stats; 1092 1093 #if defined(HWPMC_DEBUG) 1094 #include <sys/ktr.h> 1095 1096 /* debug flags, major flag groups */ 1097 struct pmc_debugflags { 1098 int pdb_CPU; 1099 int pdb_CSW; 1100 int pdb_LOG; 1101 int pdb_MDP; 1102 int pdb_MOD; 1103 int pdb_OWN; 1104 int pdb_PMC; 1105 int pdb_PRC; 1106 int pdb_SAM; 1107 }; 1108 1109 extern struct pmc_debugflags pmc_debugflags; 1110 1111 #define KTR_PMC KTR_SUBSYS 1112 1113 #define PMC_DEBUG_STRSIZE 128 1114 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1115 1116 #define PMCDBG0(M, N, L, F) do { \ 1117 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1118 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1119 } while (0) 1120 #define PMCDBG1(M, N, L, F, p1) do { \ 1121 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1122 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1123 } while (0) 1124 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1125 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1126 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1127 } while (0) 1128 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1129 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1130 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1131 } while (0) 1132 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1133 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1134 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1135 } while (0) 1136 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1137 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1138 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1139 p5); \ 1140 } while (0) 1141 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1142 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1143 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1144 p5, p6); \ 1145 } while (0) 1146 1147 /* Major numbers */ 1148 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1149 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1150 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1151 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1152 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1153 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1154 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1155 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1156 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1157 1158 /* Minor numbers */ 1159 1160 /* Common (8 bits) */ 1161 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1162 #define PMC_DEBUG_MIN_REL 1 /* release */ 1163 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1164 #define PMC_DEBUG_MIN_INI 3 /* init */ 1165 #define PMC_DEBUG_MIN_FND 4 /* find */ 1166 1167 /* MODULE */ 1168 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1169 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1170 1171 /* OWN */ 1172 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1173 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1174 1175 /* PROCESSES */ 1176 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1177 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1178 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1179 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1180 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1181 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1182 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1183 1184 /* CONTEXT SWITCHES */ 1185 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1186 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1187 1188 /* PMC */ 1189 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1190 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1191 1192 /* MACHINE DEPENDENT LAYER */ 1193 #define PMC_DEBUG_MIN_REA 8 /* read */ 1194 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1195 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1196 #define PMC_DEBUG_MIN_STA 11 /* start */ 1197 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1198 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1199 1200 /* CPU */ 1201 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1202 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1203 1204 /* LOG */ 1205 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1206 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1207 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1208 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1209 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1210 1211 #else 1212 #define PMCDBG0(M, N, L, F) /* nothing */ 1213 #define PMCDBG1(M, N, L, F, p1) 1214 #define PMCDBG2(M, N, L, F, p1, p2) 1215 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1216 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1217 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1218 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1219 #endif 1220 1221 /* declare a dedicated memory pool */ 1222 MALLOC_DECLARE(M_PMC); 1223 1224 /* 1225 * Functions 1226 */ 1227 1228 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1229 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1230 int pmc_getrowdisp(int _ri); 1231 int pmc_process_interrupt(int _ring, struct pmc *_pm, struct trapframe *_tf); 1232 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1233 struct trapframe *_tf); 1234 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1235 struct trapframe *_tf); 1236 void pmc_restore_cpu_binding(struct pmc_binding *pb); 1237 void pmc_save_cpu_binding(struct pmc_binding *pb); 1238 void pmc_select_cpu(int cpu); 1239 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1240 void pmc_mdep_free(struct pmc_mdep *md); 1241 uint64_t pmc_rdtsc(void); 1242 #endif /* _KERNEL */ 1243 #endif /* _SYS_PMC_H_ */ 1244