1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _X86_APICVAR_H_ 32 #define _X86_APICVAR_H_ 33 34 /* 35 * Local && I/O APIC variable definitions. 36 */ 37 38 /* 39 * Layout of local APIC interrupt vectors: 40 * 41 * 0xff (255) +-------------+ 42 * | | 15 (Spurious / IPIs / Local Interrupts) 43 * 0xf0 (240) +-------------+ 44 * | | 14 (I/O Interrupts / Timer) 45 * 0xe0 (224) +-------------+ 46 * | | 13 (I/O Interrupts) 47 * 0xd0 (208) +-------------+ 48 * | | 12 (I/O Interrupts) 49 * 0xc0 (192) +-------------+ 50 * | | 11 (I/O Interrupts) 51 * 0xb0 (176) +-------------+ 52 * | | 10 (I/O Interrupts) 53 * 0xa0 (160) +-------------+ 54 * | | 9 (I/O Interrupts) 55 * 0x90 (144) +-------------+ 56 * | | 8 (I/O Interrupts / System Calls) 57 * 0x80 (128) +-------------+ 58 * | | 7 (I/O Interrupts) 59 * 0x70 (112) +-------------+ 60 * | | 6 (I/O Interrupts) 61 * 0x60 (96) +-------------+ 62 * | | 5 (I/O Interrupts) 63 * 0x50 (80) +-------------+ 64 * | | 4 (I/O Interrupts) 65 * 0x40 (64) +-------------+ 66 * | | 3 (I/O Interrupts) 67 * 0x30 (48) +-------------+ 68 * | | 2 (ATPIC Interrupts) 69 * 0x20 (32) +-------------+ 70 * | | 1 (Exceptions, traps, faults, etc.) 71 * 0x10 (16) +-------------+ 72 * | | 0 (Exceptions, traps, faults, etc.) 73 * 0x00 (0) +-------------+ 74 * 75 * Note: 0x80 needs to be handled specially and not allocated to an 76 * I/O device! 77 */ 78 79 #define xAPIC_MAX_APIC_ID 0xfe 80 #define xAPIC_ID_ALL 0xff 81 #define MAX_APIC_ID 0x200 82 #define APIC_ID_ALL 0xffffffff 83 84 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID 85 86 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 87 #define APIC_IO_INTS (IDT_IO_INTS + 16) 88 #define APIC_NUM_IOINTS 191 89 90 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 91 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 92 93 /* 94 ********************* !!! WARNING !!! ****************************** 95 * Each local apic has an interrupt receive fifo that is two entries deep 96 * for each interrupt priority class (higher 4 bits of interrupt vector). 97 * Once the fifo is full the APIC can no longer receive interrupts for this 98 * class and sending IPIs from other CPUs will be blocked. 99 * To avoid deadlocks there should be no more than two IPI interrupts 100 * pending at the same time. 101 * Currently this is guaranteed by dividing the IPIs in two groups that have 102 * each at most one IPI interrupt pending. The first group is protected by the 103 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 104 * at a time) The second group uses a single interrupt and a bitmap to avoid 105 * redundant IPI interrupts. 106 */ 107 108 /* Interrupts for local APIC LVT entries other than the timer. */ 109 #define APIC_LOCAL_INTS 240 110 #define APIC_ERROR_INT APIC_LOCAL_INTS 111 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 112 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 113 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 114 115 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 116 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 117 #define IPI_INVLPG (APIC_IPI_INTS + 2) 118 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 119 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 120 /* Vector to handle bitmap based IPIs */ 121 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 122 123 /* IPIs handled by IPI_BITMAP_VECTOR */ 124 #define IPI_AST 0 /* Generate software trap. */ 125 #define IPI_PREEMPT 1 126 #define IPI_HARDCLOCK 2 127 #define IPI_BITMAP_LAST IPI_HARDCLOCK 128 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 129 130 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 131 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 132 #define IPI_DYN_FIRST (APIC_IPI_INTS + 8) 133 #define IPI_DYN_LAST (253) /* IPIs allocated at runtime */ 134 135 /* 136 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 137 * it is delivered using an NMI anyways. 138 */ 139 #define IPI_NMI_FIRST 254 140 #define IPI_TRACE 254 /* Interrupt for tracing. */ 141 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 142 143 /* 144 * The spurious interrupt can share the priority class with the IPIs since 145 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 146 */ 147 #define APIC_SPURIOUS_INT 255 148 149 #ifndef LOCORE 150 151 #define APIC_IPI_DEST_SELF -1 152 #define APIC_IPI_DEST_ALL -2 153 #define APIC_IPI_DEST_OTHERS -3 154 155 #define APIC_BUS_UNKNOWN -1 156 #define APIC_BUS_ISA 0 157 #define APIC_BUS_EISA 1 158 #define APIC_BUS_PCI 2 159 #define APIC_BUS_MAX APIC_BUS_PCI 160 161 #define IRQ_EXTINT -1 162 #define IRQ_NMI -2 163 #define IRQ_SMI -3 164 #define IRQ_DISABLED -4 165 166 /* 167 * An APIC enumerator is a pseudo bus driver that enumerates APIC's including 168 * CPU's and I/O APIC's. 169 */ 170 struct apic_enumerator { 171 const char *apic_name; 172 int (*apic_probe)(void); 173 int (*apic_probe_cpus)(void); 174 int (*apic_setup_local)(void); 175 int (*apic_setup_io)(void); 176 SLIST_ENTRY(apic_enumerator) apic_next; 177 }; 178 179 inthand_t 180 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 181 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 182 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 183 IDTVEC(spuriousint), IDTVEC(timerint), 184 IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti), 185 IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti), 186 IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti), 187 IDTVEC(spuriousint_pti), IDTVEC(timerint_pti); 188 189 extern vm_paddr_t lapic_paddr; 190 extern int *apic_cpuids; 191 192 void apic_register_enumerator(struct apic_enumerator *enumerator); 193 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 194 int ioapic_disable_pin(void *cookie, u_int pin); 195 int ioapic_get_vector(void *cookie, u_int pin); 196 void ioapic_register(void *cookie); 197 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 198 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 199 int ioapic_set_extint(void *cookie, u_int pin); 200 int ioapic_set_nmi(void *cookie, u_int pin); 201 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 202 int ioapic_set_triggermode(void *cookie, u_int pin, 203 enum intr_trigger trigger); 204 int ioapic_set_smi(void *cookie, u_int pin); 205 206 /* 207 * Struct containing pointers to APIC functions whose 208 * implementation is run time selectable. 209 */ 210 struct apic_ops { 211 void (*create)(u_int, int); 212 void (*init)(vm_paddr_t); 213 void (*xapic_mode)(void); 214 bool (*is_x2apic)(void); 215 void (*setup)(int); 216 void (*dump)(const char *); 217 void (*disable)(void); 218 void (*eoi)(void); 219 int (*id)(void); 220 int (*intr_pending)(u_int); 221 void (*set_logical_id)(u_int, u_int, u_int); 222 u_int (*cpuid)(u_int); 223 224 /* Vectors */ 225 u_int (*alloc_vector)(u_int, u_int); 226 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 227 void (*enable_vector)(u_int, u_int); 228 void (*disable_vector)(u_int, u_int); 229 void (*free_vector)(u_int, u_int, u_int); 230 231 232 /* PMC */ 233 int (*enable_pmc)(void); 234 void (*disable_pmc)(void); 235 void (*reenable_pmc)(void); 236 237 /* CMC */ 238 void (*enable_cmc)(void); 239 240 /* AMD ELVT */ 241 int (*enable_mca_elvt)(void); 242 243 /* IPI */ 244 void (*ipi_raw)(register_t, u_int); 245 void (*ipi_vectored)(u_int, int); 246 int (*ipi_wait)(int); 247 int (*ipi_alloc)(inthand_t *ipifunc); 248 void (*ipi_free)(int vector); 249 250 /* LVT */ 251 int (*set_lvt_mask)(u_int, u_int, u_char); 252 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 253 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 254 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 255 }; 256 257 extern struct apic_ops apic_ops; 258 259 static inline void 260 lapic_create(u_int apic_id, int boot_cpu) 261 { 262 263 apic_ops.create(apic_id, boot_cpu); 264 } 265 266 static inline void 267 lapic_init(vm_paddr_t addr) 268 { 269 270 apic_ops.init(addr); 271 } 272 273 static inline void 274 lapic_xapic_mode(void) 275 { 276 277 apic_ops.xapic_mode(); 278 } 279 280 static inline bool 281 lapic_is_x2apic(void) 282 { 283 284 return (apic_ops.is_x2apic()); 285 } 286 287 static inline void 288 lapic_setup(int boot) 289 { 290 291 apic_ops.setup(boot); 292 } 293 294 static inline void 295 lapic_dump(const char *str) 296 { 297 298 apic_ops.dump(str); 299 } 300 301 static inline void 302 lapic_disable(void) 303 { 304 305 apic_ops.disable(); 306 } 307 308 static inline void 309 lapic_eoi(void) 310 { 311 312 apic_ops.eoi(); 313 } 314 315 static inline int 316 lapic_id(void) 317 { 318 319 return (apic_ops.id()); 320 } 321 322 static inline int 323 lapic_intr_pending(u_int vector) 324 { 325 326 return (apic_ops.intr_pending(vector)); 327 } 328 329 /* XXX: UNUSED */ 330 static inline void 331 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 332 { 333 334 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 335 } 336 337 static inline u_int 338 apic_cpuid(u_int apic_id) 339 { 340 341 return (apic_ops.cpuid(apic_id)); 342 } 343 344 static inline u_int 345 apic_alloc_vector(u_int apic_id, u_int irq) 346 { 347 348 return (apic_ops.alloc_vector(apic_id, irq)); 349 } 350 351 static inline u_int 352 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 353 { 354 355 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 356 } 357 358 static inline void 359 apic_enable_vector(u_int apic_id, u_int vector) 360 { 361 362 apic_ops.enable_vector(apic_id, vector); 363 } 364 365 static inline void 366 apic_disable_vector(u_int apic_id, u_int vector) 367 { 368 369 apic_ops.disable_vector(apic_id, vector); 370 } 371 372 static inline void 373 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 374 { 375 376 apic_ops.free_vector(apic_id, vector, irq); 377 } 378 379 static inline int 380 lapic_enable_pmc(void) 381 { 382 383 return (apic_ops.enable_pmc()); 384 } 385 386 static inline void 387 lapic_disable_pmc(void) 388 { 389 390 apic_ops.disable_pmc(); 391 } 392 393 static inline void 394 lapic_reenable_pmc(void) 395 { 396 397 apic_ops.reenable_pmc(); 398 } 399 400 static inline void 401 lapic_enable_cmc(void) 402 { 403 404 apic_ops.enable_cmc(); 405 } 406 407 static inline int 408 lapic_enable_mca_elvt(void) 409 { 410 411 return (apic_ops.enable_mca_elvt()); 412 } 413 414 static inline void 415 lapic_ipi_raw(register_t icrlo, u_int dest) 416 { 417 418 apic_ops.ipi_raw(icrlo, dest); 419 } 420 421 static inline void 422 lapic_ipi_vectored(u_int vector, int dest) 423 { 424 425 apic_ops.ipi_vectored(vector, dest); 426 } 427 428 static inline int 429 lapic_ipi_wait(int delay) 430 { 431 432 return (apic_ops.ipi_wait(delay)); 433 } 434 435 static inline int 436 lapic_ipi_alloc(inthand_t *ipifunc) 437 { 438 439 return (apic_ops.ipi_alloc(ipifunc)); 440 } 441 442 static inline void 443 lapic_ipi_free(int vector) 444 { 445 446 return (apic_ops.ipi_free(vector)); 447 } 448 449 static inline int 450 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 451 { 452 453 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 454 } 455 456 static inline int 457 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 458 { 459 460 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 461 } 462 463 static inline int 464 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 465 { 466 467 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 468 } 469 470 static inline int 471 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 472 { 473 474 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 475 } 476 477 void lapic_handle_cmc(void); 478 void lapic_handle_error(void); 479 void lapic_handle_intr(int vector, struct trapframe *frame); 480 void lapic_handle_timer(struct trapframe *frame); 481 482 int ioapic_get_rid(u_int apic_id, uint16_t *ridp); 483 484 extern int x2apic_mode; 485 extern int lapic_eoi_suppression; 486 487 #ifdef _SYS_SYSCTL_H_ 488 SYSCTL_DECL(_hw_apic); 489 #endif 490 491 #endif /* !LOCORE */ 492 #endif /* _X86_APICVAR_H_ */ 493