1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _X86_APICVAR_H_ 30 #define _X86_APICVAR_H_ 31 32 /* 33 * Local && I/O APIC variable definitions. 34 */ 35 36 /* 37 * Layout of local APIC interrupt vectors: 38 * 39 * 0xff (255) +-------------+ 40 * | | 15 (Spurious / IPIs / Local Interrupts) 41 * 0xf0 (240) +-------------+ 42 * | | 14 (I/O Interrupts / Timer) 43 * 0xe0 (224) +-------------+ 44 * | | 13 (I/O Interrupts) 45 * 0xd0 (208) +-------------+ 46 * | | 12 (I/O Interrupts) 47 * 0xc0 (192) +-------------+ 48 * | | 11 (I/O Interrupts) 49 * 0xb0 (176) +-------------+ 50 * | | 10 (I/O Interrupts) 51 * 0xa0 (160) +-------------+ 52 * | | 9 (I/O Interrupts) 53 * 0x90 (144) +-------------+ 54 * | | 8 (I/O Interrupts / System Calls) 55 * 0x80 (128) +-------------+ 56 * | | 7 (I/O Interrupts) 57 * 0x70 (112) +-------------+ 58 * | | 6 (I/O Interrupts) 59 * 0x60 (96) +-------------+ 60 * | | 5 (I/O Interrupts) 61 * 0x50 (80) +-------------+ 62 * | | 4 (I/O Interrupts) 63 * 0x40 (64) +-------------+ 64 * | | 3 (I/O Interrupts) 65 * 0x30 (48) +-------------+ 66 * | | 2 (ATPIC Interrupts) 67 * 0x20 (32) +-------------+ 68 * | | 1 (Exceptions, traps, faults, etc.) 69 * 0x10 (16) +-------------+ 70 * | | 0 (Exceptions, traps, faults, etc.) 71 * 0x00 (0) +-------------+ 72 * 73 * Note: 0x80 needs to be handled specially and not allocated to an 74 * I/O device! 75 */ 76 77 #define MAX_APIC_ID 0xfe 78 #define APIC_ID_ALL 0xff 79 80 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 81 #define APIC_IO_INTS (IDT_IO_INTS + 16) 82 #define APIC_NUM_IOINTS 191 83 84 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 85 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 86 87 /* 88 ********************* !!! WARNING !!! ****************************** 89 * Each local apic has an interrupt receive fifo that is two entries deep 90 * for each interrupt priority class (higher 4 bits of interrupt vector). 91 * Once the fifo is full the APIC can no longer receive interrupts for this 92 * class and sending IPIs from other CPUs will be blocked. 93 * To avoid deadlocks there should be no more than two IPI interrupts 94 * pending at the same time. 95 * Currently this is guaranteed by dividing the IPIs in two groups that have 96 * each at most one IPI interrupt pending. The first group is protected by the 97 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 98 * at a time) The second group uses a single interrupt and a bitmap to avoid 99 * redundant IPI interrupts. 100 */ 101 102 /* Interrupts for local APIC LVT entries other than the timer. */ 103 #define APIC_LOCAL_INTS 240 104 #define APIC_ERROR_INT APIC_LOCAL_INTS 105 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 106 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 107 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 108 109 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 110 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 111 #define IPI_INVLPG (APIC_IPI_INTS + 2) 112 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 113 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 114 /* Vector to handle bitmap based IPIs */ 115 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 116 117 /* IPIs handled by IPI_BITMAP_VECTOR */ 118 #define IPI_AST 0 /* Generate software trap. */ 119 #define IPI_PREEMPT 1 120 #define IPI_HARDCLOCK 2 121 #define IPI_BITMAP_LAST IPI_HARDCLOCK 122 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 123 124 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 125 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 126 #ifdef __i386__ 127 #define IPI_LAZYPMAP (APIC_IPI_INTS + 8) /* Lazy pmap release. */ 128 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9) 129 #else 130 #define IPI_DYN_FIRST (APIC_IPI_INTS + 8) 131 #endif 132 #define IPI_DYN_LAST (253) /* IPIs allocated at runtime */ 133 134 /* 135 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 136 * it is delivered using an NMI anyways. 137 */ 138 #define IPI_NMI_FIRST 254 139 #define IPI_TRACE 254 /* Interrupt for tracing. */ 140 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 141 142 /* 143 * The spurious interrupt can share the priority class with the IPIs since 144 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 145 */ 146 #define APIC_SPURIOUS_INT 255 147 148 #ifndef LOCORE 149 150 #define APIC_IPI_DEST_SELF -1 151 #define APIC_IPI_DEST_ALL -2 152 #define APIC_IPI_DEST_OTHERS -3 153 154 #define APIC_BUS_UNKNOWN -1 155 #define APIC_BUS_ISA 0 156 #define APIC_BUS_EISA 1 157 #define APIC_BUS_PCI 2 158 #define APIC_BUS_MAX APIC_BUS_PCI 159 160 #define IRQ_EXTINT (NUM_IO_INTS + 1) 161 #define IRQ_NMI (NUM_IO_INTS + 2) 162 #define IRQ_SMI (NUM_IO_INTS + 3) 163 #define IRQ_DISABLED (NUM_IO_INTS + 4) 164 165 /* 166 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 167 * CPU's and I/O APIC's. 168 */ 169 struct apic_enumerator { 170 const char *apic_name; 171 int (*apic_probe)(void); 172 int (*apic_probe_cpus)(void); 173 int (*apic_setup_local)(void); 174 int (*apic_setup_io)(void); 175 SLIST_ENTRY(apic_enumerator) apic_next; 176 }; 177 178 inthand_t 179 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 180 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 181 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 182 IDTVEC(spuriousint), IDTVEC(timerint); 183 184 extern vm_paddr_t lapic_paddr; 185 extern int apic_cpuids[]; 186 187 void apic_register_enumerator(struct apic_enumerator *enumerator); 188 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 189 int ioapic_disable_pin(void *cookie, u_int pin); 190 int ioapic_get_vector(void *cookie, u_int pin); 191 void ioapic_register(void *cookie); 192 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 193 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 194 int ioapic_set_extint(void *cookie, u_int pin); 195 int ioapic_set_nmi(void *cookie, u_int pin); 196 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 197 int ioapic_set_triggermode(void *cookie, u_int pin, 198 enum intr_trigger trigger); 199 int ioapic_set_smi(void *cookie, u_int pin); 200 201 /* 202 * Struct containing pointers to APIC functions whose 203 * implementation is run time selectable. 204 */ 205 struct apic_ops { 206 void (*create)(u_int, int); 207 void (*init)(vm_paddr_t); 208 void (*xapic_mode)(void); 209 void (*setup)(int); 210 void (*dump)(const char *); 211 void (*disable)(void); 212 void (*eoi)(void); 213 int (*id)(void); 214 int (*intr_pending)(u_int); 215 void (*set_logical_id)(u_int, u_int, u_int); 216 u_int (*cpuid)(u_int); 217 218 /* Vectors */ 219 u_int (*alloc_vector)(u_int, u_int); 220 u_int (*alloc_vectors)(u_int, u_int *, u_int, u_int); 221 void (*enable_vector)(u_int, u_int); 222 void (*disable_vector)(u_int, u_int); 223 void (*free_vector)(u_int, u_int, u_int); 224 225 226 /* PMC */ 227 int (*enable_pmc)(void); 228 void (*disable_pmc)(void); 229 void (*reenable_pmc)(void); 230 231 /* CMC */ 232 void (*enable_cmc)(void); 233 234 /* IPI */ 235 void (*ipi_raw)(register_t, u_int); 236 void (*ipi_vectored)(u_int, int); 237 int (*ipi_wait)(int); 238 int (*ipi_alloc)(inthand_t *ipifunc); 239 void (*ipi_free)(int vector); 240 241 /* LVT */ 242 int (*set_lvt_mask)(u_int, u_int, u_char); 243 int (*set_lvt_mode)(u_int, u_int, u_int32_t); 244 int (*set_lvt_polarity)(u_int, u_int, enum intr_polarity); 245 int (*set_lvt_triggermode)(u_int, u_int, enum intr_trigger); 246 }; 247 248 extern struct apic_ops apic_ops; 249 250 static inline void 251 lapic_create(u_int apic_id, int boot_cpu) 252 { 253 254 apic_ops.create(apic_id, boot_cpu); 255 } 256 257 static inline void 258 lapic_init(vm_paddr_t addr) 259 { 260 261 apic_ops.init(addr); 262 } 263 264 static inline void 265 lapic_xapic_mode(void) 266 { 267 268 apic_ops.xapic_mode(); 269 } 270 271 static inline void 272 lapic_setup(int boot) 273 { 274 275 apic_ops.setup(boot); 276 } 277 278 static inline void 279 lapic_dump(const char *str) 280 { 281 282 apic_ops.dump(str); 283 } 284 285 static inline void 286 lapic_disable(void) 287 { 288 289 apic_ops.disable(); 290 } 291 292 static inline void 293 lapic_eoi(void) 294 { 295 296 apic_ops.eoi(); 297 } 298 299 static inline int 300 lapic_id(void) 301 { 302 303 return (apic_ops.id()); 304 } 305 306 static inline int 307 lapic_intr_pending(u_int vector) 308 { 309 310 return (apic_ops.intr_pending(vector)); 311 } 312 313 /* XXX: UNUSED */ 314 static inline void 315 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 316 { 317 318 apic_ops.set_logical_id(apic_id, cluster, cluster_id); 319 } 320 321 static inline u_int 322 apic_cpuid(u_int apic_id) 323 { 324 325 return (apic_ops.cpuid(apic_id)); 326 } 327 328 static inline u_int 329 apic_alloc_vector(u_int apic_id, u_int irq) 330 { 331 332 return (apic_ops.alloc_vector(apic_id, irq)); 333 } 334 335 static inline u_int 336 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 337 { 338 339 return (apic_ops.alloc_vectors(apic_id, irqs, count, align)); 340 } 341 342 static inline void 343 apic_enable_vector(u_int apic_id, u_int vector) 344 { 345 346 apic_ops.enable_vector(apic_id, vector); 347 } 348 349 static inline void 350 apic_disable_vector(u_int apic_id, u_int vector) 351 { 352 353 apic_ops.disable_vector(apic_id, vector); 354 } 355 356 static inline void 357 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 358 { 359 360 apic_ops.free_vector(apic_id, vector, irq); 361 } 362 363 static inline int 364 lapic_enable_pmc(void) 365 { 366 367 return (apic_ops.enable_pmc()); 368 } 369 370 static inline void 371 lapic_disable_pmc(void) 372 { 373 374 apic_ops.disable_pmc(); 375 } 376 377 static inline void 378 lapic_reenable_pmc(void) 379 { 380 381 apic_ops.reenable_pmc(); 382 } 383 384 static inline void 385 lapic_enable_cmc(void) 386 { 387 388 apic_ops.enable_cmc(); 389 } 390 391 static inline void 392 lapic_ipi_raw(register_t icrlo, u_int dest) 393 { 394 395 apic_ops.ipi_raw(icrlo, dest); 396 } 397 398 static inline void 399 lapic_ipi_vectored(u_int vector, int dest) 400 { 401 402 apic_ops.ipi_vectored(vector, dest); 403 } 404 405 static inline int 406 lapic_ipi_wait(int delay) 407 { 408 409 return (apic_ops.ipi_wait(delay)); 410 } 411 412 static inline int 413 lapic_ipi_alloc(inthand_t *ipifunc) 414 { 415 416 return (apic_ops.ipi_alloc(ipifunc)); 417 } 418 419 static inline void 420 lapic_ipi_free(int vector) 421 { 422 423 return (apic_ops.ipi_free(vector)); 424 } 425 426 static inline int 427 lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked) 428 { 429 430 return (apic_ops.set_lvt_mask(apic_id, lvt, masked)); 431 } 432 433 static inline int 434 lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode) 435 { 436 437 return (apic_ops.set_lvt_mode(apic_id, lvt, mode)); 438 } 439 440 static inline int 441 lapic_set_lvt_polarity(u_int apic_id, u_int lvt, enum intr_polarity pol) 442 { 443 444 return (apic_ops.set_lvt_polarity(apic_id, lvt, pol)); 445 } 446 447 static inline int 448 lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, enum intr_trigger trigger) 449 { 450 451 return (apic_ops.set_lvt_triggermode(apic_id, lvt, trigger)); 452 } 453 454 void lapic_handle_cmc(void); 455 void lapic_handle_error(void); 456 void lapic_handle_intr(int vector, struct trapframe *frame); 457 void lapic_handle_timer(struct trapframe *frame); 458 void xen_intr_handle_upcall(struct trapframe *frame); 459 void hv_vector_handler(struct trapframe *frame); 460 461 extern int x2apic_mode; 462 extern int lapic_eoi_suppression; 463 464 #ifdef _SYS_SYSCTL_H_ 465 SYSCTL_DECL(_hw_apic); 466 #endif 467 468 #endif /* !LOCORE */ 469 #endif /* _X86_APICVAR_H_ */ 470