1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __X86_INTR_MACHDEP_H__ 32 #define __X86_INTR_MACHDEP_H__ 33 34 #ifdef _KERNEL 35 36 /* 37 * Values used in determining the allocation of IRQ values among 38 * different types of I/O interrupts. These values are used as 39 * indices into a interrupt source array to map I/O interrupts to a 40 * device interrupt source whether it be a pin on an interrupt 41 * controller or an MSI interrupt. The 16 ISA IRQs are assigned fixed 42 * IDT vectors, but all other device interrupts allocate IDT vectors 43 * on demand. Currently we have 191 IDT vectors available for device 44 * interrupts on each CPU. On many systems with I/O APICs, a lot of 45 * the IRQs are not used, so the total number of IRQ values reserved 46 * can exceed the number of available IDT slots. 47 * 48 * The first 16 IRQs (0 - 15) are reserved for ISA IRQs. Interrupt 49 * pins on I/O APICs for non-ISA interrupts use IRQ values starting at 50 * IRQ 17. This layout matches the GSI numbering used by ACPI so that 51 * IRQ values returned by ACPI methods such as _CRS can be used 52 * directly by the ACPI bus driver. 53 * 54 * MSI interrupts allocate a block of interrupts starting at the end 55 * of the I/O APIC range. When running under the Xen Hypervisor, an 56 * additional range of IRQ values are available for binding to event 57 * channel events. 58 */ 59 extern u_int first_msi_irq; 60 extern u_int num_io_irqs; 61 extern u_int num_msi_irqs; 62 63 /* 64 * Default base address for MSI messages on x86 platforms. 65 */ 66 #define MSI_INTEL_ADDR_BASE 0xfee00000 67 68 #ifndef LOCORE 69 70 typedef void inthand_t(void); 71 72 #define IDTVEC(name) __CONCAT(X,name) 73 74 struct intsrc; 75 76 /* 77 * Methods that a PIC provides to mask/unmask a given interrupt source, 78 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 79 * return the vector associated with this source. 80 */ 81 struct pic { 82 void (*pic_register_sources)(struct pic *); 83 void (*pic_enable_source)(struct intsrc *); 84 void (*pic_disable_source)(struct intsrc *, int); 85 void (*pic_eoi_source)(struct intsrc *); 86 void (*pic_enable_intr)(struct intsrc *); 87 void (*pic_disable_intr)(struct intsrc *); 88 int (*pic_vector)(struct intsrc *); 89 int (*pic_source_pending)(struct intsrc *); 90 void (*pic_suspend)(struct pic *); 91 void (*pic_resume)(struct pic *, bool suspend_cancelled); 92 int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 93 enum intr_polarity); 94 int (*pic_assign_cpu)(struct intsrc *, u_int apic_id); 95 void (*pic_reprogram_pin)(struct intsrc *); 96 TAILQ_ENTRY(pic) pics; 97 }; 98 99 /* Flags for pic_disable_source() */ 100 enum { 101 PIC_EOI, 102 PIC_NO_EOI, 103 }; 104 105 /* 106 * An interrupt source. The upper-layer code uses the PIC methods to 107 * control a given source. The lower-layer PIC drivers can store additional 108 * private data in a given interrupt source such as an interrupt pin number 109 * or an I/O APIC pointer. 110 */ 111 struct intsrc { 112 struct pic *is_pic; 113 struct intr_event *is_event; 114 u_long *is_count; 115 u_long *is_straycount; 116 u_int is_index; 117 u_int is_handlers; 118 u_int is_domain; 119 u_int is_cpu; 120 }; 121 122 struct trapframe; 123 124 #ifdef SMP 125 extern cpuset_t intr_cpus; 126 #endif 127 extern struct mtx icu_lock; 128 extern int elcr_found; 129 #ifdef SMP 130 extern int msix_disable_migration; 131 #endif 132 133 #ifndef DEV_ATPIC 134 void atpic_reset(void); 135 #endif 136 /* XXX: The elcr_* prototypes probably belong somewhere else. */ 137 int elcr_probe(void); 138 enum intr_trigger elcr_read_trigger(u_int irq); 139 void elcr_resume(void); 140 void elcr_write_trigger(u_int irq, enum intr_trigger trigger); 141 #ifdef SMP 142 void intr_add_cpu(u_int cpu); 143 #endif 144 int intr_add_handler(const char *name, int vector, driver_filter_t filter, 145 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep, 146 int domain); 147 #ifdef SMP 148 int intr_bind(u_int vector, u_char cpu); 149 #endif 150 int intr_config_intr(int vector, enum intr_trigger trig, 151 enum intr_polarity pol); 152 int intr_describe(u_int vector, void *ih, const char *descr); 153 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 154 u_int intr_next_cpu(int domain); 155 struct intsrc *intr_lookup_source(int vector); 156 int intr_register_pic(struct pic *pic); 157 int intr_register_source(struct intsrc *isrc); 158 int intr_remove_handler(void *cookie); 159 void intr_resume(bool suspend_cancelled); 160 void intr_suspend(void); 161 void intr_reprogram(void); 162 void intrcnt_add(const char *name, u_long **countp); 163 void nexus_add_irq(u_long irq); 164 int msi_alloc(device_t dev, int count, int maxcount, int *irqs); 165 void msi_init(void); 166 int msi_map(int irq, uint64_t *addr, uint32_t *data); 167 int msi_release(int *irqs, int count); 168 int msix_alloc(device_t dev, int *irq); 169 int msix_release(int irq); 170 #ifdef XENHVM 171 void xen_intr_alloc_irqs(void); 172 #endif 173 174 #endif /* !LOCORE */ 175 #endif /* _KERNEL */ 176 #endif /* !__X86_INTR_MACHDEP_H__ */ 177