1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 * $FreeBSD$ 33 */ 34 35 #ifndef _MACHINE_SPECIALREG_H_ 36 #define _MACHINE_SPECIALREG_H_ 37 38 /* 39 * Bits in 386 special registers: 40 */ 41 #define CR0_PE 0x00000001 /* Protected mode Enable */ 42 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 43 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 45 #define CR0_PG 0x80000000 /* PaGing enable */ 46 47 /* 48 * Bits in 486 special registers: 49 */ 50 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 51 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 52 all modes) */ 53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 54 #define CR0_NW 0x20000000 /* Not Write-through */ 55 #define CR0_CD 0x40000000 /* Cache Disable */ 56 57 #define CR3_PCID_SAVE 0x8000000000000000 58 #define CR3_PCID_MASK 0xfff 59 60 /* 61 * Bits in PPro special registers 62 */ 63 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 64 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 65 #define CR4_TSD 0x00000004 /* Time stamp disable */ 66 #define CR4_DE 0x00000008 /* Debugging extensions */ 67 #define CR4_PSE 0x00000010 /* Page size extensions */ 68 #define CR4_PAE 0x00000020 /* Physical address extension */ 69 #define CR4_MCE 0x00000040 /* Machine check enable */ 70 #define CR4_PGE 0x00000080 /* Page global enable */ 71 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 72 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 73 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 74 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 75 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 76 #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 77 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 78 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 79 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */ 80 81 /* 82 * Bits in AMD64 special registers. EFER is 64 bits wide. 83 */ 84 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 85 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 86 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 87 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 88 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 89 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 90 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 91 #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 92 93 /* 94 * Intel Extended Features registers 95 */ 96 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 97 98 #define XFEATURE_ENABLED_X87 0x00000001 99 #define XFEATURE_ENABLED_SSE 0x00000002 100 #define XFEATURE_ENABLED_YMM_HI128 0x00000004 101 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 102 #define XFEATURE_ENABLED_BNDREGS 0x00000008 103 #define XFEATURE_ENABLED_BNDCSR 0x00000010 104 #define XFEATURE_ENABLED_OPMASK 0x00000020 105 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 106 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 107 108 #define XFEATURE_AVX \ 109 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 110 #define XFEATURE_AVX512 \ 111 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 112 XFEATURE_ENABLED_HI16_ZMM) 113 #define XFEATURE_MPX \ 114 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 115 116 /* 117 * CPUID instruction features register 118 */ 119 #define CPUID_FPU 0x00000001 120 #define CPUID_VME 0x00000002 121 #define CPUID_DE 0x00000004 122 #define CPUID_PSE 0x00000008 123 #define CPUID_TSC 0x00000010 124 #define CPUID_MSR 0x00000020 125 #define CPUID_PAE 0x00000040 126 #define CPUID_MCE 0x00000080 127 #define CPUID_CX8 0x00000100 128 #define CPUID_APIC 0x00000200 129 #define CPUID_B10 0x00000400 130 #define CPUID_SEP 0x00000800 131 #define CPUID_MTRR 0x00001000 132 #define CPUID_PGE 0x00002000 133 #define CPUID_MCA 0x00004000 134 #define CPUID_CMOV 0x00008000 135 #define CPUID_PAT 0x00010000 136 #define CPUID_PSE36 0x00020000 137 #define CPUID_PSN 0x00040000 138 #define CPUID_CLFSH 0x00080000 139 #define CPUID_B20 0x00100000 140 #define CPUID_DS 0x00200000 141 #define CPUID_ACPI 0x00400000 142 #define CPUID_MMX 0x00800000 143 #define CPUID_FXSR 0x01000000 144 #define CPUID_SSE 0x02000000 145 #define CPUID_XMM 0x02000000 146 #define CPUID_SSE2 0x04000000 147 #define CPUID_SS 0x08000000 148 #define CPUID_HTT 0x10000000 149 #define CPUID_TM 0x20000000 150 #define CPUID_IA64 0x40000000 151 #define CPUID_PBE 0x80000000 152 153 #define CPUID2_SSE3 0x00000001 154 #define CPUID2_PCLMULQDQ 0x00000002 155 #define CPUID2_DTES64 0x00000004 156 #define CPUID2_MON 0x00000008 157 #define CPUID2_DS_CPL 0x00000010 158 #define CPUID2_VMX 0x00000020 159 #define CPUID2_SMX 0x00000040 160 #define CPUID2_EST 0x00000080 161 #define CPUID2_TM2 0x00000100 162 #define CPUID2_SSSE3 0x00000200 163 #define CPUID2_CNXTID 0x00000400 164 #define CPUID2_SDBG 0x00000800 165 #define CPUID2_FMA 0x00001000 166 #define CPUID2_CX16 0x00002000 167 #define CPUID2_XTPR 0x00004000 168 #define CPUID2_PDCM 0x00008000 169 #define CPUID2_PCID 0x00020000 170 #define CPUID2_DCA 0x00040000 171 #define CPUID2_SSE41 0x00080000 172 #define CPUID2_SSE42 0x00100000 173 #define CPUID2_X2APIC 0x00200000 174 #define CPUID2_MOVBE 0x00400000 175 #define CPUID2_POPCNT 0x00800000 176 #define CPUID2_TSCDLT 0x01000000 177 #define CPUID2_AESNI 0x02000000 178 #define CPUID2_XSAVE 0x04000000 179 #define CPUID2_OSXSAVE 0x08000000 180 #define CPUID2_AVX 0x10000000 181 #define CPUID2_F16C 0x20000000 182 #define CPUID2_RDRAND 0x40000000 183 #define CPUID2_HV 0x80000000 184 185 /* 186 * Important bits in the Thermal and Power Management flags 187 * CPUID.6 EAX and ECX. 188 */ 189 #define CPUTPM1_SENSOR 0x00000001 190 #define CPUTPM1_TURBO 0x00000002 191 #define CPUTPM1_ARAT 0x00000004 192 #define CPUTPM1_HWP 0x00000080 193 #define CPUTPM1_HWP_NOTIFICATION 0x00000100 194 #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200 195 #define CPUTPM1_HWP_PERF_PREF 0x00000400 196 #define CPUTPM1_HWP_PKG 0x00000800 197 #define CPUTPM1_HWP_FLEXIBLE 0x00020000 198 #define CPUTPM2_EFFREQ 0x00000001 199 200 /* Intel Processor Trace CPUID. */ 201 202 /* Leaf 0 ebx. */ 203 #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */ 204 #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */ 205 #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */ 206 #define CPUPT_MTC (1 << 3) /* MTC Supported */ 207 #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ 208 #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ 209 210 /* Leaf 0 ecx. */ 211 #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ 212 #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ 213 #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ 214 #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ 215 #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ 216 217 /* Leaf 1 eax. */ 218 #define CPUPT_NADDR_S 0 /* Number of Address Ranges */ 219 #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S) 220 #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */ 221 #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S) 222 223 /* Leaf 1 ebx. */ 224 #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */ 225 #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S) 226 #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */ 227 #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S) 228 229 /* 230 * Important bits in the AMD extended cpuid flags 231 */ 232 #define AMDID_SYSCALL 0x00000800 233 #define AMDID_MP 0x00080000 234 #define AMDID_NX 0x00100000 235 #define AMDID_EXT_MMX 0x00400000 236 #define AMDID_FFXSR 0x02000000 237 #define AMDID_PAGE1GB 0x04000000 238 #define AMDID_RDTSCP 0x08000000 239 #define AMDID_LM 0x20000000 240 #define AMDID_EXT_3DNOW 0x40000000 241 #define AMDID_3DNOW 0x80000000 242 243 #define AMDID2_LAHF 0x00000001 244 #define AMDID2_CMP 0x00000002 245 #define AMDID2_SVM 0x00000004 246 #define AMDID2_EXT_APIC 0x00000008 247 #define AMDID2_CR8 0x00000010 248 #define AMDID2_ABM 0x00000020 249 #define AMDID2_SSE4A 0x00000040 250 #define AMDID2_MAS 0x00000080 251 #define AMDID2_PREFETCH 0x00000100 252 #define AMDID2_OSVW 0x00000200 253 #define AMDID2_IBS 0x00000400 254 #define AMDID2_XOP 0x00000800 255 #define AMDID2_SKINIT 0x00001000 256 #define AMDID2_WDT 0x00002000 257 #define AMDID2_LWP 0x00008000 258 #define AMDID2_FMA4 0x00010000 259 #define AMDID2_TCE 0x00020000 260 #define AMDID2_NODE_ID 0x00080000 261 #define AMDID2_TBM 0x00200000 262 #define AMDID2_TOPOLOGY 0x00400000 263 #define AMDID2_PCXC 0x00800000 264 #define AMDID2_PNXC 0x01000000 265 #define AMDID2_DBE 0x04000000 266 #define AMDID2_PTSC 0x08000000 267 #define AMDID2_PTSCEL2I 0x10000000 268 #define AMDID2_MWAITX 0x20000000 269 270 /* 271 * CPUID instruction 1 eax info 272 */ 273 #define CPUID_STEPPING 0x0000000f 274 #define CPUID_MODEL 0x000000f0 275 #define CPUID_FAMILY 0x00000f00 276 #define CPUID_EXT_MODEL 0x000f0000 277 #define CPUID_EXT_FAMILY 0x0ff00000 278 #ifdef __i386__ 279 #define CPUID_TO_MODEL(id) \ 280 ((((id) & CPUID_MODEL) >> 4) | \ 281 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 282 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 283 #define CPUID_TO_FAMILY(id) \ 284 ((((id) & CPUID_FAMILY) >> 8) + \ 285 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 286 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 287 #else 288 #define CPUID_TO_MODEL(id) \ 289 ((((id) & CPUID_MODEL) >> 4) | \ 290 (((id) & CPUID_EXT_MODEL) >> 12)) 291 #define CPUID_TO_FAMILY(id) \ 292 ((((id) & CPUID_FAMILY) >> 8) + \ 293 (((id) & CPUID_EXT_FAMILY) >> 20)) 294 #endif 295 296 /* 297 * CPUID instruction 1 ebx info 298 */ 299 #define CPUID_BRAND_INDEX 0x000000ff 300 #define CPUID_CLFUSH_SIZE 0x0000ff00 301 #define CPUID_HTT_CORES 0x00ff0000 302 #define CPUID_LOCAL_APIC_ID 0xff000000 303 304 /* 305 * CPUID instruction 5 info 306 */ 307 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 308 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 309 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 310 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 311 312 /* 313 * MWAIT cpu power states. Lower 4 bits are sub-states. 314 */ 315 #define MWAIT_C0 0xf0 316 #define MWAIT_C1 0x00 317 #define MWAIT_C2 0x10 318 #define MWAIT_C3 0x20 319 #define MWAIT_C4 0x30 320 321 /* 322 * MWAIT extensions. 323 */ 324 /* Interrupt breaks MWAIT even when masked. */ 325 #define MWAIT_INTRBREAK 0x00000001 326 327 /* 328 * CPUID instruction 6 ecx info 329 */ 330 #define CPUID_PERF_STAT 0x00000001 331 #define CPUID_PERF_BIAS 0x00000008 332 333 /* 334 * CPUID instruction 0xb ebx info. 335 */ 336 #define CPUID_TYPE_INVAL 0 337 #define CPUID_TYPE_SMT 1 338 #define CPUID_TYPE_CORE 2 339 340 /* 341 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 342 */ 343 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 344 #define CPUID_EXTSTATE_XSAVEC 0x00000002 345 #define CPUID_EXTSTATE_XINUSE 0x00000004 346 #define CPUID_EXTSTATE_XSAVES 0x00000008 347 348 /* 349 * AMD extended function 8000_0007h ebx info 350 */ 351 #define AMDRAS_MCA_OF_RECOV 0x00000001 352 #define AMDRAS_SUCCOR 0x00000002 353 #define AMDRAS_HW_ASSERT 0x00000004 354 #define AMDRAS_SCALABLE_MCA 0x00000008 355 #define AMDRAS_PFEH_SUPPORT 0x00000010 356 357 /* 358 * AMD extended function 8000_0007h edx info 359 */ 360 #define AMDPM_TS 0x00000001 361 #define AMDPM_FID 0x00000002 362 #define AMDPM_VID 0x00000004 363 #define AMDPM_TTP 0x00000008 364 #define AMDPM_TM 0x00000010 365 #define AMDPM_STC 0x00000020 366 #define AMDPM_100MHZ_STEPS 0x00000040 367 #define AMDPM_HW_PSTATE 0x00000080 368 #define AMDPM_TSC_INVARIANT 0x00000100 369 #define AMDPM_CPB 0x00000200 370 371 /* 372 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) 373 */ 374 #define AMDFEID_CLZERO 0x00000001 375 #define AMDFEID_IRPERF 0x00000002 376 #define AMDFEID_XSAVEERPTR 0x00000004 377 378 /* 379 * AMD extended function 8000_0008h ecx info 380 */ 381 #define AMDID_CMP_CORES 0x000000ff 382 #define AMDID_COREID_SIZE 0x0000f000 383 #define AMDID_COREID_SIZE_SHIFT 12 384 385 /* 386 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 387 */ 388 #define CPUID_STDEXT_FSGSBASE 0x00000001 389 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 390 #define CPUID_STDEXT_SGX 0x00000004 391 #define CPUID_STDEXT_BMI1 0x00000008 392 #define CPUID_STDEXT_HLE 0x00000010 393 #define CPUID_STDEXT_AVX2 0x00000020 394 #define CPUID_STDEXT_FDP_EXC 0x00000040 395 #define CPUID_STDEXT_SMEP 0x00000080 396 #define CPUID_STDEXT_BMI2 0x00000100 397 #define CPUID_STDEXT_ERMS 0x00000200 398 #define CPUID_STDEXT_INVPCID 0x00000400 399 #define CPUID_STDEXT_RTM 0x00000800 400 #define CPUID_STDEXT_PQM 0x00001000 401 #define CPUID_STDEXT_NFPUSG 0x00002000 402 #define CPUID_STDEXT_MPX 0x00004000 403 #define CPUID_STDEXT_PQE 0x00008000 404 #define CPUID_STDEXT_AVX512F 0x00010000 405 #define CPUID_STDEXT_AVX512DQ 0x00020000 406 #define CPUID_STDEXT_RDSEED 0x00040000 407 #define CPUID_STDEXT_ADX 0x00080000 408 #define CPUID_STDEXT_SMAP 0x00100000 409 #define CPUID_STDEXT_AVX512IFMA 0x00200000 410 #define CPUID_STDEXT_PCOMMIT 0x00400000 411 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 412 #define CPUID_STDEXT_CLWB 0x01000000 413 #define CPUID_STDEXT_PROCTRACE 0x02000000 414 #define CPUID_STDEXT_AVX512PF 0x04000000 415 #define CPUID_STDEXT_AVX512ER 0x08000000 416 #define CPUID_STDEXT_AVX512CD 0x10000000 417 #define CPUID_STDEXT_SHA 0x20000000 418 #define CPUID_STDEXT_AVX512BW 0x40000000 419 #define CPUID_STDEXT_AVX512VL 0x80000000 420 421 /* 422 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info 423 */ 424 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 425 #define CPUID_STDEXT2_UMIP 0x00000004 426 #define CPUID_STDEXT2_PKU 0x00000008 427 #define CPUID_STDEXT2_OSPKE 0x00000010 428 #define CPUID_STDEXT2_RDPID 0x00400000 429 #define CPUID_STDEXT2_SGXLC 0x40000000 430 431 /* 432 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info 433 */ 434 #define CPUID_STDEXT3_IBPB 0x04000000 435 #define CPUID_STDEXT3_STIBP 0x08000000 436 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000 437 #define CPUID_STDEXT3_ARCH_CAP 0x20000000 438 #define CPUID_STDEXT3_SSBD 0x80000000 439 440 /* MSR IA32_ARCH_CAP(ABILITIES) bits */ 441 #define IA32_ARCH_CAP_RDCL_NO 0x00000001 442 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 443 #define IA32_ARCH_CAP_RSBA 0x00000004 444 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 445 #define IA32_ARCH_CAP_SSB_NO 0x00000010 446 447 /* 448 * CPUID manufacturers identifiers 449 */ 450 #define AMD_VENDOR_ID "AuthenticAMD" 451 #define CENTAUR_VENDOR_ID "CentaurHauls" 452 #define CYRIX_VENDOR_ID "CyrixInstead" 453 #define INTEL_VENDOR_ID "GenuineIntel" 454 #define NEXGEN_VENDOR_ID "NexGenDriven" 455 #define NSC_VENDOR_ID "Geode by NSC" 456 #define RISE_VENDOR_ID "RiseRiseRise" 457 #define SIS_VENDOR_ID "SiS SiS SiS " 458 #define TRANSMETA_VENDOR_ID "GenuineTMx86" 459 #define UMC_VENDOR_ID "UMC UMC UMC " 460 461 /* 462 * Model-specific registers for the i386 family 463 */ 464 #define MSR_P5_MC_ADDR 0x000 465 #define MSR_P5_MC_TYPE 0x001 466 #define MSR_TSC 0x010 467 #define MSR_P5_CESR 0x011 468 #define MSR_P5_CTR0 0x012 469 #define MSR_P5_CTR1 0x013 470 #define MSR_IA32_PLATFORM_ID 0x017 471 #define MSR_APICBASE 0x01b 472 #define MSR_EBL_CR_POWERON 0x02a 473 #define MSR_TEST_CTL 0x033 474 #define MSR_IA32_FEATURE_CONTROL 0x03a 475 #define MSR_IA32_SPEC_CTRL 0x048 476 #define MSR_IA32_PRED_CMD 0x049 477 #define MSR_BIOS_UPDT_TRIG 0x079 478 #define MSR_BBL_CR_D0 0x088 479 #define MSR_BBL_CR_D1 0x089 480 #define MSR_BBL_CR_D2 0x08a 481 #define MSR_BIOS_SIGN 0x08b 482 #define MSR_PERFCTR0 0x0c1 483 #define MSR_PERFCTR1 0x0c2 484 #define MSR_PLATFORM_INFO 0x0ce 485 #define MSR_MPERF 0x0e7 486 #define MSR_APERF 0x0e8 487 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 488 #define MSR_MTRRcap 0x0fe 489 #define MSR_IA32_ARCH_CAP 0x10a 490 #define MSR_IA32_FLUSH_CMD 0x10b 491 #define MSR_BBL_CR_ADDR 0x116 492 #define MSR_BBL_CR_DECC 0x118 493 #define MSR_BBL_CR_CTL 0x119 494 #define MSR_BBL_CR_TRIG 0x11a 495 #define MSR_BBL_CR_BUSY 0x11b 496 #define MSR_BBL_CR_CTL3 0x11e 497 #define MSR_SYSENTER_CS_MSR 0x174 498 #define MSR_SYSENTER_ESP_MSR 0x175 499 #define MSR_SYSENTER_EIP_MSR 0x176 500 #define MSR_MCG_CAP 0x179 501 #define MSR_MCG_STATUS 0x17a 502 #define MSR_MCG_CTL 0x17b 503 #define MSR_EVNTSEL0 0x186 504 #define MSR_EVNTSEL1 0x187 505 #define MSR_THERM_CONTROL 0x19a 506 #define MSR_THERM_INTERRUPT 0x19b 507 #define MSR_THERM_STATUS 0x19c 508 #define MSR_IA32_MISC_ENABLE 0x1a0 509 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 510 #define MSR_TURBO_RATIO_LIMIT 0x1ad 511 #define MSR_TURBO_RATIO_LIMIT1 0x1ae 512 #define MSR_DEBUGCTLMSR 0x1d9 513 #define MSR_LASTBRANCHFROMIP 0x1db 514 #define MSR_LASTBRANCHTOIP 0x1dc 515 #define MSR_LASTINTFROMIP 0x1dd 516 #define MSR_LASTINTTOIP 0x1de 517 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 518 #define MSR_MTRRVarBase 0x200 519 #define MSR_MTRR64kBase 0x250 520 #define MSR_MTRR16kBase 0x258 521 #define MSR_MTRR4kBase 0x268 522 #define MSR_PAT 0x277 523 #define MSR_MC0_CTL2 0x280 524 #define MSR_MTRRdefType 0x2ff 525 #define MSR_MC0_CTL 0x400 526 #define MSR_MC0_STATUS 0x401 527 #define MSR_MC0_ADDR 0x402 528 #define MSR_MC0_MISC 0x403 529 #define MSR_MC1_CTL 0x404 530 #define MSR_MC1_STATUS 0x405 531 #define MSR_MC1_ADDR 0x406 532 #define MSR_MC1_MISC 0x407 533 #define MSR_MC2_CTL 0x408 534 #define MSR_MC2_STATUS 0x409 535 #define MSR_MC2_ADDR 0x40a 536 #define MSR_MC2_MISC 0x40b 537 #define MSR_MC3_CTL 0x40c 538 #define MSR_MC3_STATUS 0x40d 539 #define MSR_MC3_ADDR 0x40e 540 #define MSR_MC3_MISC 0x40f 541 #define MSR_MC4_CTL 0x410 542 #define MSR_MC4_STATUS 0x411 543 #define MSR_MC4_ADDR 0x412 544 #define MSR_MC4_MISC 0x413 545 #define MSR_RAPL_POWER_UNIT 0x606 546 #define MSR_PKG_ENERGY_STATUS 0x611 547 #define MSR_DRAM_ENERGY_STATUS 0x619 548 #define MSR_PP0_ENERGY_STATUS 0x639 549 #define MSR_PP1_ENERGY_STATUS 0x641 550 #define MSR_PPERF 0x64e 551 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ 552 #define MSR_IA32_PM_ENABLE 0x770 553 #define MSR_IA32_HWP_CAPABILITIES 0x771 554 #define MSR_IA32_HWP_REQUEST_PKG 0x772 555 #define MSR_IA32_HWP_INTERRUPT 0x773 556 #define MSR_IA32_HWP_REQUEST 0x774 557 #define MSR_IA32_HWP_STATUS 0x777 558 559 /* 560 * VMX MSRs 561 */ 562 #define MSR_VMX_BASIC 0x480 563 #define MSR_VMX_PINBASED_CTLS 0x481 564 #define MSR_VMX_PROCBASED_CTLS 0x482 565 #define MSR_VMX_EXIT_CTLS 0x483 566 #define MSR_VMX_ENTRY_CTLS 0x484 567 #define MSR_VMX_CR0_FIXED0 0x486 568 #define MSR_VMX_CR0_FIXED1 0x487 569 #define MSR_VMX_CR4_FIXED0 0x488 570 #define MSR_VMX_CR4_FIXED1 0x489 571 #define MSR_VMX_PROCBASED_CTLS2 0x48b 572 #define MSR_VMX_EPT_VPID_CAP 0x48c 573 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 574 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 575 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 576 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 577 578 /* 579 * X2APIC MSRs. 580 * Writes are not serializing. 581 */ 582 #define MSR_APIC_000 0x800 583 #define MSR_APIC_ID 0x802 584 #define MSR_APIC_VERSION 0x803 585 #define MSR_APIC_TPR 0x808 586 #define MSR_APIC_EOI 0x80b 587 #define MSR_APIC_LDR 0x80d 588 #define MSR_APIC_SVR 0x80f 589 #define MSR_APIC_ISR0 0x810 590 #define MSR_APIC_ISR1 0x811 591 #define MSR_APIC_ISR2 0x812 592 #define MSR_APIC_ISR3 0x813 593 #define MSR_APIC_ISR4 0x814 594 #define MSR_APIC_ISR5 0x815 595 #define MSR_APIC_ISR6 0x816 596 #define MSR_APIC_ISR7 0x817 597 #define MSR_APIC_TMR0 0x818 598 #define MSR_APIC_IRR0 0x820 599 #define MSR_APIC_ESR 0x828 600 #define MSR_APIC_LVT_CMCI 0x82F 601 #define MSR_APIC_ICR 0x830 602 #define MSR_APIC_LVT_TIMER 0x832 603 #define MSR_APIC_LVT_THERMAL 0x833 604 #define MSR_APIC_LVT_PCINT 0x834 605 #define MSR_APIC_LVT_LINT0 0x835 606 #define MSR_APIC_LVT_LINT1 0x836 607 #define MSR_APIC_LVT_ERROR 0x837 608 #define MSR_APIC_ICR_TIMER 0x838 609 #define MSR_APIC_CCR_TIMER 0x839 610 #define MSR_APIC_DCR_TIMER 0x83e 611 #define MSR_APIC_SELF_IPI 0x83f 612 613 #define MSR_IA32_XSS 0xda0 614 615 /* 616 * Intel Processor Trace (PT) MSRs. 617 */ 618 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */ 619 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */ 620 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */ 621 #define RTIT_CTL_TRACEEN (1 << 0) 622 #define RTIT_CTL_CYCEN (1 << 1) 623 #define RTIT_CTL_OS (1 << 2) 624 #define RTIT_CTL_USER (1 << 3) 625 #define RTIT_CTL_PWREVTEN (1 << 4) 626 #define RTIT_CTL_FUPONPTW (1 << 5) 627 #define RTIT_CTL_FABRICEN (1 << 6) 628 #define RTIT_CTL_CR3FILTER (1 << 7) 629 #define RTIT_CTL_TOPA (1 << 8) 630 #define RTIT_CTL_MTCEN (1 << 9) 631 #define RTIT_CTL_TSCEN (1 << 10) 632 #define RTIT_CTL_DISRETC (1 << 11) 633 #define RTIT_CTL_PTWEN (1 << 12) 634 #define RTIT_CTL_BRANCHEN (1 << 13) 635 #define RTIT_CTL_MTC_FREQ_S 14 636 #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S) 637 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S) 638 #define RTIT_CTL_CYC_THRESH_S 19 639 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S) 640 #define RTIT_CTL_PSB_FREQ_S 24 641 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S) 642 #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4) 643 #define RTIT_CTL_ADDR0_CFG_S 32 644 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S) 645 #define RTIT_CTL_ADDR1_CFG_S 36 646 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S) 647 #define RTIT_CTL_ADDR2_CFG_S 40 648 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S) 649 #define RTIT_CTL_ADDR3_CFG_S 44 650 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S) 651 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */ 652 #define RTIT_STATUS_FILTEREN (1 << 0) 653 #define RTIT_STATUS_CONTEXTEN (1 << 1) 654 #define RTIT_STATUS_TRIGGEREN (1 << 2) 655 #define RTIT_STATUS_ERROR (1 << 4) 656 #define RTIT_STATUS_STOPPED (1 << 5) 657 #define RTIT_STATUS_PACKETBYTECNT_S 32 658 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S) 659 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */ 660 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2) 661 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2) 662 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */ 663 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */ 664 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */ 665 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */ 666 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */ 667 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */ 668 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */ 669 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */ 670 671 /* Intel Processor Trace Table of Physical Addresses (ToPA). */ 672 #define TOPA_SIZE_S 6 673 #define TOPA_SIZE_M (0xf << TOPA_SIZE_S) 674 #define TOPA_SIZE_4K (0 << TOPA_SIZE_S) 675 #define TOPA_SIZE_8K (1 << TOPA_SIZE_S) 676 #define TOPA_SIZE_16K (2 << TOPA_SIZE_S) 677 #define TOPA_SIZE_32K (3 << TOPA_SIZE_S) 678 #define TOPA_SIZE_64K (4 << TOPA_SIZE_S) 679 #define TOPA_SIZE_128K (5 << TOPA_SIZE_S) 680 #define TOPA_SIZE_256K (6 << TOPA_SIZE_S) 681 #define TOPA_SIZE_512K (7 << TOPA_SIZE_S) 682 #define TOPA_SIZE_1M (8 << TOPA_SIZE_S) 683 #define TOPA_SIZE_2M (9 << TOPA_SIZE_S) 684 #define TOPA_SIZE_4M (10 << TOPA_SIZE_S) 685 #define TOPA_SIZE_8M (11 << TOPA_SIZE_S) 686 #define TOPA_SIZE_16M (12 << TOPA_SIZE_S) 687 #define TOPA_SIZE_32M (13 << TOPA_SIZE_S) 688 #define TOPA_SIZE_64M (14 << TOPA_SIZE_S) 689 #define TOPA_SIZE_128M (15 << TOPA_SIZE_S) 690 #define TOPA_STOP (1 << 4) 691 #define TOPA_INT (1 << 2) 692 #define TOPA_END (1 << 0) 693 694 /* 695 * Constants related to MSR's. 696 */ 697 #define APICBASE_RESERVED 0x000002ff 698 #define APICBASE_BSP 0x00000100 699 #define APICBASE_X2APIC 0x00000400 700 #define APICBASE_ENABLED 0x00000800 701 #define APICBASE_ADDRESS 0xfffff000 702 703 /* MSR_IA32_FEATURE_CONTROL related */ 704 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 705 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 706 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 707 708 /* MSR IA32_MISC_ENABLE */ 709 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 710 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 711 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 712 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 713 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 714 #define IA32_MISC_EN_MONE 0x0000000000040000ULL 715 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 716 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 717 #define IA32_MISC_EN_XDD 0x0000000400000000ULL 718 719 /* 720 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' 721 * document 336996-001 Speculative Execution Side Channel Mitigations. 722 */ 723 /* MSR IA32_SPEC_CTRL */ 724 #define IA32_SPEC_CTRL_IBRS 0x00000001 725 #define IA32_SPEC_CTRL_STIBP 0x00000002 726 #define IA32_SPEC_CTRL_SSBD 0x00000004 727 728 /* MSR IA32_PRED_CMD */ 729 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL 730 731 /* MSR IA32_FLUSH_CMD */ 732 #define IA32_FLUSH_CMD_L1D 0x00000001 733 734 /* MSR IA32_HWP_CAPABILITIES */ 735 #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) 736 #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) 737 #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) 738 #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) 739 740 /* MSR IA32_HWP_REQUEST */ 741 #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) 742 #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62) 743 #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61) 744 #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60) 745 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59) 746 #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42) 747 #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32) 748 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24) 749 #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16) 750 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8) 751 #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0) 752 753 /* 754 * PAT modes. 755 */ 756 #define PAT_UNCACHEABLE 0x00 757 #define PAT_WRITE_COMBINING 0x01 758 #define PAT_WRITE_THROUGH 0x04 759 #define PAT_WRITE_PROTECTED 0x05 760 #define PAT_WRITE_BACK 0x06 761 #define PAT_UNCACHED 0x07 762 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 763 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 764 765 /* 766 * Constants related to MTRRs 767 */ 768 #define MTRR_UNCACHEABLE 0x00 769 #define MTRR_WRITE_COMBINING 0x01 770 #define MTRR_WRITE_THROUGH 0x04 771 #define MTRR_WRITE_PROTECTED 0x05 772 #define MTRR_WRITE_BACK 0x06 773 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 774 #define MTRR_N16K 16 775 #define MTRR_N4K 64 776 #define MTRR_CAP_WC 0x0000000000000400 777 #define MTRR_CAP_FIXED 0x0000000000000100 778 #define MTRR_CAP_VCNT 0x00000000000000ff 779 #define MTRR_DEF_ENABLE 0x0000000000000800 780 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 781 #define MTRR_DEF_TYPE 0x00000000000000ff 782 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 783 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 784 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 785 #define MTRR_PHYSMASK_VALID 0x0000000000000800 786 787 /* 788 * Cyrix configuration registers, accessible as IO ports. 789 */ 790 #define CCR0 0xc0 /* Configuration control register 0 */ 791 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 792 non-cacheable */ 793 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 794 #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 795 #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 796 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 797 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 798 state */ 799 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 800 assoc */ 801 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 802 803 #define CCR1 0xc1 /* Configuration control register 1 */ 804 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 805 #define CCR1_SMI 0x02 /* Enables SMM pins */ 806 #define CCR1_SMAC 0x04 /* System management memory access */ 807 #define CCR1_MMAC 0x08 /* Main memory access */ 808 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 809 #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 810 811 #define CCR2 0xc2 812 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 813 #define CCR2_SADS 0x02 /* Slow ADS */ 814 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 815 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 816 #define CCR2_WT1 0x10 /* WT region 1 */ 817 #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 818 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 819 hold state. */ 820 #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 821 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 822 823 #define CCR3 0xc3 824 #define CCR3_SMILOCK 0x01 /* SMM register lock */ 825 #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 826 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 827 #define CCR3_SMMMODE 0x08 /* SMM Mode */ 828 #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 829 #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 830 #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 831 #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 832 833 #define CCR4 0xe8 834 #define CCR4_IOMASK 0x07 835 #define CCR4_MEM 0x08 /* Enables momory bypassing */ 836 #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 837 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 838 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 839 840 #define CCR5 0xe9 841 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 842 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 843 #define CCR5_LBR1 0x10 /* Local bus region 1 */ 844 #define CCR5_ARREN 0x20 /* Enables ARR region */ 845 846 #define CCR6 0xea 847 848 #define CCR7 0xeb 849 850 /* Performance Control Register (5x86 only). */ 851 #define PCR0 0x20 852 #define PCR0_RSTK 0x01 /* Enables return stack */ 853 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 854 #define PCR0_LOOP 0x04 /* Enables loop */ 855 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 856 serialize pipe. */ 857 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 858 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 859 #define PCR0_LSSER 0x80 /* Disable reorder */ 860 861 /* Device Identification Registers */ 862 #define DIR0 0xfe 863 #define DIR1 0xff 864 865 /* 866 * Machine Check register constants. 867 */ 868 #define MCG_CAP_COUNT 0x000000ff 869 #define MCG_CAP_CTL_P 0x00000100 870 #define MCG_CAP_EXT_P 0x00000200 871 #define MCG_CAP_CMCI_P 0x00000400 872 #define MCG_CAP_TES_P 0x00000800 873 #define MCG_CAP_EXT_CNT 0x00ff0000 874 #define MCG_CAP_SER_P 0x01000000 875 #define MCG_STATUS_RIPV 0x00000001 876 #define MCG_STATUS_EIPV 0x00000002 877 #define MCG_STATUS_MCIP 0x00000004 878 #define MCG_CTL_ENABLE 0xffffffffffffffff 879 #define MCG_CTL_DISABLE 0x0000000000000000 880 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 881 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 882 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 883 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 884 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 885 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 886 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 887 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 888 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 889 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 890 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 891 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 892 #define MC_STATUS_PCC 0x0200000000000000 893 #define MC_STATUS_ADDRV 0x0400000000000000 894 #define MC_STATUS_MISCV 0x0800000000000000 895 #define MC_STATUS_EN 0x1000000000000000 896 #define MC_STATUS_UC 0x2000000000000000 897 #define MC_STATUS_OVER 0x4000000000000000 898 #define MC_STATUS_VAL 0x8000000000000000 899 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 900 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 901 #define MC_CTL2_THRESHOLD 0x0000000000007fff 902 #define MC_CTL2_CMCI_EN 0x0000000040000000 903 #define MC_AMDNB_BANK 4 904 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */ 905 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */ 906 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */ 907 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */ 908 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ 909 #define MC_MISC_AMD_LVT_SHIFT 52 910 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */ 911 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */ 912 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */ 913 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */ 914 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */ 915 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */ 916 #define MC_MISC_AMD_CNT_SHIFT 32 917 #define MC_MISC_AMD_CNT_MAX 0xfff 918 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */ 919 #define MC_MISC_AMD_PTR_SHIFT 24 920 921 /* 922 * The following four 3-byte registers control the non-cacheable regions. 923 * These registers must be written as three separate bytes. 924 * 925 * NCRx+0: A31-A24 of starting address 926 * NCRx+1: A23-A16 of starting address 927 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 928 * 929 * The non-cacheable region's starting address must be aligned to the 930 * size indicated by the NCR_SIZE_xx field. 931 */ 932 #define NCR1 0xc4 933 #define NCR2 0xc7 934 #define NCR3 0xca 935 #define NCR4 0xcd 936 937 #define NCR_SIZE_0K 0 938 #define NCR_SIZE_4K 1 939 #define NCR_SIZE_8K 2 940 #define NCR_SIZE_16K 3 941 #define NCR_SIZE_32K 4 942 #define NCR_SIZE_64K 5 943 #define NCR_SIZE_128K 6 944 #define NCR_SIZE_256K 7 945 #define NCR_SIZE_512K 8 946 #define NCR_SIZE_1M 9 947 #define NCR_SIZE_2M 10 948 #define NCR_SIZE_4M 11 949 #define NCR_SIZE_8M 12 950 #define NCR_SIZE_16M 13 951 #define NCR_SIZE_32M 14 952 #define NCR_SIZE_4G 15 953 954 /* 955 * The address region registers are used to specify the location and 956 * size for the eight address regions. 957 * 958 * ARRx + 0: A31-A24 of start address 959 * ARRx + 1: A23-A16 of start address 960 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 961 */ 962 #define ARR0 0xc4 963 #define ARR1 0xc7 964 #define ARR2 0xca 965 #define ARR3 0xcd 966 #define ARR4 0xd0 967 #define ARR5 0xd3 968 #define ARR6 0xd6 969 #define ARR7 0xd9 970 971 #define ARR_SIZE_0K 0 972 #define ARR_SIZE_4K 1 973 #define ARR_SIZE_8K 2 974 #define ARR_SIZE_16K 3 975 #define ARR_SIZE_32K 4 976 #define ARR_SIZE_64K 5 977 #define ARR_SIZE_128K 6 978 #define ARR_SIZE_256K 7 979 #define ARR_SIZE_512K 8 980 #define ARR_SIZE_1M 9 981 #define ARR_SIZE_2M 10 982 #define ARR_SIZE_4M 11 983 #define ARR_SIZE_8M 12 984 #define ARR_SIZE_16M 13 985 #define ARR_SIZE_32M 14 986 #define ARR_SIZE_4G 15 987 988 /* 989 * The region control registers specify the attributes associated with 990 * the ARRx addres regions. 991 */ 992 #define RCR0 0xdc 993 #define RCR1 0xdd 994 #define RCR2 0xde 995 #define RCR3 0xdf 996 #define RCR4 0xe0 997 #define RCR5 0xe1 998 #define RCR6 0xe2 999 #define RCR7 0xe3 1000 1001 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 1002 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 1003 #define RCR_WWO 0x02 /* Weak write ordering. */ 1004 #define RCR_WL 0x04 /* Weak locking. */ 1005 #define RCR_WG 0x08 /* Write gathering. */ 1006 #define RCR_WT 0x10 /* Write-through. */ 1007 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 1008 1009 /* AMD Write Allocate Top-Of-Memory and Control Register */ 1010 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 1011 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 1012 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 1013 1014 /* AMD64 MSR's */ 1015 #define MSR_EFER 0xc0000080 /* extended features */ 1016 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 1017 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 1018 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 1019 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 1020 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 1021 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 1022 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 1023 #define MSR_PERFEVSEL0 0xc0010000 1024 #define MSR_PERFEVSEL1 0xc0010001 1025 #define MSR_PERFEVSEL2 0xc0010002 1026 #define MSR_PERFEVSEL3 0xc0010003 1027 #define MSR_K7_PERFCTR0 0xc0010004 1028 #define MSR_K7_PERFCTR1 0xc0010005 1029 #define MSR_K7_PERFCTR2 0xc0010006 1030 #define MSR_K7_PERFCTR3 0xc0010007 1031 #define MSR_SYSCFG 0xc0010010 1032 #define MSR_HWCR 0xc0010015 1033 #define MSR_IORRBASE0 0xc0010016 1034 #define MSR_IORRMASK0 0xc0010017 1035 #define MSR_IORRBASE1 0xc0010018 1036 #define MSR_IORRMASK1 0xc0010019 1037 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 1038 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 1039 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 1040 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 1041 #define MSR_MC0_CTL_MASK 0xc0010044 1042 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 1043 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 1044 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 1045 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 1046 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 1047 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 1048 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 1049 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 1050 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ 1051 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ 1052 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 1053 1054 /* MSR_VM_CR related */ 1055 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 1056 1057 /* VIA ACE crypto featureset: for via_feature_rng */ 1058 #define VIA_HAS_RNG 1 /* cpu has RNG */ 1059 1060 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 1061 #define VIA_HAS_AES 1 /* cpu has AES */ 1062 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 1063 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 1064 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 1065 1066 /* Centaur Extended Feature flags */ 1067 #define VIA_CPUID_HAS_RNG 0x000004 1068 #define VIA_CPUID_DO_RNG 0x000008 1069 #define VIA_CPUID_HAS_ACE 0x000040 1070 #define VIA_CPUID_DO_ACE 0x000080 1071 #define VIA_CPUID_HAS_ACE2 0x000100 1072 #define VIA_CPUID_DO_ACE2 0x000200 1073 #define VIA_CPUID_HAS_PHE 0x000400 1074 #define VIA_CPUID_DO_PHE 0x000800 1075 #define VIA_CPUID_HAS_PMM 0x001000 1076 #define VIA_CPUID_DO_PMM 0x002000 1077 1078 /* VIA ACE xcrypt-* instruction context control options */ 1079 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 1080 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 1081 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 1082 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 1083 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 1084 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 1085 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 1086 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 1087 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 1088 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 1089 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 1090 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 1091 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 1092 1093 #endif /* !_MACHINE_SPECIALREG_H_ */ 1094