1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2015 The FreeBSD Foundation 5 * 6 * This software was developed by Konstantin Belousov <kib@FreeBSD.org> 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #if defined(__amd64__) 34 #define DEV_APIC 35 #else 36 #include "opt_apic.h" 37 #endif 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/lock.h> 44 #include <sys/malloc.h> 45 #include <sys/memdesc.h> 46 #include <sys/module.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/rwlock.h> 50 #include <sys/smp.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 #include <sys/vmem.h> 54 #include <vm/vm.h> 55 #include <vm/vm_extern.h> 56 #include <vm/vm_kern.h> 57 #include <vm/vm_object.h> 58 #include <vm/vm_page.h> 59 #include <vm/vm_pager.h> 60 #include <vm/vm_map.h> 61 #include <contrib/dev/acpica/include/acpi.h> 62 #include <contrib/dev/acpica/include/accommon.h> 63 #include <dev/acpica/acpivar.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <machine/bus.h> 67 #include <machine/pci_cfgreg.h> 68 #include <x86/include/busdma_impl.h> 69 #include <dev/iommu/busdma_iommu.h> 70 #include <x86/iommu/intel_reg.h> 71 #include <x86/iommu/intel_dmar.h> 72 73 #ifdef DEV_APIC 74 #include "pcib_if.h" 75 #include <machine/intr_machdep.h> 76 #include <x86/apicreg.h> 77 #include <x86/apicvar.h> 78 #endif 79 80 #define DMAR_FAULT_IRQ_RID 0 81 #define DMAR_QI_IRQ_RID 1 82 #define DMAR_REG_RID 2 83 84 static device_t *dmar_devs; 85 static int dmar_devcnt; 86 87 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *); 88 89 static void 90 dmar_iterate_tbl(dmar_iter_t iter, void *arg) 91 { 92 ACPI_TABLE_DMAR *dmartbl; 93 ACPI_DMAR_HEADER *dmarh; 94 char *ptr, *ptrend; 95 ACPI_STATUS status; 96 97 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 98 if (ACPI_FAILURE(status)) 99 return; 100 ptr = (char *)dmartbl + sizeof(*dmartbl); 101 ptrend = (char *)dmartbl + dmartbl->Header.Length; 102 for (;;) { 103 if (ptr >= ptrend) 104 break; 105 dmarh = (ACPI_DMAR_HEADER *)ptr; 106 if (dmarh->Length <= 0) { 107 printf("dmar_identify: corrupted DMAR table, l %d\n", 108 dmarh->Length); 109 break; 110 } 111 ptr += dmarh->Length; 112 if (!iter(dmarh, arg)) 113 break; 114 } 115 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 116 } 117 118 struct find_iter_args { 119 int i; 120 ACPI_DMAR_HARDWARE_UNIT *res; 121 }; 122 123 static int 124 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 125 { 126 struct find_iter_args *fia; 127 128 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT) 129 return (1); 130 131 fia = arg; 132 if (fia->i == 0) { 133 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh; 134 return (0); 135 } 136 fia->i--; 137 return (1); 138 } 139 140 static ACPI_DMAR_HARDWARE_UNIT * 141 dmar_find_by_index(int idx) 142 { 143 struct find_iter_args fia; 144 145 fia.i = idx; 146 fia.res = NULL; 147 dmar_iterate_tbl(dmar_find_iter, &fia); 148 return (fia.res); 149 } 150 151 static int 152 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 153 { 154 155 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT) 156 dmar_devcnt++; 157 return (1); 158 } 159 160 static int dmar_enable = 0; 161 static void 162 dmar_identify(driver_t *driver, device_t parent) 163 { 164 ACPI_TABLE_DMAR *dmartbl; 165 ACPI_DMAR_HARDWARE_UNIT *dmarh; 166 ACPI_STATUS status; 167 int i, error; 168 169 if (acpi_disabled("dmar")) 170 return; 171 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable); 172 if (!dmar_enable) 173 return; 174 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl); 175 if (ACPI_FAILURE(status)) 176 return; 177 haw = dmartbl->Width + 1; 178 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR) 179 dmar_high = BUS_SPACE_MAXADDR; 180 else 181 dmar_high = 1ULL << (haw + 1); 182 if (bootverbose) { 183 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width, 184 (unsigned)dmartbl->Flags, 185 "\020\001INTR_REMAP\002X2APIC_OPT_OUT"); 186 } 187 AcpiPutTable((ACPI_TABLE_HEADER *)dmartbl); 188 189 dmar_iterate_tbl(dmar_count_iter, NULL); 190 if (dmar_devcnt == 0) 191 return; 192 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF, 193 M_WAITOK | M_ZERO); 194 for (i = 0; i < dmar_devcnt; i++) { 195 dmarh = dmar_find_by_index(i); 196 if (dmarh == NULL) { 197 printf("dmar_identify: cannot find HWUNIT %d\n", i); 198 continue; 199 } 200 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i); 201 if (dmar_devs[i] == NULL) { 202 printf("dmar_identify: cannot create instance %d\n", i); 203 continue; 204 } 205 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY, 206 DMAR_REG_RID, dmarh->Address, PAGE_SIZE); 207 if (error != 0) { 208 printf( 209 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n", 210 i, (uintmax_t)dmarh->Address, error); 211 device_delete_child(parent, dmar_devs[i]); 212 dmar_devs[i] = NULL; 213 } 214 } 215 } 216 217 static int 218 dmar_probe(device_t dev) 219 { 220 221 if (acpi_get_handle(dev) != NULL) 222 return (ENXIO); 223 device_set_desc(dev, "DMA remap"); 224 return (BUS_PROBE_NOWILDCARD); 225 } 226 227 static void 228 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx) 229 { 230 struct dmar_msi_data *dmd; 231 232 dmd = &unit->intrs[idx]; 233 if (dmd->irq == -1) 234 return; 235 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 236 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 237 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 238 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)), 239 dev, dmd->irq); 240 dmd->irq = -1; 241 } 242 243 static void 244 dmar_release_resources(device_t dev, struct dmar_unit *unit) 245 { 246 int i; 247 248 iommu_fini_busdma(&unit->iommu); 249 dmar_fini_irt(unit); 250 dmar_fini_qi(unit); 251 dmar_fini_fault_log(unit); 252 for (i = 0; i < DMAR_INTR_TOTAL; i++) 253 dmar_release_intr(dev, unit, i); 254 if (unit->regs != NULL) { 255 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 256 unit->regs); 257 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid, 258 unit->regs); 259 unit->regs = NULL; 260 } 261 if (unit->domids != NULL) { 262 delete_unrhdr(unit->domids); 263 unit->domids = NULL; 264 } 265 if (unit->ctx_obj != NULL) { 266 vm_object_deallocate(unit->ctx_obj); 267 unit->ctx_obj = NULL; 268 } 269 } 270 271 static int 272 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx) 273 { 274 device_t pcib; 275 struct dmar_msi_data *dmd; 276 uint64_t msi_addr; 277 uint32_t msi_data; 278 int error; 279 280 dmd = &unit->intrs[idx]; 281 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */ 282 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq); 283 if (error != 0) { 284 device_printf(dev, "cannot allocate %s interrupt, %d\n", 285 dmd->name, error); 286 goto err1; 287 } 288 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid, 289 dmd->irq, 1); 290 if (error != 0) { 291 device_printf(dev, "cannot set %s interrupt resource, %d\n", 292 dmd->name, error); 293 goto err2; 294 } 295 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 296 &dmd->irq_rid, RF_ACTIVE); 297 if (dmd->irq_res == NULL) { 298 device_printf(dev, 299 "cannot allocate resource for %s interrupt\n", dmd->name); 300 error = ENXIO; 301 goto err3; 302 } 303 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC, 304 dmd->handler, NULL, unit, &dmd->intr_handle); 305 if (error != 0) { 306 device_printf(dev, "cannot setup %s interrupt, %d\n", 307 dmd->name, error); 308 goto err4; 309 } 310 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, "%s", dmd->name); 311 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data); 312 if (error != 0) { 313 device_printf(dev, "cannot map %s interrupt, %d\n", 314 dmd->name, error); 315 goto err5; 316 } 317 dmar_write4(unit, dmd->msi_data_reg, msi_data); 318 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 319 /* Only for xAPIC mode */ 320 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 321 return (0); 322 323 err5: 324 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle); 325 err4: 326 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res); 327 err3: 328 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid); 329 err2: 330 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq); 331 dmd->irq = -1; 332 err1: 333 return (error); 334 } 335 336 #ifdef DEV_APIC 337 static int 338 dmar_remap_intr(device_t dev, device_t child, u_int irq) 339 { 340 struct dmar_unit *unit; 341 struct dmar_msi_data *dmd; 342 uint64_t msi_addr; 343 uint32_t msi_data; 344 int i, error; 345 346 unit = device_get_softc(dev); 347 for (i = 0; i < DMAR_INTR_TOTAL; i++) { 348 dmd = &unit->intrs[i]; 349 if (irq == dmd->irq) { 350 error = PCIB_MAP_MSI(device_get_parent( 351 device_get_parent(dev)), 352 dev, irq, &msi_addr, &msi_data); 353 if (error != 0) 354 return (error); 355 DMAR_LOCK(unit); 356 (dmd->disable_intr)(unit); 357 dmar_write4(unit, dmd->msi_data_reg, msi_data); 358 dmar_write4(unit, dmd->msi_addr_reg, msi_addr); 359 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32); 360 (dmd->enable_intr)(unit); 361 DMAR_UNLOCK(unit); 362 return (0); 363 } 364 } 365 return (ENOENT); 366 } 367 #endif 368 369 static void 370 dmar_print_caps(device_t dev, struct dmar_unit *unit, 371 ACPI_DMAR_HARDWARE_UNIT *dmaru) 372 { 373 uint32_t caphi, ecaphi; 374 375 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n", 376 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver), 377 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment, 378 dmaru->Flags, "\020\001INCLUDE_ALL_PCI"); 379 caphi = unit->hw_cap >> 32; 380 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap, 381 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH"); 382 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI"); 383 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d", 384 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap), 385 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap), 386 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap)); 387 if ((unit->hw_cap & DMAR_CAP_PSI) != 0) 388 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap)); 389 printf("\n"); 390 ecaphi = unit->hw_ecap >> 32; 391 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap, 392 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS" 393 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS"); 394 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS"); 395 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap), 396 DMAR_ECAP_IRO(unit->hw_ecap)); 397 } 398 399 static int 400 dmar_attach(device_t dev) 401 { 402 struct dmar_unit *unit; 403 ACPI_DMAR_HARDWARE_UNIT *dmaru; 404 uint64_t timeout; 405 int disable_pmr; 406 int i, error; 407 408 unit = device_get_softc(dev); 409 unit->dev = dev; 410 unit->iommu.unit = device_get_unit(dev); 411 unit->iommu.dev = dev; 412 dmaru = dmar_find_by_index(unit->iommu.unit); 413 if (dmaru == NULL) 414 return (EINVAL); 415 unit->segment = dmaru->Segment; 416 unit->base = dmaru->Address; 417 unit->reg_rid = DMAR_REG_RID; 418 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 419 &unit->reg_rid, RF_ACTIVE); 420 if (unit->regs == NULL) { 421 device_printf(dev, "cannot allocate register window\n"); 422 return (ENOMEM); 423 } 424 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG); 425 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG); 426 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG); 427 if (bootverbose) 428 dmar_print_caps(dev, unit, dmaru); 429 dmar_quirks_post_ident(unit); 430 431 timeout = dmar_get_timeout(); 432 TUNABLE_UINT64_FETCH("hw.iommu.dmar.timeout", &timeout); 433 dmar_update_timeout(timeout); 434 435 for (i = 0; i < DMAR_INTR_TOTAL; i++) 436 unit->intrs[i].irq = -1; 437 438 unit->intrs[DMAR_INTR_FAULT].name = "fault"; 439 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID; 440 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr; 441 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG; 442 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG; 443 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG; 444 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr; 445 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr; 446 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT); 447 if (error != 0) { 448 dmar_release_resources(dev, unit); 449 return (error); 450 } 451 if (DMAR_HAS_QI(unit)) { 452 unit->intrs[DMAR_INTR_QI].name = "qi"; 453 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID; 454 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr; 455 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG; 456 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG; 457 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG; 458 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr; 459 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr; 460 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI); 461 if (error != 0) { 462 dmar_release_resources(dev, unit); 463 return (error); 464 } 465 } 466 467 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); 468 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)), 469 &unit->iommu.lock); 470 LIST_INIT(&unit->domains); 471 472 /* 473 * 9.2 "Context Entry": 474 * When Caching Mode (CM) field is reported as Set, the 475 * domain-id value of zero is architecturally reserved. 476 * Software must not use domain-id value of zero 477 * when CM is Set. 478 */ 479 if ((unit->hw_cap & DMAR_CAP_CM) != 0) 480 alloc_unr_specific(unit->domids, 0); 481 482 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + 483 DMAR_CTX_CNT), 0, 0, NULL); 484 485 /* 486 * Allocate and load the root entry table pointer. Enable the 487 * address translation after the required invalidations are 488 * done. 489 */ 490 dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); 491 DMAR_LOCK(unit); 492 error = dmar_load_root_entry_ptr(unit); 493 if (error != 0) { 494 DMAR_UNLOCK(unit); 495 dmar_release_resources(dev, unit); 496 return (error); 497 } 498 error = dmar_inv_ctx_glob(unit); 499 if (error != 0) { 500 DMAR_UNLOCK(unit); 501 dmar_release_resources(dev, unit); 502 return (error); 503 } 504 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) { 505 error = dmar_inv_iotlb_glob(unit); 506 if (error != 0) { 507 DMAR_UNLOCK(unit); 508 dmar_release_resources(dev, unit); 509 return (error); 510 } 511 } 512 513 DMAR_UNLOCK(unit); 514 error = dmar_init_fault_log(unit); 515 if (error != 0) { 516 dmar_release_resources(dev, unit); 517 return (error); 518 } 519 error = dmar_init_qi(unit); 520 if (error != 0) { 521 dmar_release_resources(dev, unit); 522 return (error); 523 } 524 error = dmar_init_irt(unit); 525 if (error != 0) { 526 dmar_release_resources(dev, unit); 527 return (error); 528 } 529 530 disable_pmr = 0; 531 TUNABLE_INT_FETCH("hw.dmar.pmr.disable", &disable_pmr); 532 if (disable_pmr) { 533 error = dmar_disable_protected_regions(unit); 534 if (error != 0) 535 device_printf(dev, 536 "Failed to disable protected regions\n"); 537 } 538 539 error = iommu_init_busdma(&unit->iommu); 540 if (error != 0) { 541 dmar_release_resources(dev, unit); 542 return (error); 543 } 544 545 #ifdef NOTYET 546 DMAR_LOCK(unit); 547 error = dmar_enable_translation(unit); 548 if (error != 0) { 549 DMAR_UNLOCK(unit); 550 dmar_release_resources(dev, unit); 551 return (error); 552 } 553 DMAR_UNLOCK(unit); 554 #endif 555 556 return (0); 557 } 558 559 static int 560 dmar_detach(device_t dev) 561 { 562 563 return (EBUSY); 564 } 565 566 static int 567 dmar_suspend(device_t dev) 568 { 569 570 return (0); 571 } 572 573 static int 574 dmar_resume(device_t dev) 575 { 576 577 /* XXXKIB */ 578 return (0); 579 } 580 581 static device_method_t dmar_methods[] = { 582 DEVMETHOD(device_identify, dmar_identify), 583 DEVMETHOD(device_probe, dmar_probe), 584 DEVMETHOD(device_attach, dmar_attach), 585 DEVMETHOD(device_detach, dmar_detach), 586 DEVMETHOD(device_suspend, dmar_suspend), 587 DEVMETHOD(device_resume, dmar_resume), 588 #ifdef DEV_APIC 589 DEVMETHOD(bus_remap_intr, dmar_remap_intr), 590 #endif 591 DEVMETHOD_END 592 }; 593 594 static driver_t dmar_driver = { 595 "dmar", 596 dmar_methods, 597 sizeof(struct dmar_unit), 598 }; 599 600 DRIVER_MODULE(dmar, acpi, dmar_driver, 0, 0); 601 MODULE_DEPEND(dmar, acpi, 1, 1, 1); 602 603 static void 604 dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path) 605 { 606 int i; 607 608 printf("[%d, ", busno); 609 for (i = 0; i < depth; i++) { 610 if (i != 0) 611 printf(", "); 612 printf("(%d, %d)", path[i].Device, path[i].Function); 613 } 614 printf("]"); 615 } 616 617 int 618 dmar_dev_depth(device_t child) 619 { 620 devclass_t pci_class; 621 device_t bus, pcib; 622 int depth; 623 624 pci_class = devclass_find("pci"); 625 for (depth = 1; ; depth++) { 626 bus = device_get_parent(child); 627 pcib = device_get_parent(bus); 628 if (device_get_devclass(device_get_parent(pcib)) != 629 pci_class) 630 return (depth); 631 child = pcib; 632 } 633 } 634 635 void 636 dmar_dev_path(device_t child, int *busno, void *path1, int depth) 637 { 638 devclass_t pci_class; 639 device_t bus, pcib; 640 ACPI_DMAR_PCI_PATH *path; 641 642 pci_class = devclass_find("pci"); 643 path = path1; 644 for (depth--; depth != -1; depth--) { 645 path[depth].Device = pci_get_slot(child); 646 path[depth].Function = pci_get_function(child); 647 bus = device_get_parent(child); 648 pcib = device_get_parent(bus); 649 if (device_get_devclass(device_get_parent(pcib)) != 650 pci_class) { 651 /* reached a host bridge */ 652 *busno = pcib_get_bus(bus); 653 return; 654 } 655 child = pcib; 656 } 657 panic("wrong depth"); 658 } 659 660 static int 661 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1, 662 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2, 663 enum AcpiDmarScopeType scope_type) 664 { 665 int i, depth; 666 667 if (busno1 != busno2) 668 return (0); 669 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2) 670 return (0); 671 depth = depth1; 672 if (depth2 < depth) 673 depth = depth2; 674 for (i = 0; i < depth; i++) { 675 if (path1[i].Device != path2[i].Device || 676 path1[i].Function != path2[i].Function) 677 return (0); 678 } 679 return (1); 680 } 681 682 static int 683 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, int dev_busno, 684 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 685 { 686 ACPI_DMAR_PCI_PATH *path; 687 int path_len; 688 689 if (devscope->Length < sizeof(*devscope)) { 690 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 691 devscope->Length); 692 return (-1); 693 } 694 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && 695 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE) 696 return (0); 697 path_len = devscope->Length - sizeof(*devscope); 698 if (path_len % 2 != 0) { 699 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 700 devscope->Length); 701 return (-1); 702 } 703 path_len /= 2; 704 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1); 705 if (path_len == 0) { 706 printf("dmar_match_devscope: corrupted DMAR table, dl %d\n", 707 devscope->Length); 708 return (-1); 709 } 710 711 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno, 712 dev_path, dev_path_len, devscope->EntryType)); 713 } 714 715 static bool 716 dmar_match_by_path(struct dmar_unit *unit, int dev_domain, int dev_busno, 717 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len, const char **banner) 718 { 719 ACPI_DMAR_HARDWARE_UNIT *dmarh; 720 ACPI_DMAR_DEVICE_SCOPE *devscope; 721 char *ptr, *ptrend; 722 int match; 723 724 dmarh = dmar_find_by_index(unit->iommu.unit); 725 if (dmarh == NULL) 726 return (false); 727 if (dmarh->Segment != dev_domain) 728 return (false); 729 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) { 730 if (banner != NULL) 731 *banner = "INCLUDE_ALL"; 732 return (true); 733 } 734 ptr = (char *)dmarh + sizeof(*dmarh); 735 ptrend = (char *)dmarh + dmarh->Header.Length; 736 while (ptr < ptrend) { 737 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 738 ptr += devscope->Length; 739 match = dmar_match_devscope(devscope, dev_busno, dev_path, 740 dev_path_len); 741 if (match == -1) 742 return (false); 743 if (match == 1) { 744 if (banner != NULL) 745 *banner = "specific match"; 746 return (true); 747 } 748 } 749 return (false); 750 } 751 752 static struct dmar_unit * 753 dmar_find_by_scope(int dev_domain, int dev_busno, 754 const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len) 755 { 756 struct dmar_unit *unit; 757 int i; 758 759 for (i = 0; i < dmar_devcnt; i++) { 760 if (dmar_devs[i] == NULL) 761 continue; 762 unit = device_get_softc(dmar_devs[i]); 763 if (dmar_match_by_path(unit, dev_domain, dev_busno, dev_path, 764 dev_path_len, NULL)) 765 return (unit); 766 } 767 return (NULL); 768 } 769 770 struct dmar_unit * 771 dmar_find(device_t dev, bool verbose) 772 { 773 struct dmar_unit *unit; 774 const char *banner; 775 int i, dev_domain, dev_busno, dev_path_len; 776 777 /* 778 * This function can only handle PCI(e) devices. 779 */ 780 if (device_get_devclass(device_get_parent(dev)) != 781 devclass_find("pci")) 782 return (NULL); 783 784 dev_domain = pci_get_domain(dev); 785 dev_path_len = dmar_dev_depth(dev); 786 ACPI_DMAR_PCI_PATH dev_path[dev_path_len]; 787 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len); 788 banner = ""; 789 790 for (i = 0; i < dmar_devcnt; i++) { 791 if (dmar_devs[i] == NULL) 792 continue; 793 unit = device_get_softc(dmar_devs[i]); 794 if (dmar_match_by_path(unit, dev_domain, dev_busno, 795 dev_path, dev_path_len, &banner)) 796 break; 797 } 798 if (i == dmar_devcnt) 799 return (NULL); 800 801 if (verbose) { 802 device_printf(dev, "pci%d:%d:%d:%d matched dmar%d by %s", 803 dev_domain, pci_get_bus(dev), pci_get_slot(dev), 804 pci_get_function(dev), unit->iommu.unit, banner); 805 printf(" scope path "); 806 dmar_print_path(dev_busno, dev_path_len, dev_path); 807 printf("\n"); 808 } 809 return (unit); 810 } 811 812 static struct dmar_unit * 813 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid) 814 { 815 device_t dmar_dev; 816 struct dmar_unit *unit; 817 ACPI_DMAR_HARDWARE_UNIT *dmarh; 818 ACPI_DMAR_DEVICE_SCOPE *devscope; 819 ACPI_DMAR_PCI_PATH *path; 820 char *ptr, *ptrend; 821 #ifdef DEV_APIC 822 int error; 823 #endif 824 int i; 825 826 for (i = 0; i < dmar_devcnt; i++) { 827 dmar_dev = dmar_devs[i]; 828 if (dmar_dev == NULL) 829 continue; 830 unit = (struct dmar_unit *)device_get_softc(dmar_dev); 831 dmarh = dmar_find_by_index(i); 832 if (dmarh == NULL) 833 continue; 834 ptr = (char *)dmarh + sizeof(*dmarh); 835 ptrend = (char *)dmarh + dmarh->Header.Length; 836 for (;;) { 837 if (ptr >= ptrend) 838 break; 839 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 840 ptr += devscope->Length; 841 if (devscope->EntryType != entry_type) 842 continue; 843 if (devscope->EnumerationId != id) 844 continue; 845 #ifdef DEV_APIC 846 if (entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { 847 error = ioapic_get_rid(id, rid); 848 /* 849 * If our IOAPIC has PCI bindings then 850 * use the PCI device rid. 851 */ 852 if (error == 0) 853 return (unit); 854 } 855 #endif 856 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE) 857 == 2) { 858 if (rid != NULL) { 859 path = (ACPI_DMAR_PCI_PATH *) 860 (devscope + 1); 861 *rid = PCI_RID(devscope->Bus, 862 path->Device, path->Function); 863 } 864 return (unit); 865 } 866 printf( 867 "dmar_find_nonpci: id %d type %d path length != 2\n", 868 id, entry_type); 869 break; 870 } 871 } 872 return (NULL); 873 } 874 875 struct dmar_unit * 876 dmar_find_hpet(device_t dev, uint16_t *rid) 877 { 878 879 return (dmar_find_nonpci(hpet_get_uid(dev), ACPI_DMAR_SCOPE_TYPE_HPET, 880 rid)); 881 } 882 883 struct dmar_unit * 884 dmar_find_ioapic(u_int apic_id, uint16_t *rid) 885 { 886 887 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid)); 888 } 889 890 struct rmrr_iter_args { 891 struct dmar_domain *domain; 892 int dev_domain; 893 int dev_busno; 894 const ACPI_DMAR_PCI_PATH *dev_path; 895 int dev_path_len; 896 struct iommu_map_entries_tailq *rmrr_entries; 897 }; 898 899 static int 900 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 901 { 902 struct rmrr_iter_args *ria; 903 ACPI_DMAR_RESERVED_MEMORY *resmem; 904 ACPI_DMAR_DEVICE_SCOPE *devscope; 905 struct iommu_map_entry *entry; 906 char *ptr, *ptrend; 907 int match; 908 909 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 910 return (1); 911 912 ria = arg; 913 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 914 if (resmem->Segment != ria->dev_domain) 915 return (1); 916 917 ptr = (char *)resmem + sizeof(*resmem); 918 ptrend = (char *)resmem + resmem->Header.Length; 919 for (;;) { 920 if (ptr >= ptrend) 921 break; 922 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; 923 ptr += devscope->Length; 924 match = dmar_match_devscope(devscope, ria->dev_busno, 925 ria->dev_path, ria->dev_path_len); 926 if (match == 1) { 927 entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), 928 IOMMU_PGF_WAITOK); 929 entry->start = resmem->BaseAddress; 930 /* The RMRR entry end address is inclusive. */ 931 entry->end = resmem->EndAddress; 932 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, 933 dmamap_link); 934 } 935 } 936 937 return (1); 938 } 939 940 void 941 dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain, int dev_busno, 942 const void *dev_path, int dev_path_len, 943 struct iommu_map_entries_tailq *rmrr_entries) 944 { 945 struct rmrr_iter_args ria; 946 947 ria.domain = domain; 948 ria.dev_domain = dev_domain; 949 ria.dev_busno = dev_busno; 950 ria.dev_path = (const ACPI_DMAR_PCI_PATH *)dev_path; 951 ria.dev_path_len = dev_path_len; 952 ria.rmrr_entries = rmrr_entries; 953 dmar_iterate_tbl(dmar_rmrr_iter, &ria); 954 } 955 956 struct inst_rmrr_iter_args { 957 struct dmar_unit *dmar; 958 }; 959 960 static device_t 961 dmar_path_dev(int segment, int path_len, int busno, 962 const ACPI_DMAR_PCI_PATH *path, uint16_t *rid) 963 { 964 device_t dev; 965 int i; 966 967 dev = NULL; 968 for (i = 0; i < path_len; i++) { 969 dev = pci_find_dbsf(segment, busno, path->Device, 970 path->Function); 971 if (i != path_len - 1) { 972 busno = pci_cfgregread(segment, busno, path->Device, 973 path->Function, PCIR_SECBUS_1, 1); 974 path++; 975 } 976 } 977 *rid = PCI_RID(busno, path->Device, path->Function); 978 return (dev); 979 } 980 981 static int 982 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) 983 { 984 const ACPI_DMAR_RESERVED_MEMORY *resmem; 985 const ACPI_DMAR_DEVICE_SCOPE *devscope; 986 struct inst_rmrr_iter_args *iria; 987 const char *ptr, *ptrend; 988 device_t dev; 989 struct dmar_unit *unit; 990 int dev_path_len; 991 uint16_t rid; 992 993 iria = arg; 994 995 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY) 996 return (1); 997 998 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh; 999 if (resmem->Segment != iria->dmar->segment) 1000 return (1); 1001 1002 ptr = (const char *)resmem + sizeof(*resmem); 1003 ptrend = (const char *)resmem + resmem->Header.Length; 1004 for (;;) { 1005 if (ptr >= ptrend) 1006 break; 1007 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr; 1008 ptr += devscope->Length; 1009 /* XXXKIB bridge */ 1010 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT) 1011 continue; 1012 rid = 0; 1013 dev_path_len = (devscope->Length - 1014 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2; 1015 dev = dmar_path_dev(resmem->Segment, dev_path_len, 1016 devscope->Bus, 1017 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), &rid); 1018 if (dev == NULL) { 1019 if (bootverbose) { 1020 printf("dmar%d no dev found for RMRR " 1021 "[%#jx, %#jx] rid %#x scope path ", 1022 iria->dmar->iommu.unit, 1023 (uintmax_t)resmem->BaseAddress, 1024 (uintmax_t)resmem->EndAddress, 1025 rid); 1026 dmar_print_path(devscope->Bus, dev_path_len, 1027 (const ACPI_DMAR_PCI_PATH *)(devscope + 1)); 1028 printf("\n"); 1029 } 1030 unit = dmar_find_by_scope(resmem->Segment, 1031 devscope->Bus, 1032 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1033 dev_path_len); 1034 if (iria->dmar != unit) 1035 continue; 1036 dmar_get_ctx_for_devpath(iria->dmar, rid, 1037 resmem->Segment, devscope->Bus, 1038 (const ACPI_DMAR_PCI_PATH *)(devscope + 1), 1039 dev_path_len, false, true); 1040 } else { 1041 unit = dmar_find(dev, false); 1042 if (iria->dmar != unit) 1043 continue; 1044 iommu_instantiate_ctx(&(iria)->dmar->iommu, 1045 dev, true); 1046 } 1047 } 1048 1049 return (1); 1050 1051 } 1052 1053 /* 1054 * Pre-create all contexts for the DMAR which have RMRR entries. 1055 */ 1056 int 1057 dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) 1058 { 1059 struct dmar_unit *dmar; 1060 struct inst_rmrr_iter_args iria; 1061 int error; 1062 1063 dmar = IOMMU2DMAR(unit); 1064 1065 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) 1066 return (0); 1067 1068 error = 0; 1069 iria.dmar = dmar; 1070 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria); 1071 DMAR_LOCK(dmar); 1072 if (!LIST_EMPTY(&dmar->domains)) { 1073 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0, 1074 ("dmar%d: RMRR not handled but translation is already enabled", 1075 dmar->iommu.unit)); 1076 error = dmar_disable_protected_regions(dmar); 1077 if (error != 0) 1078 printf("dmar%d: Failed to disable protected regions\n", 1079 dmar->iommu.unit); 1080 error = dmar_enable_translation(dmar); 1081 if (bootverbose) { 1082 if (error == 0) { 1083 printf("dmar%d: enabled translation\n", 1084 dmar->iommu.unit); 1085 } else { 1086 printf("dmar%d: enabling translation failed, " 1087 "error %d\n", dmar->iommu.unit, error); 1088 } 1089 } 1090 } 1091 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR); 1092 return (error); 1093 } 1094 1095 #ifdef DDB 1096 #include <ddb/ddb.h> 1097 #include <ddb/db_lex.h> 1098 1099 static void 1100 dmar_print_domain_entry(const struct iommu_map_entry *entry) 1101 { 1102 struct iommu_map_entry *l, *r; 1103 1104 db_printf( 1105 " start %jx end %jx first %jx last %jx free_down %jx flags %x ", 1106 entry->start, entry->end, entry->first, entry->last, 1107 entry->free_down, entry->flags); 1108 db_printf("left "); 1109 l = RB_LEFT(entry, rb_entry); 1110 if (l == NULL) 1111 db_printf("NULL "); 1112 else 1113 db_printf("%jx ", l->start); 1114 db_printf("right "); 1115 r = RB_RIGHT(entry, rb_entry); 1116 if (r == NULL) 1117 db_printf("NULL"); 1118 else 1119 db_printf("%jx", r->start); 1120 db_printf("\n"); 1121 } 1122 1123 static void 1124 dmar_print_ctx(struct dmar_ctx *ctx) 1125 { 1126 1127 db_printf( 1128 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n", 1129 ctx, pci_get_bus(ctx->context.tag->owner), 1130 pci_get_slot(ctx->context.tag->owner), 1131 pci_get_function(ctx->context.tag->owner), ctx->refs, 1132 ctx->context.flags, ctx->context.loads, ctx->context.unloads); 1133 } 1134 1135 static void 1136 dmar_print_domain(struct dmar_domain *domain, bool show_mappings) 1137 { 1138 struct iommu_domain *iodom; 1139 struct iommu_map_entry *entry; 1140 struct dmar_ctx *ctx; 1141 1142 iodom = DOM2IODOM(domain); 1143 1144 db_printf( 1145 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" 1146 " ctx_cnt %d flags %x pgobj %p map_ents %u\n", 1147 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl, 1148 (uintmax_t)domain->iodom.end, domain->refs, domain->ctx_cnt, 1149 domain->iodom.flags, domain->pgtbl_obj, domain->iodom.entries_cnt); 1150 if (!LIST_EMPTY(&domain->contexts)) { 1151 db_printf(" Contexts:\n"); 1152 LIST_FOREACH(ctx, &domain->contexts, link) 1153 dmar_print_ctx(ctx); 1154 } 1155 if (!show_mappings) 1156 return; 1157 db_printf(" mapped:\n"); 1158 RB_FOREACH(entry, iommu_gas_entries_tree, &iodom->rb_root) { 1159 dmar_print_domain_entry(entry); 1160 if (db_pager_quit) 1161 break; 1162 } 1163 if (db_pager_quit) 1164 return; 1165 db_printf(" unloading:\n"); 1166 TAILQ_FOREACH(entry, &domain->iodom.unload_entries, dmamap_link) { 1167 dmar_print_domain_entry(entry); 1168 if (db_pager_quit) 1169 break; 1170 } 1171 } 1172 1173 DB_SHOW_COMMAND_FLAGS(dmar_domain, db_dmar_print_domain, CS_OWN) 1174 { 1175 struct dmar_unit *unit; 1176 struct dmar_domain *domain; 1177 struct dmar_ctx *ctx; 1178 bool show_mappings, valid; 1179 int pci_domain, bus, device, function, i, t; 1180 db_expr_t radix; 1181 1182 valid = false; 1183 radix = db_radix; 1184 db_radix = 10; 1185 t = db_read_token(); 1186 if (t == tSLASH) { 1187 t = db_read_token(); 1188 if (t != tIDENT) { 1189 db_printf("Bad modifier\n"); 1190 db_radix = radix; 1191 db_skip_to_eol(); 1192 return; 1193 } 1194 show_mappings = strchr(db_tok_string, 'm') != NULL; 1195 t = db_read_token(); 1196 } else { 1197 show_mappings = false; 1198 } 1199 if (t == tNUMBER) { 1200 pci_domain = db_tok_number; 1201 t = db_read_token(); 1202 if (t == tNUMBER) { 1203 bus = db_tok_number; 1204 t = db_read_token(); 1205 if (t == tNUMBER) { 1206 device = db_tok_number; 1207 t = db_read_token(); 1208 if (t == tNUMBER) { 1209 function = db_tok_number; 1210 valid = true; 1211 } 1212 } 1213 } 1214 } 1215 db_radix = radix; 1216 db_skip_to_eol(); 1217 if (!valid) { 1218 db_printf("usage: show dmar_domain [/m] " 1219 "<domain> <bus> <device> <func>\n"); 1220 return; 1221 } 1222 for (i = 0; i < dmar_devcnt; i++) { 1223 unit = device_get_softc(dmar_devs[i]); 1224 LIST_FOREACH(domain, &unit->domains, link) { 1225 LIST_FOREACH(ctx, &domain->contexts, link) { 1226 if (pci_domain == unit->segment && 1227 bus == pci_get_bus(ctx->context.tag->owner) && 1228 device == 1229 pci_get_slot(ctx->context.tag->owner) && 1230 function == 1231 pci_get_function(ctx->context.tag->owner)) { 1232 dmar_print_domain(domain, 1233 show_mappings); 1234 goto out; 1235 } 1236 } 1237 } 1238 } 1239 out:; 1240 } 1241 1242 static void 1243 dmar_print_one(int idx, bool show_domains, bool show_mappings) 1244 { 1245 struct dmar_unit *unit; 1246 struct dmar_domain *domain; 1247 int i, frir; 1248 1249 unit = device_get_softc(dmar_devs[idx]); 1250 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->iommu.unit, 1251 unit, dmar_read8(unit, DMAR_RTADDR_REG), 1252 dmar_read4(unit, DMAR_VER_REG)); 1253 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n", 1254 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG), 1255 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG), 1256 dmar_read4(unit, DMAR_GSTS_REG), 1257 dmar_read4(unit, DMAR_FSTS_REG), 1258 dmar_read4(unit, DMAR_FECTL_REG)); 1259 if (unit->ir_enabled) { 1260 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n", 1261 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt); 1262 } 1263 db_printf("fed 0x%x fea 0x%x feua 0x%x\n", 1264 dmar_read4(unit, DMAR_FEDATA_REG), 1265 dmar_read4(unit, DMAR_FEADDR_REG), 1266 dmar_read4(unit, DMAR_FEUADDR_REG)); 1267 db_printf("primary fault log:\n"); 1268 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) { 1269 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16; 1270 db_printf(" %d at 0x%x: %jx %jx\n", i, frir, 1271 (uintmax_t)dmar_read8(unit, frir), 1272 (uintmax_t)dmar_read8(unit, frir + 8)); 1273 } 1274 if (DMAR_HAS_QI(unit)) { 1275 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n", 1276 dmar_read4(unit, DMAR_IEDATA_REG), 1277 dmar_read4(unit, DMAR_IEADDR_REG), 1278 dmar_read4(unit, DMAR_IEUADDR_REG)); 1279 if (unit->qi_enabled) { 1280 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) " 1281 "size 0x%jx\n" 1282 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n" 1283 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n", 1284 (uintmax_t)unit->inv_queue, 1285 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG), 1286 (uintmax_t)unit->inv_queue_size, 1287 dmar_read4(unit, DMAR_IQH_REG), 1288 dmar_read4(unit, DMAR_IQT_REG), 1289 unit->inv_queue_avail, 1290 dmar_read4(unit, DMAR_ICS_REG), 1291 dmar_read4(unit, DMAR_IECTL_REG), 1292 unit->inv_waitd_seq_hw, 1293 &unit->inv_waitd_seq_hw, 1294 (uintmax_t)unit->inv_waitd_seq_hw_phys, 1295 unit->inv_waitd_seq, 1296 unit->inv_waitd_gen); 1297 } else { 1298 db_printf("qi is disabled\n"); 1299 } 1300 } 1301 if (show_domains) { 1302 db_printf("domains:\n"); 1303 LIST_FOREACH(domain, &unit->domains, link) { 1304 dmar_print_domain(domain, show_mappings); 1305 if (db_pager_quit) 1306 break; 1307 } 1308 } 1309 } 1310 1311 DB_SHOW_COMMAND(dmar, db_dmar_print) 1312 { 1313 bool show_domains, show_mappings; 1314 1315 show_domains = strchr(modif, 'd') != NULL; 1316 show_mappings = strchr(modif, 'm') != NULL; 1317 if (!have_addr) { 1318 db_printf("usage: show dmar [/d] [/m] index\n"); 1319 return; 1320 } 1321 dmar_print_one((int)addr, show_domains, show_mappings); 1322 } 1323 1324 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars) 1325 { 1326 int i; 1327 bool show_domains, show_mappings; 1328 1329 show_domains = strchr(modif, 'd') != NULL; 1330 show_mappings = strchr(modif, 'm') != NULL; 1331 1332 for (i = 0; i < dmar_devcnt; i++) { 1333 dmar_print_one(i, show_domains, show_mappings); 1334 if (db_pager_quit) 1335 break; 1336 } 1337 } 1338 #endif 1339 1340 struct iommu_unit * 1341 iommu_find(device_t dev, bool verbose) 1342 { 1343 struct dmar_unit *dmar; 1344 1345 dmar = dmar_find(dev, verbose); 1346 1347 return (&dmar->iommu); 1348 } 1349